From nobody Tue Apr 7 01:36:56 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 831D03D5251 for ; Fri, 3 Apr 2026 16:10:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775232606; cv=none; b=sQRbcHfYiasWfeqsPMxhqO4Z/A0e+Equ2Bp+9SfSiDFjPjGrz/02N0wpMLguFT4IZs84MnjB5sg0PahUFbea6D+13SZUIGk+xl1TyYlH6BjhCbCmFfhrI1RhCU4CwOrsn3akWGoPv6n3Cet1CTCn6OF2mt/ClsH1pj6OR8eCj6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775232606; c=relaxed/simple; bh=Y83KYn/IVlv0CuC1jWDIk1uUyPw9VZxig3d2hhCSWLk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dxODHTUTIN+9HUdyqpxhOfjr7JmGwpJSA+tv0OISHedCHi8KLwe0+kGHoEWhimunMHH0EsduyJ/KCLMLmCkPdG8aBVG/H2a6PR4pQLhDACQL57R8ZL2P0kdT10/zBpPbAshUKIwYLLndb4dbRmTiWeMiFa8oYs1mbeFuDpJTfpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=fX0TW3G+; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fX0TW3G+" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 092911A312B; Fri, 3 Apr 2026 16:10:04 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CC75B603C1; Fri, 3 Apr 2026 16:10:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3796A104500FB; Fri, 3 Apr 2026 18:10:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1775232602; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8PfJAvOeYuhH5dbaDKJSTXCqDQ9KrVUp5a2zaIJVtqQ=; b=fX0TW3G+QCtp4oSRisM4uUPTCgxO0PWqGemlRIr5nkFNOHaoSzkduz4HpALyNhrYLSq8/F kGdMa5s3r718SBxAkzFC/oda64BcExkVZ4ZZGV2f7IZLyesthcuL2kXtBQnW1R0UccIlf0 slDX60Mz/1xNX6zErIDZnwBmC8Y01TPWCDH/JZ/uHHAaw5glgP918C7Rk6WHQHzjv/Oblj LJI4abbCNTT4UKd7Jyte5s8C2jbD8q8IeVkzjwLaDT5wP4aJMfRHDqF6MxzzB2DiIyuuPL RO8y4kgbaw4xBzGXVohvHl83fX3AdLQ0FUgHy7QRpmFOxyu/Y04Sh1/koj3bHQ== From: Miquel Raynal Date: Fri, 03 Apr 2026 18:09:29 +0200 Subject: [PATCH v4 11/27] mtd: spi-nor: swp: Rename a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-11-833dab5e7288@bootlin.com> References: <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-0-833dab5e7288@bootlin.com> In-Reply-To: <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-0-833dab5e7288@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 "mask" is not very descriptive when we already manipulate two masks, and soon will manipulate three. Rename it "bp_mask" to align with the existing "tb_mask" and soon "cmp_mask". Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index af6e577d9b42..66f85826ba0d 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -57,9 +57,9 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ u64 *len) { u64 min_prot_len; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr[0] & mask; + u8 bp, val =3D sr[0] & bp_mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -160,7 +160,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -199,7 +199,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) lock_len =3D ofs + len; =20 if (lock_len =3D=3D nor->params->size) { - val =3D mask; + val =3D bp_mask; } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; @@ -208,15 +208,15 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; =20 /* Don't "lock" with no region! */ - if (!(val & mask)) + if (!(val & bp_mask)) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -234,7 +234,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new[0] & mask) < (status_old[0] & mask)) + if ((status_new[0] & bp_mask) < (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); @@ -250,7 +250,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1], status_new[1]; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -306,11 +306,11 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 /* Some power-of-two sizes may not be supported */ - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) @@ -324,7 +324,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new[0] & mask) > (status_old[0] & mask)) + if ((status_new[0] & bp_mask) > (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); --=20 2.53.0