From nobody Tue Apr 7 12:23:23 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14FB83D3324 for ; Fri, 3 Apr 2026 17:33:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775237635; cv=none; b=DZwQAJmvNJD7Js2obybfIpvQoqWDL1C38rjFkorhOnbyronRa43kBgDA5QNmlLyaeuB2xdq4DVUGeugJRZ6MAmnVmG2BTevhSlinF1bDv3sM5nGfRsOPkzP2l/jk+06rbJgtqT6DIAOYkUyMA/MThosklZLONQVrJFwtngkVHb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775237635; c=relaxed/simple; bh=rZiOZBnfnYQhiYHGIxAvJ9diYifTV8qWwPU2z0ofvp8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U7TkeI2TfWAQvXPZriA5ipvV9ZjT/5f8SkKeRzoLFbjZzy1smBfNmeWV8F7B+ldZSBhGsel38m0yeYD5DGHJIt/P5oQZmAoYak/8E10gWLwmaqyd9VwnCH9+XJgTxm1kPe2wyRCQeZAs9Vs0DmUVX+j4qD1CCqIAaicEmRxKwZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=dqeG9Sey; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ZbbbTCxU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="dqeG9Sey"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ZbbbTCxU" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 633AxPEV3803870 for ; Fri, 3 Apr 2026 17:33:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vcScscqC6ncRDOFK8ujM+tWz/LTHnr7UQ8J+Pxb8j2M=; b=dqeG9SeyGxu65jgn 253UAbPLB45tHnHRPFfTb/GgGF91MtPxXdQq9uG9TLgV7Li7MPEnJ+fGGDm19+9D LKQzsJSTvzU7HA58w6YY+idGppBEOqgKRjEruPFJ4bx7kubqHIBmV5XUnimaZF1f T4G9xk6lruJrqDo4oGpSBeXzde097t0BKCCczSNrJ89+W8ZhHGyiUpFVjMkaL38k jWJOxNlqaju4iu1PE/o4wN1CTer43klBXDPb7iV7EJGarsIav29LrGyNKbY/llUa nZFcYqhjoUdH0HouloI+Wjp6nUliGgMREX6BV9obnJ1DEeLRt9IeB4LC1pCxob4a MPBAMw== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dac9f92f1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 03 Apr 2026 17:33:53 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-82c83bd48afso1281027b3a.3 for ; Fri, 03 Apr 2026 10:33:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775237632; x=1775842432; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vcScscqC6ncRDOFK8ujM+tWz/LTHnr7UQ8J+Pxb8j2M=; b=ZbbbTCxUPux32ouelSa9A+YIR6HQqc4H9hK/BpauqanbAX/jM/19ShdZicY1F0XHYs a2v31cWFNqSMFt4/e4qi7sEdJQFjCj1QRo0Ak3alMyoh0b9ReHZXL/ts+I1ecIP/qDAX QznienB9+frejc5fv5nzGQMHUy8kNYfXO4cofqlk0AhCwyRxjT1voPvSKaGf6ZJsE1ds f+O8+94NTtzjCuAmWjchN8haFj02lCC6PGu0BhNqwOUGRNBYDcwXHg0mLd/a2tQYFgWM DA987bXJ795Zwc09Zv9KX1WWEruo02QWPLfNdSc206Bj86cAlTnq3g0+QvDMPHKA803c 083w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775237632; x=1775842432; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=vcScscqC6ncRDOFK8ujM+tWz/LTHnr7UQ8J+Pxb8j2M=; b=Ravp+Shg9YesPNe85FCa2Lf9rlAZCaHztUIi2uHlMIAoZS+AGuw1kCro1O6R6UXpX5 ndu1B93lgxUG8nyxBTrqPymfmzi3cyveo+hLh1snNG7Nvj1jYuy8OOw01utkYBe2u5xg 7L+89aU3oEcioKF/ZNusDT7Em6QH8UHfMicLTjSNxiLwT0eKVbLcvRmu4sc/DCnX85+P rV8NzefJOgz45dLS+1k0rcEGaZZzMQbzi8wfNdPQsVyfCA0A6F1AFu8qc0ao1EbjBTSv Picwdu7Tsp/sY4jWwNfQaX2B7Clj7idkBxrA8q7VVA9w76wHt1sdKlVKiKmYBpda2mgg 6uHg== X-Forwarded-Encrypted: i=1; AJvYcCVgsU8NDzYgqqj0lVSQJgeH+Ian3HpqcxiLyFUVTLvVYZA+3fWiHonTflNBukSLN9V+bA4SugtE4BFwYaM=@vger.kernel.org X-Gm-Message-State: AOJu0YwF8EI7qVjiTO4al1MmAbGywXBBO/vIz1NShVPv4Cd6/6NkHB4S YmRHz9Va5MCrSoGApqpn9Tl7k4itgoGBajQ51SccF8zdDdbTxyrvw3hc9axZmq6QwFmirzAVLNZ YYE6uYt3XrZR41DdK8gRMJuR456XR31iwdyFGfD8V9Rr+SxZxxI3H81h8wZ/YxSgDB9s= X-Gm-Gg: AeBDiesIn3dXOsS8D8R3iwUFqGzllMS+Lei/Mu5+A/jzUQSqQuZxnNsLXaRLc0NlhQy K40KLsHxH7DdQd51ip6SSDZhnz0wPsJuJSmsDOlkwhIqSTCA8n0o1N+rRJOS5UA/7g0mpIvNSG5 eNhg9saKL1KjFpGgAVdNpP50wrRqQBefAi4QTKbiu4tsUZDYetBsSIMUhYjyYTEpMJCJn6PaOwM 5Kx70lp8UFeLPGNSDQmmaAGcQnzbB4j1YKu4ecxCzvfayjnhftacoESUki1YLg+FTFn6Er+DzKo kL23mus78nJSTJ0EHogLbvC/Qllf93qnO1hqPBdd9iggk2oWRX36nbz7w4xziBr8ZAAkMrVMtDo V4RN5w/Pu4qsW9cF1RawqUhYe65rGEd26+UASaQwrV8rYMxLUoPeU3gG4 X-Received: by 2002:a05:6a00:4513:b0:824:a0b9:64ee with SMTP id d2e1a72fcca58-82d0da6701bmr3354482b3a.17.1775237632095; Fri, 03 Apr 2026 10:33:52 -0700 (PDT) X-Received: by 2002:a05:6a00:4513:b0:824:a0b9:64ee with SMTP id d2e1a72fcca58-82d0da6701bmr3354465b3a.17.1775237631551; Fri, 03 Apr 2026 10:33:51 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82cf9b3e169sm6359125b3a.18.2026.04.03.10.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 10:33:51 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 03 Apr 2026 23:03:33 +0530 Subject: [PATCH v9 1/3] PM: sleep: wakeirq: Add support for dedicated shared wake IRQ setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-wakeirq_support-v9-1-1cbecf3b58d7@oss.qualcomm.com> References: <20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com> In-Reply-To: <20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com> To: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Greg Kroah-Hartman , Danilo Krummrich , Bjorn Helgaas , Bartosz Golaszewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Saravana Kannan , Linus Walleij Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, quic_vbadigan@quicinc.com, sherry.sun@nxp.com, driver-core@lists.linux.dev, devicetree@vger.kernel.org, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775237619; l=4919; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=rZiOZBnfnYQhiYHGIxAvJ9diYifTV8qWwPU2z0ofvp8=; b=AtVe7Za3lH9ooZtSOFwQ+ddqgaaMkLKTsqDn9qYDBQyyFK+dX9FjNqWehwfP9dUX65Fmih+Dq T8CyWBsudwtARHgL1Bug5or/c6NzndI5Bwt1VErpm+i0QrfSWhK0PlH X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 4ddzdDiBPiVmGuT96yDDfOmN6i-Ii9b5 X-Proofpoint-ORIG-GUID: 4ddzdDiBPiVmGuT96yDDfOmN6i-Ii9b5 X-Authority-Analysis: v=2.4 cv=BO++bVQG c=1 sm=1 tr=0 ts=69cffa01 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=GqrSgIjjxmp09zFQf4gA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDE1NiBTYWx0ZWRfX123EVHght0uX M3M3Zq0yn2KHj2GkM3Nb+QnnS3wmOKqL4MVG57xYHWTGJxEy3Wkg6qQOclj/vCWz16UK4QIs1zN PVCQKfpuRusVlFBT2cEb5KnjvzDK9P5IsjyPgUppjPGWZB91FW4gXfbRN1hrXyHDVbP4GAagJ3d Q60j4ez1oSy4HFEwBVkAE2RZEPhwUqrjFpzHb/GOzl7B83D8ltC8HDE57JCzilNToB0Q6iPqbvm +5TQF8MKX4IwWYvi41KKXfvqSffqnYsNStbw1soydaMtJWk+hY/aS1wWTbZW/v7/ADvcvDlHdBy dI4TozQ1HWN90RAyCERDmzph9hFRF+SfUS+QkkWqaRFr/EFOBk3msWKC8Js2QtRFX3kdSiQTKPe 9dUTax6srEZ2JYdYDG3Wchg1V7VIcckb2beAO2mI3+4igj9D9hgnxPATALrusBZgrvr95akuSZJ K629OL2jijrLfBQQW5A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_05,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604030156 Some devices require more flexibility when configuring their dedicated wake-up interrupts, such as support for IRQF_SHARED or other IRQ flags. This is particularly useful in PCIe systems where multiple endpoints (e.g., Wi-Fi and Bluetooth controllers) share a common WAKE# signal line which requests platform to re-establish power and reference clocks to the components. In such cases, drivers can use this new API dev_pm_set_dedicated_shared_wake_irq() to register a shared wake IRQ. Update the internal helper __dev_pm_set_dedicated_wake_irq() to accept an irq_flags argument. Modify the existing dev_pm_set_dedicated_wake_irq() and dev_pm_set_dedicated_wake_irq_reverse() to preserve current behavior. When IRQ registered with IRQF_SHARED we can't use IRQF_NO_AUTOEN flag, so after registering for irq, disable it explicitly. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Rafael J. Wysocki (Intel) --- drivers/base/power/wakeirq.c | 39 ++++++++++++++++++++++++++++++++++----- include/linux/pm_wakeirq.h | 6 ++++++ 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/base/power/wakeirq.c b/drivers/base/power/wakeirq.c index ad23f0fa5d1a5a9eb49b1af2288ee4908082b13e..b7b106f55559a7c85cb35d9e5ed= 22fe37970662d 100644 --- a/drivers/base/power/wakeirq.c +++ b/drivers/base/power/wakeirq.c @@ -171,7 +171,8 @@ static irqreturn_t handle_threaded_wake_irq(int irq, vo= id *_wirq) return IRQ_HANDLED; } =20 -static int __dev_pm_set_dedicated_wake_irq(struct device *dev, int irq, un= signed int flag) +static int __dev_pm_set_dedicated_wake_irq(struct device *dev, int irq, un= signed int flag, + unsigned int irq_flags) { struct wake_irq *wirq; int err; @@ -200,8 +201,7 @@ static int __dev_pm_set_dedicated_wake_irq(struct devic= e *dev, int irq, unsigned * so we use a threaded irq. */ err =3D request_threaded_irq(irq, NULL, handle_threaded_wake_irq, - IRQF_ONESHOT | IRQF_NO_AUTOEN, - wirq->name, wirq); + IRQF_ONESHOT | irq_flags, wirq->name, wirq); if (err) goto err_free_name; =20 @@ -237,7 +237,7 @@ static int __dev_pm_set_dedicated_wake_irq(struct devic= e *dev, int irq, unsigned */ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) { - return __dev_pm_set_dedicated_wake_irq(dev, irq, 0); + return __dev_pm_set_dedicated_wake_irq(dev, irq, 0, IRQF_NO_AUTOEN); } EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq); =20 @@ -258,10 +258,39 @@ EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq); */ int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq) { - return __dev_pm_set_dedicated_wake_irq(dev, irq, WAKE_IRQ_DEDICATED_REVER= SE); + return __dev_pm_set_dedicated_wake_irq(dev, irq, WAKE_IRQ_DEDICATED_REVER= SE, + IRQF_NO_AUTOEN); } EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq_reverse); =20 +/** + * dev_pm_set_dedicated_shared_wake_irq - Request a dedicated shared wake-= up interrupt + * @dev: Device entry + * @irq: Device wake-up interrupt + * @flags: Custom IRQ flags (e.g., IRQ_TYPE_EDGE_FALLING) + * + * This API sets up a threaded interrupt handler for a device that has + * a shared wake-up interrupt in addition to the device IO interrupt. It a= lso + * sets IRQ flags like IRQ_TYPE_EDGE_FALLING passed by the caller. + * + * Returns 0 on success or a negative error code on failure. + */ +int dev_pm_set_dedicated_shared_wake_irq(struct device *dev, int irq, unsi= gned long flags) +{ + struct wake_irq *wirq; + int ret; + + ret =3D __dev_pm_set_dedicated_wake_irq(dev, irq, 0, IRQF_SHARED | flags= ); + if (ret) + return ret; + + wirq =3D dev->power.wakeirq; + disable_irq_nosync(wirq->irq); + + return 0; +} +EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_shared_wake_irq); + /** * dev_pm_enable_wake_irq_check - Checks and enables wake-up interrupt * @dev: Device diff --git a/include/linux/pm_wakeirq.h b/include/linux/pm_wakeirq.h index 25b63ed51b765c2c6919f259668a12675330835e..61f1e840745b56baa57db37563e= 450cb2d757a85 100644 --- a/include/linux/pm_wakeirq.h +++ b/include/linux/pm_wakeirq.h @@ -11,6 +11,7 @@ extern int dev_pm_set_dedicated_wake_irq(struct device *d= ev, int irq); extern int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int i= rq); extern void dev_pm_clear_wake_irq(struct device *dev); extern int devm_pm_set_wake_irq(struct device *dev, int irq); +extern int dev_pm_set_dedicated_shared_wake_irq(struct device *dev, int ir= q, unsigned long flags); =20 #else /* !CONFIG_PM */ =20 @@ -38,5 +39,10 @@ static inline int devm_pm_set_wake_irq(struct device *de= v, int irq) return 0; } =20 +static inline int dev_pm_set_dedicated_shared_wake_irq(struct device *dev, + int irq, unsigned long flags) +{ + return 0; +} #endif /* CONFIG_PM */ #endif /* _LINUX_PM_WAKEIRQ_H */ --=20 2.34.1 From nobody Tue Apr 7 12:23:23 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC3A63D3D00 for ; Fri, 3 Apr 2026 17:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775237641; cv=none; b=mpfUs8Pe+zxPjdhhlvru+4f5DoWoOrszzhuK4qXpjJUo0VcQOTtl7QjRBLHkJU5oFhGcaOh3kQBXAF4+8kvcWfTX1GyzfXkZHuyJXpjQpwnYpoa5pRcdz8fX/Y6rh/tdktY3ZZvXh6QX0YKp2bnXmiMuKRtvRSwRFjW/yUsQqgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775237641; c=relaxed/simple; bh=4QSi4U79nO6Kuv75iJWSSw33Z4grlzD3UTlYLg1qQkk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MeievM1cCoAe+1PRGCXndNv3kJRHh4IMp7tJUovkJAy0seTqhjvAlp6CDCL431w0SZpBiYimJ2yhpFN2eqEF6rD11lN4vUcyouICbemKllMdKbqo6cIDw3Jc2nWtaoz04ZNXVSfFhg9cM2+EVyP8DalhC0zrjBYuW7bwtW3Dys4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=aZEfTlaj; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gEnyTl98; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="aZEfTlaj"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gEnyTl98" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 633AxCxE3803282 for ; Fri, 3 Apr 2026 17:33:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= t6NWwp7xMQI5NgRMH63RnyN3vLoPe8JewDZUaKKorxg=; b=aZEfTlaj1hsn+O3u 8NFaxgxBssSSIgfmJGXdkmcSIP1+0WYi6Hi3fL0KK5W1FKpdXtnbc3KIAPaueurW HcbQys6NSgfYA7VSBSLS5qb90tfIiNbnJW5eBeLZYD7ZU5LZo+/ytXIAZZC24ZlV PDLPQlw5WLq7zjy2ZBitWZzQE4DTCQV1+MogRJRgsR1S2vMH+ycjDgqh5Sh2OlMa vH3btz4KuBwSb701RJitz66s+EyyGbWimjJ4Fu9YQU44sFUFYHVP1lTfIgOiVefg zOZzlAkA2jQi/yAU9BXflXTHSmNqNuC/qLzitcKGPl5K7ZmTmF1KiaQJhrZEG7la ESju+Q== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dac9f92fb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 03 Apr 2026 17:33:59 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-82cf0130d17so1232637b3a.3 for ; Fri, 03 Apr 2026 10:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775237638; x=1775842438; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=t6NWwp7xMQI5NgRMH63RnyN3vLoPe8JewDZUaKKorxg=; b=gEnyTl98ScjVTXoPMln7o5DU28DSHB2OCjUeogAcL2/MbJzH/zFd05UDYOHTbB31ZM nL1ZrYy4V7mr+p2uKWWCw6nFXhLGQQX/T/GYmC7RhhT9iT9pDJrYVAEby8Csnjukn+oN Qi53hbo7lj2UgZkZLbs/Y2AVufh4zP3ACd2loujcBPBeIRuvRDw2UTP/YHoxJzbhTn3M +9IoAyDG1zmSXjDSidUT4nGT69WE4M/RRRy/Crsc2+ONVtRQTQsoLpJLbJMZvWTI21MW q0TQ4gzb3TISVW5sQsltz2RzrW3VzuNObtvvoi3MMq/kxCe+Im/rT0pAvI/vEDh3ewBe 47KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775237638; x=1775842438; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=t6NWwp7xMQI5NgRMH63RnyN3vLoPe8JewDZUaKKorxg=; b=o78almRrUa+zDew8QnT+qbkzm+MjPw5hu/NCE900ro1LaVUPElMrl7GwxTxQDYZgW/ R9JcLmYFYnN1mc3mLXS2bcQ1tCG8BQ0UzPnhtnb3FYF7nOQJYLRs+ZQOeZCUdkZ4GnAG XR4mcfSDPB7mx4b/cnsYu8n/Hvtlv7A+OWCYqrXaRLJ9DumUGZn8PwYyKZ1XyouUWTtn nIgksa2Q1Bijo5aois6Ja9XBnlxF7Myl7hCe72vt6b/z6qAnSYvQWxCojsg7hXto9Gjj 9eWFDA8Tjgj6YQz7xEvDpeBwuWKk98e4iCquvNmwNFwaiwNELbReQcMZKPDQDth4EeZW FENA== X-Forwarded-Encrypted: i=1; AJvYcCXE5oCSWGH4rdJjjp2tjNvLTt9RRqg1U7rNHamAGHwePQBVXVExl45hu1mTgTitlRwiYLCn2t7MJEyjSng=@vger.kernel.org X-Gm-Message-State: AOJu0Yyo5MBpvep28M04om9CUT5MAHjIc6f483eH8K+nKzn4KRP7y42Q iCItJdFCa4O0q2EiUhlP55zewxBsRmAvByVciEwEpDY50BWqhw/zNjkdpC+VpubPQ0uejhp6qLX Vgk2/NozULXOA/PBCv1cwFbCVHQ02jYkq+2IgjJdtYYAzPpa4Gc8yWLh4ECKMtSSoW4U= X-Gm-Gg: ATEYQzxIZ3gkHtcQILvdBVqIrenIRSWjn9SPUlIrqLc5bAazX6nGdlo36X+u7rlLj3E ua3QcoafbcQmK80BegYd4n9fj3TyeIigzyUBj0+0Z2j1ADpx9zBnHWXJiduMB1llo7V/GutKrKH yLUhKBhZLQDjpnz3gnlqjHiR8sVJFn30cueXv5216LRvTcPbOsd8m6X0da8+TgriIWByv90EFbh V6ax++1JErdGX2iihXv/iP4haTrZMscRPOzOCOPEHyM4RmlHPxyhhoOkYoLW2x9zwvUyKzKyICf LkocH6k3/p6DJJap+JkBmTAI0C0C1i9xiRmWc0vNVwj4WYErZptUxAKespZ289f91nynS+Ai6Uu zEOzU9l/bXTndYUVTro1IbWzArT9xNFOoLmUAjMXDOhYKDjAb/B/78SPg X-Received: by 2002:a05:6a00:3d4f:b0:82c:dc9c:e765 with SMTP id d2e1a72fcca58-82d0d749427mr3930147b3a.0.1775237638448; Fri, 03 Apr 2026 10:33:58 -0700 (PDT) X-Received: by 2002:a05:6a00:3d4f:b0:82c:dc9c:e765 with SMTP id d2e1a72fcca58-82d0d749427mr3930115b3a.0.1775237637915; Fri, 03 Apr 2026 10:33:57 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82cf9b3e169sm6359125b3a.18.2026.04.03.10.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 10:33:57 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 03 Apr 2026 23:03:34 +0530 Subject: [PATCH v9 2/3] gpio: Add fwnode_gpiod_get() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-wakeirq_support-v9-2-1cbecf3b58d7@oss.qualcomm.com> References: <20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com> In-Reply-To: <20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com> To: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Greg Kroah-Hartman , Danilo Krummrich , Bjorn Helgaas , Bartosz Golaszewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Saravana Kannan , Linus Walleij Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, quic_vbadigan@quicinc.com, sherry.sun@nxp.com, driver-core@lists.linux.dev, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775237619; l=1418; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=4QSi4U79nO6Kuv75iJWSSw33Z4grlzD3UTlYLg1qQkk=; b=S3BBZnE3MjxvBLw9tw9ecCrgVVwynC/kNl/NBJTEmrlZVZtP/c6mx9OmMyhsxVYd5XSpcq4h8 ahd7a5OtAF8CGyTIaMGUzdN/cOHXYeBoxs6bvGKrSadbndkpQ7xGY2r X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: P8ak9UxSDQh3NMqKcCc_2pElHfY7liu9 X-Proofpoint-ORIG-GUID: P8ak9UxSDQh3NMqKcCc_2pElHfY7liu9 X-Authority-Analysis: v=2.4 cv=BO++bVQG c=1 sm=1 tr=0 ts=69cffa07 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Ocqi7cVID08-S0eeb-IA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDE1NiBTYWx0ZWRfX/yMR3moluZwK /nK1loAenBQerG1US1T4hMYvWj8an0GaJNxrWxm1g40Y4sgahIvanq0zI2yk+LEfcSq8y6BcgPZ c+7bu9XdMnG6G1pzP5wZvwpkXpEHwpuayuZuyVMbk4LrJ8Vgb9ehyyvy7GHLSZaxYw+rRNV/+iw pgs0fwdYcknVl5/WvYUujMFY2UPmCR2LLmSm4mCIJx/XWy2MXL6nPXosWUyuhs2tX1k+MinSKBH 3BK2fQvw6k5CPlYdiqj9AKHi7OQjH7I17YN0RUTf/SuISt4NExMlTtjtQv3Z46cdum+fNOiHbzT O30TdE5D7XPm4bl3pz1eHM2gTD1x1lROlFnedlzUy76QN81/SX7ajk95KerObL3NtT84pEUAeoX oClBtMKydFc4sxAhk/arqaq+AJHlhkCOZMjh7+bJ3ZR6vg+xCuBUEy0ZYvXJguJTlseMbrapISU 1woUnoEdFRuczKEG30Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_05,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604030156 Add fwnode_gpiod_get() as a convenience wrapper around fwnode_gpiod_get_index() for the common case where only the first GPIO is required. This mirrors existing gpiod_get() and devm_gpiod_get() helpers and avoids open-coding index 0 at call sites. Suggested-by: Manivannan Sadhasivam Acked-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Acked-by: Bartosz Golaszewski Signed-off-by: Krishna Chaitanya Chundru --- include/linux/gpio/consumer.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h index 0d8408582918680bfea6a04ccedfc0c75211907a..fee926c0262ce9dc4b9a3c151e7= 4f2cf37470a49 100644 --- a/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h @@ -596,6 +596,15 @@ static inline int gpiod_disable_hw_timestamp_ns(struct= gpio_desc *desc, } #endif /* CONFIG_GPIOLIB && CONFIG_HTE */ =20 +static inline +struct gpio_desc *fwnode_gpiod_get(struct fwnode_handle *fwnode, + const char *con_id, + enum gpiod_flags flags, + const char *label) +{ + return fwnode_gpiod_get_index(fwnode, con_id, 0, flags, label); +} + static inline struct gpio_desc *devm_fwnode_gpiod_get(struct device *dev, struct fwnode_handle *fwnode, --=20 2.34.1 From nobody Tue Apr 7 12:23:23 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 186143CEBBF for ; Fri, 3 Apr 2026 17:34:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775237647; cv=none; b=S0lctD29ogkktpf5mes+QWXJFca94/CIxxQ8z6Y0wHoWrYLWvxNPjyXAtF8/+lVfPw/SA7Fx7Yyd6CO79AK9fKDMgjsxgFE378CUl7kH1XyxkSK7GKYms4O1SdUFlrrvnxpOtV2C3Tn5j7FPpMKv51qWyJiCZ1JoVR1qToELj40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775237647; c=relaxed/simple; bh=BswqjKSE0ZPr7l8CqajQN/6PIFNVHGX3Hga0DwKabto=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OiZNrxko9Obp1qX/1mXxNLjhMN6DdHaway6ou/Eobxq0tD8HkueptDKNSbxinMiorN92onNqRykHlrarxTHe3Fm8m+Qb3/F8Jo37ixUsk7FUqE7Cf7Hgv0FM8OruYnlF45Vaf+9vnld6Le/FgwNT2T7Mayxqxp7SxewcMzfgEDw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=gTZpm2eh; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=cClyO87Z; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="gTZpm2eh"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="cClyO87Z" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 633BgZj13780256 for ; Fri, 3 Apr 2026 17:34:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= cS4DEz8Mt35qtFStKmkL4fllgbCdtEZk/8Dp6lQ4xAE=; b=gTZpm2ehytKDxwEr ERNZ7dJt6s6UAnDyeEs9htoGSCKZBNd5Xhmakm3InV9G+pu91OrlBv7QvdRYj7zj iehK5+thhtYXXkmEgZ1KUgPsNpr0eOBE+9Fk34xegN2BnFfFGZlCGZhLu1Ml1Wl5 fNZRiQjmAnQDVnkA9d5FpJ+uueZnKA0SQXuEEaULgrQM8wdRRmPeeZlA0TglFtUe s5RvKc49bDNZmWbSmLrL++6VFc6DT7e8g9aJ2qSIj2dJU0ympXj7AyTVfJ1KYLaH RYCu4HinXTfWOgiYe3fqnl/ejGjfgzsRvve4aUmb0Jn9gdZhj6CeRWzipg9YeVYo epSvuQ== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4da663j9h9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 03 Apr 2026 17:34:05 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-82ce34a78edso2773195b3a.1 for ; Fri, 03 Apr 2026 10:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775237645; x=1775842445; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cS4DEz8Mt35qtFStKmkL4fllgbCdtEZk/8Dp6lQ4xAE=; b=cClyO87ZvLdDkowguJGPZoYel0elBXhahxlV5f/7Z77PMUhqUKVchP9+WoHvi2KtWq CEsz03IUoELGv2fyWe1hjnM9ZYV4rHeT757LaLHY/cEF7ZzQ+JG4nAk5Fn765L9K4HIK 6HRU9aZsE1rSOBWwoQTnwdbedRqvURZtxdnvAUxSgSliXZCYPNW4Gl+yV1qRdJhBBdOK evX+IPZIkpZNpLjAUczxhJ9ZZt497rFmhdoUqueNcQfGM+Pv5vXW/0G52aXBACRs/4gq 9UflDMmkpGS8ifiHz8f7AQcBB0YQstsJjsntQPdJUu2GmEa9QadcRTCu1rKbTEJOQ5Nw yAbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775237645; x=1775842445; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=cS4DEz8Mt35qtFStKmkL4fllgbCdtEZk/8Dp6lQ4xAE=; b=QT/K6VFH/+o+1+bQVk9VkqpA1Zd8F0PfEKaS26gKLeZ/fWALttL8OHGywvcUyEJYy9 aPZUHQLbKedI3Dk8P6gOHd244yuSlhkyNtv7IUypKPMEE+RG0AjZrN7HYzbArQYgOtjZ xecap4hCCc3WRTI008VibBgznTPf2w1Aa8DVZKVqQjypA6SB4OSADTMyFBtiaj6BIIBC pI+6iFyaBXLjd16YCCeTl2PrcC5ueYissPhEahc43OYP7lakp2G54hfUJZTU6ALcr38r Rax28J/SPH3/5I+Mm+GN5ukZm4BTCyVcjQTs1LW3EpWMnDfKMgjQhd8lafJSGC9lHYmO X5tA== X-Forwarded-Encrypted: i=1; AJvYcCVlBwaRxD7epI0BE8eSY6W2EAf7McLUmeW8FUS1uxep2lgjKqiIesKbCpOCMKQSomq52lVpDrOGOBM3sAQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzHi0cJVzoLgZJM7nHt34JWviHe/R27LlCWJOkPrSceK4xxIxLJ U4SrO7DcvUEjCSjI1RqZCU3+bEqixn4zImNwmCS+a0vWBNTua59zGWzNP7dbTCPoqD7meO/eoLO 3Di7FU8j54dSmVC1KbBW9FdH8wvDoCtWbj51yMUrZd9e3F+wWeNZreOQKhdSh7GkYssk= X-Gm-Gg: AeBDietv7+yLCynVl2+tjcB09zuwjwXx8LTfEsah/WToGUuunPTZS957hBv4slh+ttt ezFgA1q6s0wwzG9txkp8BA40eHlpcuJ/PfG4bhtC/lm4MAGsDk7DfgzeEuLigbmrOENB7TBausJ qi0jLVxKjNvn6d5te8sMLUaTL+I2zLQfETDqxoY1pjxRaN0MyptWuuu3Sj21u4FctwSw90BDL8U 0xb0f9FEpPVQNePZpIjm/uI1iz0Bc275MpZM/1fENPRMPDYt7PMgmjeiYcphXIQWb3lagro4f4E bL6NIhdaGkIRnJtTBf43TNisPEw78GGsPb03wmlY79AbxUXsXL6cgwnVka0Zz7T23Q5aFgiY25l r03TbBedAWS+4147WRRtcvjGmhnzfABJmXu99uY8e2jXZsMa4j+KT60Tw X-Received: by 2002:a05:6a00:aa85:b0:829:6f9f:ea44 with SMTP id d2e1a72fcca58-82d0da8ba21mr3650308b3a.17.1775237644415; Fri, 03 Apr 2026 10:34:04 -0700 (PDT) X-Received: by 2002:a05:6a00:aa85:b0:829:6f9f:ea44 with SMTP id d2e1a72fcca58-82d0da8ba21mr3650271b3a.17.1775237643823; Fri, 03 Apr 2026 10:34:03 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82cf9b3e169sm6359125b3a.18.2026.04.03.10.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 10:34:03 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 03 Apr 2026 23:03:35 +0530 Subject: [PATCH v9 3/3] PCI: Add support for PCIe WAKE# interrupt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-wakeirq_support-v9-3-1cbecf3b58d7@oss.qualcomm.com> References: <20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com> In-Reply-To: <20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com> To: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Greg Kroah-Hartman , Danilo Krummrich , Bjorn Helgaas , Bartosz Golaszewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Saravana Kannan , Linus Walleij Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, quic_vbadigan@quicinc.com, sherry.sun@nxp.com, driver-core@lists.linux.dev, devicetree@vger.kernel.org, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775237619; l=9559; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=BswqjKSE0ZPr7l8CqajQN/6PIFNVHGX3Hga0DwKabto=; b=pVJaDEIVyCYsRjLoOdV+ozcPmLpciI51NBeTwG4tfB8XVBRF6FRa0ehgQDSNsUjBcEXHth3ar s0c9kgZp6wJBV95/lEUubAriMtA0xndknzRipBvddEmPXjcRFTRhmT8 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAzMDE1NiBTYWx0ZWRfX21WJPUKXD/9B mUsmHUCbIxhj+EoxjMHYJCjBn7pzRX4W5X/Ff2rDQMx4gvg7EhFblqq0QFtxincYKzhIBXzIxsk e/Fro6NEdLeuowjgrQYLYTJqYk5IkVqbIrA2CWssIw0/R0haGvR9KlyGQfE1Y7eZ/AYEWWHu0KL yImeANxDy/w+f0QsS0Srm+qAozToH5XLUuatMSN0HOvs5GCuhy7quFshGy/Z7KfKH/w2IWzv4fG 1fRvTMkUTxM/lnUgUCiUFVEWyv5SGCDjgh71wxDKWlYBVZC5N2P+awy84MjFOphD7r/AFHtREA2 0iN4PXjepVog+6RIfOkksEh5vmcwZkqGgjfYCCZrbhGxtWdo498g9P6WsQVPYQ64Rvc6jJfa5qz wInsBxdfo8bfU2/cEa+VrVtmUfEJKis/KHq0bKt9crp51WJtLI/q+MFpx6P3pijYjUO4FCY6v9l d5+eVb4GHcjYUkLOz+Q== X-Proofpoint-GUID: o-MYK1uJ3nXipkAXOmSELzf2F8LbHbvW X-Proofpoint-ORIG-GUID: o-MYK1uJ3nXipkAXOmSELzf2F8LbHbvW X-Authority-Analysis: v=2.4 cv=Acu83nXG c=1 sm=1 tr=0 ts=69cffa0d cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8 a=XVdArZcsv8hm62BSzCUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_05,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604030156 According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2), two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a hardware-only mechanism and is invisible to software (PCIe r7.0, Section 4.2.7.8.1). This change adds support for the WAKE# mechanism in the PCI core. According to the PCIe specification, multiple WAKE# signals can exist in a system or each component in the hierarchy could share a single WAKE# signal. In configurations involving a PCIe switch, each downstream port (DSP) of the switch may be connected to a separate WAKE# line, allowing each endpoint to signal WAKE# independently. From figure 5.4 in sec 5.3.3.2, WAKE# can also be terminated at the switch itself. To support this, the WAKE# should be described in the device tree node of the endpoint/bridge. If all endpoints share a single WAKE# line, then each endpoint node should describe the same WAKE# signal or a single WAKE# in the Root Port node. In pci_device_add(), PCI framework will search for the WAKE# in device node, If not found, it searches in its upstream port only if upstream port is Root Port. Once found, register for the wake IRQ in shared mode, as the WAKE# may be shared among multiple endpoints. dev_pm_set_dedicated_shared_wake_irq() associates a wakeup IRQ with a device and requests it, but the PM core keeps the IRQ disabled by default. The IRQ is enabled only when the device is permitted to wake the system, i.e. during system suspend and after runtime suspend, and only when device wakeup is enabled. When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to bring the device back to an active power state, such as transitioning from D3cold to D0. Once the device is active and the link is usable, the endpoint may generate a PME, which is then handled by the PCI core through PME polling or the PCIe PME service driver to complete the wakeup of the endpoint. WAKE# is added in dts schema and merged based on below links. Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@= oss.qualcomm.com/ Link: https://github.com/devicetree-org/dt-schema/pull/170 Reviewed-by: Linus Walleij Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/pci/pci.c | 10 +++++++ drivers/pci/pci.h | 2 ++ drivers/pci/probe.c | 2 ++ drivers/pci/remove.c | 1 + include/linux/of_pci.h | 4 +++ include/linux/pci.h | 2 ++ 7 files changed, 95 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 9f8eb5df279ed28db7a3b2fd29c65da9975c2efa..1678e82962b78ac206829a3a1fc= 121b0142b993b 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "PCI: OF: " fmt =20 #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include "pci.h" =20 #ifdef CONFIG_PCI @@ -586,6 +588,78 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev= , u8 slot, u8 pin) return irq_create_of_mapping(&oirq); } EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); + +static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc = *wake) +{ + int ret, wake_irq; + + wake_irq =3D gpiod_to_irq(wake); + if (wake_irq < 0) { + pci_err(pdev, "Failed to get wake irq: %d\n", wake_irq); + return; + } + + /* + * dev_pm_set_dedicated_shared_wake_irq() associates a wakeup IRQ with the + * device and requests it, but the PM core keeps it disabled by default. + * The IRQ is enabled only when the device is allowed to wake the system + * (during system suspend and after runtime suspend), and only if device + * wakeup is enabled. + * + * When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume= () + * to bring the device back to an active power state (e.g. from D3cold to= D0). + * Once the device is active and the link is usable, the endpoint may sig= nal + * a PME, which is then handled by the PCI core (either via PME polling o= r the + * PCIe PME service driver) to wakeup particular endpoint. + */ + ret =3D dev_pm_set_dedicated_shared_wake_irq(&pdev->dev, wake_irq, + IRQ_TYPE_LEVEL_LOW); + if (ret < 0) { + pci_err(pdev, "Failed to set WAKE# IRQ: %d\n", ret); + return; + } + + device_init_wakeup(&pdev->dev, true); +} + +void pci_configure_of_wake_gpio(struct pci_dev *dev) +{ + struct device_node *dn =3D pci_device_to_OF_node(dev); + struct pci_dev *upstream; + struct gpio_desc *gpio; + + if (!dn) + return; + + /* + * The devices in a hierarchy expose wakeup capability through the 'wake-= gpios' + * property defined either in the device node or in the Slot node. So fir= st check + * for the property in device node and if not available, check in the Slo= t node. + */ + gpio =3D fwnode_gpiod_get(of_fwnode_handle(dn), "wake", + GPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE, NULL); + if (IS_ERR(gpio)) { + upstream =3D pci_upstream_bridge(dev); + if (upstream && pci_is_root_bus(upstream->bus) && upstream->wake) + pci_configure_wake_irq(dev, upstream->wake); + } else { + dev->wake =3D gpio; + pci_configure_wake_irq(dev, gpio); + } +} + +void pci_remove_of_wake_gpio(struct pci_dev *dev) +{ + struct device_node *dn =3D pci_device_to_OF_node(dev); + + if (!dn) + return; + + dev_pm_clear_wake_irq(&dev->dev); + device_init_wakeup(&dev->dev, false); + gpiod_put(dev->wake); + dev->wake =3D NULL; +} #endif /* CONFIG_OF_IRQ */ =20 static int pci_parse_request_of_pci_ranges(struct device *dev, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8479c2e1f74f1044416281aba11bf071ea89488a..3d858f36ab48a6daec645574ca9= 027d9d6f071de 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -1123,6 +1124,15 @@ static inline bool platform_pci_bridge_d3(struct pci= _dev *dev) return acpi_pci_bridge_d3(dev); } =20 +void platform_pci_configure_wake(struct pci_dev *dev) +{ + return pci_configure_of_wake_gpio(dev); +} + +void platform_pci_remove_wake(struct pci_dev *dev) +{ + return pci_remove_of_wake_gpio(dev); +} /** * pci_update_current_state - Read power state of given device and cache it * @dev: PCI device to handle. diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce6698514d92500dfea03cc562cdc2..65ca9551e558d2e3331fab0a968= 620d6b2a2522a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -282,6 +282,8 @@ void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_typ= e); +void platform_pci_configure_wake(struct pci_dev *dev); +void platform_pci_remove_wake(struct pci_dev *dev); =20 static inline bool pci_bus_rrs_vendor_id(u32 l) { diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index bccc7a4bdd794384b7877d453c7989941471c999..372b0d2f4531ea53c0570608306= a547101d59e7b 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2771,6 +2771,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_b= us *bus) /* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */ pci_tsm_init(dev); =20 + platform_pci_configure_wake(dev); + pci_npem_create(dev); =20 pci_doe_sysfs_init(dev); diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index e9d519993853f92f1810d3eff9f44ca7e3e1abd9..d781b41e57c4444077075690cec= 926a9fe15334f 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -35,6 +35,7 @@ static void pci_destroy_dev(struct pci_dev *dev) if (pci_dev_test_and_set_removed(dev)) return; =20 + platform_pci_remove_wake(dev); pci_doe_sysfs_teardown(dev); pci_npem_remove(dev); =20 diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 29658c0ee71ff10122760214d04ee2bab01709fd..0efd6e9cb4d3d3beaafb42ea411= 303139f1150d5 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -30,12 +30,16 @@ static inline void of_pci_check_probe_only(void) { } =20 #if IS_ENABLED(CONFIG_OF_IRQ) int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); +void pci_configure_of_wake_gpio(struct pci_dev *dev); +void pci_remove_of_wake_gpio(struct pci_dev *dev); #else static inline int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) { return 0; } +static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { } +static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { } #endif =20 #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index 1c270f1d512301de4d462fe7e5097c32af5c6f8d..d1e08df8a8deaa87780589f2324= 2767fdcdba541 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -586,6 +586,8 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ =20 + struct gpio_desc *wake; /* Holds WAKE# gpio */ + #ifdef CONFIG_PCIE_TPH u16 tph_cap; /* TPH capability offset */ u8 tph_mode; /* TPH mode */ --=20 2.34.1