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Fri, 03 Apr 2026 06:28:11 -0700 (PDT) Received: from brgl-qcom.local ([2a01:cb1d:dc:7e00:129d:59e8:f7c9:47ca]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488980e312csm22224685e9.7.2026.04.03.06.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 06:28:11 -0700 (PDT) From: Bartosz Golaszewski Date: Fri, 03 Apr 2026 15:27:55 +0200 Subject: [PATCH 1/3] dt-bindings: pinctrl: describe the TLMM controller on Qualcomm Nord platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-nord-tlmm-v1-1-4864f400c700@oss.qualcomm.com> References: <20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com> In-Reply-To: <20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Bartosz Golaszewski , Shawn Guo , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Signed-off-by: Bartosz Golaszewski --- .../bindings/pinctrl/qcom,nord-tlmm.yaml | 206 +++++++++++++++++= ++++ 1 file changed, 206 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b1fdaa24a045469e3dec512ce02= 00f240daa1959 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Nord TLMM block + +maintainers: + - Bartosz Golaszewski + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm Nord SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,nord-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 74 + + gpio-line-names: + maxItems: 180 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-nord-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-nord-tlmm-state" + additionalProperties: false + +$defs: + qcom-nord-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180])$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_cha= r3, + atest_char_start, atest_usb20, atest_usb21, aud_intfc0_clk, + aud_intfc0_data0, aud_intfc0_data1, aud_intfc0_data2, + aud_intfc0_data3, aud_intfc0_data4, aud_intfc0_data5, + aud_intfc0_data6, aud_intfc0_data7, aud_intfc0_ws, + aud_intfc10_clk, aud_intfc10_data0, aud_intfc10_data1, + aud_intfc10_ws, aud_intfc1_clk, aud_intfc1_data0, + aud_intfc1_data1, aud_intfc1_data2, aud_intfc1_data3, + aud_intfc1_data4, aud_intfc1_data5, aud_intfc1_data6, + aud_intfc1_data7, aud_intfc1_ws, aud_intfc2_clk, + aud_intfc2_data0, aud_intfc2_data1, aud_intfc2_data2, + aud_intfc2_data3, aud_intfc2_ws, aud_intfc3_clk, + aud_intfc3_data0, aud_intfc3_data1, aud_intfc3_ws, + aud_intfc4_clk, aud_intfc4_data0, aud_intfc4_data1, + aud_intfc4_ws, aud_intfc5_clk, aud_intfc5_data0, + aud_intfc5_data1, aud_intfc5_ws, aud_intfc6_clk, + aud_intfc6_data0, aud_intfc6_data1, aud_intfc6_ws, + aud_intfc7_clk, aud_intfc7_data0, aud_intfc7_data1, + aud_intfc7_ws, aud_intfc8_clk, aud_intfc8_data0, + aud_intfc8_data1, aud_intfc8_ws, aud_intfc9_clk, + aud_intfc9_data0, aud_intfc9_ws, aud_mclk0_mira, + aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb, + aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1, + bist_done, ccu_async_in0, ccu_async_in1, ccu_async_in2, + ccu_async_in3, ccu_async_in4, ccu_async_in5, ccu_i2c_scl0, + ccu_i2c_scl1, ccu_i2c_scl2, ccu_i2c_scl3, ccu_i2c_scl4, + ccu_i2c_scl5, ccu_i2c_scl6, ccu_i2c_scl7, ccu_i2c_scl8, + ccu_i2c_scl9, ccu_i2c_sda0, ccu_i2c_sda1, ccu_i2c_sda2, + ccu_i2c_sda3, ccu_i2c_sda4, ccu_i2c_sda5, ccu_i2c_sda6, + ccu_i2c_sda7, ccu_i2c_sda8, ccu_i2c_sda9, ccu_timer0, + ccu_timer1, ccu_timer10, ccu_timer11, ccu_timer12, ccu_tim= er13, + ccu_timer14, ccu_timer15, ccu_timer2, ccu_timer3, ccu_time= r4, + ccu_timer5, ccu_timer6, ccu_timer7, ccu_timer8, ccu_timer9, + clink_debug, dbg_out, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0, + ddr_pxi1, ddr_pxi10, ddr_pxi11, ddr_pxi12, ddr_pxi13, ddr_= pxi14, + ddr_pxi15, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi= 6, + ddr_pxi7, ddr_pxi8, ddr_pxi9, dp_rx0, dp_rx00, dp_rx01, + dp_rx0_mute, dp_rx1, dp_rx10, dp_rx11, dp_rx1_mute, edp0_h= ot, + edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, + edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg0, emac1_mcg1, + emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_ptp, + gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp= 5_clk, + gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_= pass, + mbist_pass, mdp0_vsync0_out, mdp0_vsync10_out, mdp0_vsync1= _out, + mdp0_vsync2_out, mdp0_vsync3_out, mdp0_vsync4_out, + mdp0_vsync5_out, mdp0_vsync6_out, mdp0_vsync7_out, + mdp0_vsync8_out, mdp0_vsync9_out, mdp1_vsync0_out, + mdp1_vsync10_out, mdp1_vsync1_out, mdp1_vsync2_out, + mdp1_vsync3_out, mdp1_vsync4_out, mdp1_vsync5_out, + mdp1_vsync6_out, mdp1_vsync7_out, mdp1_vsync8_out, + mdp1_vsync9_out, mdp_vsync_e, mdp_vsync_p, mdp_vsync_s, + pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n, + pcie3_clk_req_n, phase_flag0, phase_flag1, phase_flag10, + phase_flag11, phase_flag12, phase_flag13, phase_flag14, + phase_flag15, phase_flag16, phase_flag17, phase_flag18, + phase_flag19, phase_flag2, phase_flag20, phase_flag21, + phase_flag22, phase_flag23, phase_flag24, phase_flag25, + phase_flag26, phase_flag27, phase_flag28, phase_flag29, + phase_flag3, phase_flag30, phase_flag31, phase_flag4, + phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_= rosc1, + pwrbrk_i_n, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1, + qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_g= pio14, + qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio= 5, + qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qspi0, qsp= i1, + qspi2, qspi3, qspi_clk, qspi_cs0_n, qspi_cs1_n, qup0_se0_l= 0, + qup0_se0_l1, qup0_se0_l2, qup0_se0_l3, qup0_se1_l0, qup0_s= e1_l1, + qup0_se1_l2, qup0_se1_l3, qup0_se2_l0, qup0_se2_l1, qup0_s= e2_l2, + qup0_se2_l3, qup0_se3_l0, qup0_se3_l1, qup0_se3_l2, qup0_s= e3_l3, + qup0_se4_l0, qup0_se4_l1, qup0_se4_l2, qup0_se4_l3, qup0_s= e5_l0, + qup0_se5_l1, qup0_se5_l2, qup0_se5_l3, qup1_se0_l0, qup1_s= e0_l1, + qup1_se0_l2, qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_s= e1_l2, + qup1_se1_l3, qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_s= e2_l3, + qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, qup1_se3_l3, qup1_s= e4_l0, + qup1_se4_l1, qup1_se4_l2, qup1_se4_l3, qup1_se5_l0, qup1_s= e5_l1, + qup1_se5_l2, qup1_se5_l3, qup1_se6_l0, qup1_se6_l1, qup1_s= e6_l2, + qup1_se6_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2, qup2_s= e0_l3, + qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3, qup2_s= e2_l0, + qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4, qup2_s= e3_l0, + qup2_se3_l1, qup2_se3_l2, qup2_se3_l3, qup2_se4_l0, qup2_s= e4_l1, + qup2_se4_l2, qup2_se4_l3, qup2_se4_l4, qup2_se4_l5, qup2_s= e4_l6, + qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_s= e6_l0, + qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup3_se0_l0_mira, + qup3_se0_l0_mirb, qup3_se0_l1_mira, qup3_se0_l1_mirb, + qup3_se0_l2, qup3_se0_l3, qup3_se0_l4, qup3_se0_l5, qup3_s= e0_l6, + sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert, + smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0, + tmess_prng1, tsc_timer0, tsc_timer1, tsc_timer2, tsc_timer= 3, + tsc_timer4, tsc_timer5, tsc_timer6, tsc_timer7, tsc_timer8, + tsc_timer9, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_= pwm4, + tsense_pwm5, tsense_pwm6, tsense_pwm7, tsense_pwm8, usb0_h= s, + usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy, + usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,nord-tlmm"; + reg =3D <0x0f100000 0xc0000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 181>; + wakeup-parent =3D <&pdc>; + + qup_uart15_default: qup-uart15-default-state { + tx-pins { + pins =3D "gpio147"; + function =3D "qup2_se2_l2"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio148"; + function =3D "qup2_se2_l3"; + drive-strength =3D <2>; + bias-disable; + }; + }; + }; +... --=20 2.47.3 From nobody Sun Jun 14 15:56:16 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 232B43BD237 for ; Fri, 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text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com> References: <20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com> In-Reply-To: <20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Bartosz Golaszewski , Shawn Guo , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=94295; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=q3VY16+z98mU26357XioWhSWdZKcrlIgpbmBCCMzO2I=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBpz8Bl5EY0LGOXwV1Va4Q2IsiF6dbtCCduak07A lvdQdGzJQqJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCac/AZQAKCRAFnS7L/zaE w4XsEACJprcX8S8/nw2pfxvgWdLXqxc4m3BL/8WeL3Jbb5rs+fh0RIRezpTMSkzFAEsJfQEB9qp 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X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 adultscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604030120 Add support for the TLMM controller on the Qualcomm Nord platform. Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/Kconfig.msm | 7 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-nord.c | 3297 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 3305 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 6df6159fa5f89f9f0470e700b4698dc8849ed515..6698e2a50b2f67b1aadb4a84033= 9e769c92f95f8 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -261,6 +261,13 @@ config PINCTRL_SA8775P This is the pinctrl, pinmux and pinconf driver for the Qualcomm TLMM block found on the Qualcomm SA8775P platforms. =20 +config PINCTRL_NORD + tristate "Qualcomm Technologies Inc NORD (SA8797p) pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux and pinconf driver for the Qualcomm + TLMM block found on the Qualcomm NORD platforms. + config PINCTRL_SAR2130P tristate "Qualcomm Technologies Inc SAR2130P pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a8fd12f90d6e6f8e139097cc0a81d6f178f09000..ba6e9408373ff4327bb0c092f1f= 30889998503a1 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_PINCTRL_MDM9607) +=3D pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) +=3D pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_MILOS) +=3D pinctrl-milos.o obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) +=3D pinctrl-milos-lpass-lpi.o +obj-$(CONFIG_PINCTRL_NORD) +=3D pinctrl-nord.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) +=3D pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) +=3D pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) +=3D pinctrl-ssbi-gpio.o diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pin= ctrl-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..82e519abaf75771817a0f811c6a= f80c4f98e93ed --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-nord.c @@ -0,0 +1,3297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg =3D REG_SIZE * id, \ + .io_reg =3D 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D 0xc + REG_SIZE * id, \ + .intr_target_reg =3D 0x8 + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .egpio_enable =3D 12, \ + .egpio_present =3D 11, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs =3D 12, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D 0, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D pull, \ + .drv_bit =3D drv, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D -1, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D offset, \ + .io_reg =3D offset + 0x4, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D 3, \ + .drv_bit =3D 0, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D 0, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +#define QUP_I3C(qup_mode, qup_offset) \ + { \ + .mode =3D qup_mode, \ + .offset =3D qup_offset, \ + } + +static const struct pinctrl_pin_desc nord_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); + +static const unsigned int ufs_reset_pins[] =3D { 181 }; + +enum nord_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_char_start, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_aud_intfc0_clk, + msm_mux_aud_intfc0_data0, + msm_mux_aud_intfc0_data1, + msm_mux_aud_intfc0_data2, + msm_mux_aud_intfc0_data3, + msm_mux_aud_intfc0_data4, + msm_mux_aud_intfc0_data5, + msm_mux_aud_intfc0_data6, + msm_mux_aud_intfc0_data7, + msm_mux_aud_intfc0_ws, + msm_mux_aud_intfc10_clk, + msm_mux_aud_intfc10_data0, + msm_mux_aud_intfc10_data1, + msm_mux_aud_intfc10_ws, + msm_mux_aud_intfc1_clk, + msm_mux_aud_intfc1_data0, + msm_mux_aud_intfc1_data1, + msm_mux_aud_intfc1_data2, + msm_mux_aud_intfc1_data3, + msm_mux_aud_intfc1_data4, + msm_mux_aud_intfc1_data5, + msm_mux_aud_intfc1_data6, + msm_mux_aud_intfc1_data7, + msm_mux_aud_intfc1_ws, + msm_mux_aud_intfc2_clk, + msm_mux_aud_intfc2_data0, + msm_mux_aud_intfc2_data1, + msm_mux_aud_intfc2_data2, + msm_mux_aud_intfc2_data3, + msm_mux_aud_intfc2_ws, + msm_mux_aud_intfc3_clk, + msm_mux_aud_intfc3_data0, + msm_mux_aud_intfc3_data1, + msm_mux_aud_intfc3_ws, + msm_mux_aud_intfc4_clk, + msm_mux_aud_intfc4_data0, + msm_mux_aud_intfc4_data1, + msm_mux_aud_intfc4_ws, + msm_mux_aud_intfc5_clk, + msm_mux_aud_intfc5_data0, + msm_mux_aud_intfc5_data1, + msm_mux_aud_intfc5_ws, + msm_mux_aud_intfc6_clk, + msm_mux_aud_intfc6_data0, + msm_mux_aud_intfc6_data1, + msm_mux_aud_intfc6_ws, + msm_mux_aud_intfc7_clk, + msm_mux_aud_intfc7_data0, + msm_mux_aud_intfc7_data1, + msm_mux_aud_intfc7_ws, + msm_mux_aud_intfc8_clk, + msm_mux_aud_intfc8_data0, + msm_mux_aud_intfc8_data1, + msm_mux_aud_intfc8_ws, + msm_mux_aud_intfc9_clk, + msm_mux_aud_intfc9_data0, + msm_mux_aud_intfc9_ws, + msm_mux_aud_mclk0_mira, + msm_mux_aud_mclk0_mirb, + msm_mux_aud_mclk1_mira, + msm_mux_aud_mclk1_mirb, + msm_mux_aud_mclk2_mira, + msm_mux_aud_mclk2_mirb, + msm_mux_aud_refclk0, + msm_mux_aud_refclk1, + msm_mux_bist_done, + msm_mux_ccu_async_in0, + msm_mux_ccu_async_in1, + msm_mux_ccu_async_in2, + msm_mux_ccu_async_in3, + msm_mux_ccu_async_in4, + msm_mux_ccu_async_in5, + msm_mux_ccu_i2c_scl0, + msm_mux_ccu_i2c_scl1, + msm_mux_ccu_i2c_scl2, + msm_mux_ccu_i2c_scl3, + msm_mux_ccu_i2c_scl4, + msm_mux_ccu_i2c_scl5, + msm_mux_ccu_i2c_scl6, + msm_mux_ccu_i2c_scl7, + msm_mux_ccu_i2c_scl8, + msm_mux_ccu_i2c_scl9, + msm_mux_ccu_i2c_sda0, + msm_mux_ccu_i2c_sda1, + msm_mux_ccu_i2c_sda2, + msm_mux_ccu_i2c_sda3, + msm_mux_ccu_i2c_sda4, + msm_mux_ccu_i2c_sda5, + msm_mux_ccu_i2c_sda6, + msm_mux_ccu_i2c_sda7, + msm_mux_ccu_i2c_sda8, + msm_mux_ccu_i2c_sda9, + msm_mux_ccu_timer0, + msm_mux_ccu_timer1, + msm_mux_ccu_timer10, + msm_mux_ccu_timer11, + msm_mux_ccu_timer12, + msm_mux_ccu_timer13, + msm_mux_ccu_timer14, + msm_mux_ccu_timer15, + msm_mux_ccu_timer2, + msm_mux_ccu_timer3, + msm_mux_ccu_timer4, + msm_mux_ccu_timer5, + msm_mux_ccu_timer6, + msm_mux_ccu_timer7, + msm_mux_ccu_timer8, + msm_mux_ccu_timer9, + msm_mux_clink_debug, + msm_mux_dbg_out, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi10, + msm_mux_ddr_pxi11, + msm_mux_ddr_pxi12, + msm_mux_ddr_pxi13, + msm_mux_ddr_pxi14, + msm_mux_ddr_pxi15, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_ddr_pxi6, + msm_mux_ddr_pxi7, + msm_mux_ddr_pxi8, + msm_mux_ddr_pxi9, + msm_mux_dp_rx0, + msm_mux_dp_rx00, + msm_mux_dp_rx01, + msm_mux_dp_rx0_mute, + msm_mux_dp_rx1, + msm_mux_dp_rx10, + msm_mux_dp_rx11, + msm_mux_dp_rx1_mute, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_hot, + msm_mux_edp1_lcd, + msm_mux_edp2_hot, + msm_mux_edp2_lcd, + msm_mux_edp3_hot, + msm_mux_edp3_lcd, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_mdc, + msm_mux_emac1_mdio, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_gcc_gp4_clk, + msm_mux_gcc_gp5_clk, + msm_mux_gcc_gp6_clk, + msm_mux_gcc_gp7_clk, + msm_mux_gcc_gp8_clk, + msm_mux_jitter_bist, + msm_mux_lbist_pass, + msm_mux_mbist_pass, + msm_mux_mdp0_vsync0_out, + msm_mux_mdp0_vsync10_out, + msm_mux_mdp0_vsync1_out, + msm_mux_mdp0_vsync2_out, + msm_mux_mdp0_vsync3_out, + msm_mux_mdp0_vsync4_out, + msm_mux_mdp0_vsync5_out, + msm_mux_mdp0_vsync6_out, + msm_mux_mdp0_vsync7_out, + msm_mux_mdp0_vsync8_out, + msm_mux_mdp0_vsync9_out, + msm_mux_mdp1_vsync0_out, + msm_mux_mdp1_vsync10_out, + msm_mux_mdp1_vsync1_out, + msm_mux_mdp1_vsync2_out, + msm_mux_mdp1_vsync3_out, + msm_mux_mdp1_vsync4_out, + msm_mux_mdp1_vsync5_out, + msm_mux_mdp1_vsync6_out, + msm_mux_mdp1_vsync7_out, + msm_mux_mdp1_vsync8_out, + msm_mux_mdp1_vsync9_out, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie3_clk_req_n, + msm_mux_phase_flag0, + msm_mux_phase_flag1, + msm_mux_phase_flag10, + msm_mux_phase_flag11, + msm_mux_phase_flag12, + msm_mux_phase_flag13, + msm_mux_phase_flag14, + msm_mux_phase_flag15, + msm_mux_phase_flag16, + msm_mux_phase_flag17, + msm_mux_phase_flag18, + msm_mux_phase_flag19, + msm_mux_phase_flag2, + msm_mux_phase_flag20, + msm_mux_phase_flag21, + msm_mux_phase_flag22, + msm_mux_phase_flag23, + msm_mux_phase_flag24, + msm_mux_phase_flag25, + msm_mux_phase_flag26, + msm_mux_phase_flag27, + msm_mux_phase_flag28, + msm_mux_phase_flag29, + msm_mux_phase_flag3, + msm_mux_phase_flag30, + msm_mux_phase_flag31, + msm_mux_phase_flag4, + msm_mux_phase_flag5, + msm_mux_phase_flag6, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_phase_flag9, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_pwrbrk_i_n, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qdss_gpio0, + msm_mux_qdss_gpio1, + msm_mux_qdss_gpio10, + msm_mux_qdss_gpio11, + msm_mux_qdss_gpio12, + msm_mux_qdss_gpio13, + msm_mux_qdss_gpio14, + msm_mux_qdss_gpio15, + msm_mux_qdss_gpio2, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio4, + msm_mux_qdss_gpio5, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_qdss_gpio8, + msm_mux_qdss_gpio9, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs0_n, + msm_mux_qspi_cs1_n, + msm_mux_qup0_se0_l0, + msm_mux_qup0_se0_l1, + msm_mux_qup0_se0_l2, + msm_mux_qup0_se0_l3, + msm_mux_qup0_se1_l0, + msm_mux_qup0_se1_l1, + msm_mux_qup0_se1_l2, + msm_mux_qup0_se1_l3, + msm_mux_qup0_se2_l0, + msm_mux_qup0_se2_l1, + msm_mux_qup0_se2_l2, + msm_mux_qup0_se2_l3, + msm_mux_qup0_se3_l0, + msm_mux_qup0_se3_l1, + msm_mux_qup0_se3_l2, + msm_mux_qup0_se3_l3, + msm_mux_qup0_se4_l0, + msm_mux_qup0_se4_l1, + msm_mux_qup0_se4_l2, + msm_mux_qup0_se4_l3, + msm_mux_qup0_se5_l0, + msm_mux_qup0_se5_l1, + msm_mux_qup0_se5_l2, + msm_mux_qup0_se5_l3, + msm_mux_qup1_se0_l0, + msm_mux_qup1_se0_l1, + msm_mux_qup1_se0_l2, + msm_mux_qup1_se0_l3, + msm_mux_qup1_se1_l0, + msm_mux_qup1_se1_l1, + msm_mux_qup1_se1_l2, + msm_mux_qup1_se1_l3, + msm_mux_qup1_se2_l0, + msm_mux_qup1_se2_l1, + msm_mux_qup1_se2_l2, + msm_mux_qup1_se2_l3, + msm_mux_qup1_se3_l0, + msm_mux_qup1_se3_l1, + msm_mux_qup1_se3_l2, + msm_mux_qup1_se3_l3, + msm_mux_qup1_se4_l0, + msm_mux_qup1_se4_l1, + msm_mux_qup1_se4_l2, + msm_mux_qup1_se4_l3, + msm_mux_qup1_se5_l0, + msm_mux_qup1_se5_l1, + msm_mux_qup1_se5_l2, + msm_mux_qup1_se5_l3, + msm_mux_qup1_se6_l0, + msm_mux_qup1_se6_l1, + msm_mux_qup1_se6_l2, + msm_mux_qup1_se6_l3, + msm_mux_qup2_se0_l0, + msm_mux_qup2_se0_l1, + msm_mux_qup2_se0_l2, + msm_mux_qup2_se0_l3, + msm_mux_qup2_se1_l0, + msm_mux_qup2_se1_l1, + msm_mux_qup2_se1_l2, + msm_mux_qup2_se1_l3, + msm_mux_qup2_se2_l0, + msm_mux_qup2_se2_l1, + msm_mux_qup2_se2_l2, + msm_mux_qup2_se2_l3, + msm_mux_qup2_se2_l4, + msm_mux_qup2_se3_l0, + msm_mux_qup2_se3_l1, + msm_mux_qup2_se3_l2, + msm_mux_qup2_se3_l3, + msm_mux_qup2_se4_l0, + msm_mux_qup2_se4_l1, + msm_mux_qup2_se4_l2, + msm_mux_qup2_se4_l3, + msm_mux_qup2_se4_l4, + msm_mux_qup2_se4_l5, + msm_mux_qup2_se4_l6, + msm_mux_qup2_se5_l0, + msm_mux_qup2_se5_l1, + msm_mux_qup2_se5_l2, + msm_mux_qup2_se5_l3, + msm_mux_qup2_se6_l0, + msm_mux_qup2_se6_l1, + msm_mux_qup2_se6_l2, + msm_mux_qup2_se6_l3, + msm_mux_qup3_se0_l0_mira, + msm_mux_qup3_se0_l0_mirb, + msm_mux_qup3_se0_l1_mira, + msm_mux_qup3_se0_l1_mirb, + msm_mux_qup3_se0_l2, + msm_mux_qup3_se0_l3, + msm_mux_qup3_se0_l4, + msm_mux_qup3_se0_l5, + msm_mux_qup3_se0_l6, + msm_mux_sailss_ospi, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_smb_alert, + msm_mux_smb_alert_n, + msm_mux_smb_clk, + msm_mux_smb_dat, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tsc_timer0, + msm_mux_tsc_timer1, + msm_mux_tsc_timer2, + msm_mux_tsc_timer3, + msm_mux_tsc_timer4, + msm_mux_tsc_timer5, + msm_mux_tsc_timer6, + msm_mux_tsc_timer7, + msm_mux_tsc_timer8, + msm_mux_tsc_timer9, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_tsense_pwm5, + msm_mux_tsense_pwm6, + msm_mux_tsense_pwm7, + msm_mux_tsense_pwm8, + msm_mux_usb0_hs, + msm_mux_usb0_phy_ps, + msm_mux_usb1_hs, + msm_mux_usb1_phy_ps, + msm_mux_usb2_hs, + msm_mux_usxgmii0_phy, + msm_mux_usxgmii1_phy, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", +}; + +static const char *const aoss_cti_groups[] =3D { + "gpio83", + "gpio84", + "gpio85", + "gpio86", +}; + +static const char *const atest_char0_groups[] =3D { + "gpio177", +}; + +static const char *const atest_char1_groups[] =3D { + "gpio178", +}; + +static const char *const atest_char2_groups[] =3D { + "gpio179", +}; + +static const char *const atest_char3_groups[] =3D { + "gpio180", +}; + +static const char *const atest_char_start_groups[] =3D { + "gpio176", +}; + +static const char *const atest_usb20_groups[] =3D { + "gpio126", + "gpio128", + "gpio130", +}; + +static const char *const atest_usb21_groups[] =3D { + "gpio127", + "gpio129", + "gpio131", +}; + +static const char *const aud_intfc0_clk_groups[] =3D { + "gpio57", +}; + +static const char *const aud_intfc0_data0_groups[] =3D { + "gpio59", +}; + +static const char *const aud_intfc0_data1_groups[] =3D { + "gpio60", +}; + +static const char *const aud_intfc0_data2_groups[] =3D { + "gpio61", +}; + +static const char *const aud_intfc0_data3_groups[] =3D { + "gpio62", +}; + +static const char *const aud_intfc0_data4_groups[] =3D { + "gpio63", +}; + +static const char *const aud_intfc0_data5_groups[] =3D { + "gpio64", +}; + +static const char *const aud_intfc0_data6_groups[] =3D { + "gpio65", +}; + +static const char *const aud_intfc0_data7_groups[] =3D { + "gpio66", +}; + +static const char *const aud_intfc0_ws_groups[] =3D { + "gpio58", +}; + +static const char *const aud_intfc10_clk_groups[] =3D { + "gpio61", +}; + +static const char *const aud_intfc10_data0_groups[] =3D { + "gpio81", +}; + +static const char *const aud_intfc10_data1_groups[] =3D { + "gpio82", +}; + +static const char *const aud_intfc10_ws_groups[] =3D { + "gpio62", +}; + +static const char *const aud_intfc1_clk_groups[] =3D { + "gpio67", +}; + +static const char *const aud_intfc1_data0_groups[] =3D { + "gpio69", +}; + +static const char *const aud_intfc1_data1_groups[] =3D { + "gpio70", +}; + +static const char *const aud_intfc1_data2_groups[] =3D { + "gpio71", +}; + +static const char *const aud_intfc1_data3_groups[] =3D { + "gpio72", +}; + +static const char *const aud_intfc1_data4_groups[] =3D { + "gpio73", +}; + +static const char *const aud_intfc1_data5_groups[] =3D { + "gpio74", +}; + +static const char *const aud_intfc1_data6_groups[] =3D { + "gpio75", +}; + +static const char *const aud_intfc1_data7_groups[] =3D { + "gpio76", +}; + +static const char *const aud_intfc1_ws_groups[] =3D { + "gpio68", +}; + +static const char *const aud_intfc2_clk_groups[] =3D { + "gpio77", +}; + +static const char *const aud_intfc2_data0_groups[] =3D { + "gpio79", +}; + +static const char *const aud_intfc2_data1_groups[] =3D { + "gpio80", +}; + +static const char *const aud_intfc2_data2_groups[] =3D { + "gpio81", +}; + +static const char *const aud_intfc2_data3_groups[] =3D { + "gpio82", +}; + +static const char *const aud_intfc2_ws_groups[] =3D { + "gpio78", +}; + +static const char *const aud_intfc3_clk_groups[] =3D { + "gpio83", +}; + +static const char *const aud_intfc3_data0_groups[] =3D { + "gpio85", +}; + +static const char *const aud_intfc3_data1_groups[] =3D { + "gpio86", +}; + +static const char *const aud_intfc3_ws_groups[] =3D { + "gpio84", +}; + +static const char *const aud_intfc4_clk_groups[] =3D { + "gpio87", +}; + +static const char *const aud_intfc4_data0_groups[] =3D { + "gpio89", +}; + +static const char *const aud_intfc4_data1_groups[] =3D { + "gpio90", +}; + +static const char *const aud_intfc4_ws_groups[] =3D { + "gpio88", +}; + +static const char *const aud_intfc5_clk_groups[] =3D { + "gpio91", +}; + +static const char *const aud_intfc5_data0_groups[] =3D { + "gpio93", +}; + +static const char *const aud_intfc5_data1_groups[] =3D { + "gpio94", +}; + +static const char *const aud_intfc5_ws_groups[] =3D { + "gpio92", +}; + +static const char *const aud_intfc6_clk_groups[] =3D { + "gpio95", +}; + +static const char *const aud_intfc6_data0_groups[] =3D { + "gpio97", +}; + +static const char *const aud_intfc6_data1_groups[] =3D { + "gpio98", +}; + +static const char *const aud_intfc6_ws_groups[] =3D { + "gpio96", +}; + +static const char *const aud_intfc7_clk_groups[] =3D { + "gpio63", +}; + +static const char *const aud_intfc7_data0_groups[] =3D { + "gpio65", +}; + +static const char *const aud_intfc7_data1_groups[] =3D { + "gpio66", +}; + +static const char *const aud_intfc7_ws_groups[] =3D { + "gpio64", +}; + +static const char *const aud_intfc8_clk_groups[] =3D { + "gpio73", +}; + +static const char *const aud_intfc8_data0_groups[] =3D { + "gpio75", +}; + +static const char *const aud_intfc8_data1_groups[] =3D { + "gpio76", +}; + +static const char *const aud_intfc8_ws_groups[] =3D { + "gpio74", +}; + +static const char *const aud_intfc9_clk_groups[] =3D { + "gpio70", +}; + +static const char *const aud_intfc9_data0_groups[] =3D { + "gpio72", +}; + +static const char *const aud_intfc9_ws_groups[] =3D { + "gpio71", +}; + +static const char *const aud_mclk0_mira_groups[] =3D { + "gpio99", +}; + +static const char *const aud_mclk0_mirb_groups[] =3D { + "gpio86", +}; + +static const char *const aud_mclk1_mira_groups[] =3D { + "gpio100", +}; + +static const char *const aud_mclk1_mirb_groups[] =3D { + "gpio90", +}; + +static const char *const aud_mclk2_mira_groups[] =3D { + "gpio101", +}; + +static const char *const aud_mclk2_mirb_groups[] =3D { + "gpio94", +}; + +static const char *const aud_refclk0_groups[] =3D { + "gpio100", +}; + +static const char *const aud_refclk1_groups[] =3D { + "gpio101", +}; + +static const char *const bist_done_groups[] =3D { + "gpio168", +}; + +static const char *const ccu_async_in0_groups[] =3D { + "gpio176", +}; + +static const char *const ccu_async_in1_groups[] =3D { + "gpio177", +}; + +static const char *const ccu_async_in2_groups[] =3D { + "gpio178", +}; + +static const char *const ccu_async_in3_groups[] =3D { + "gpio179", +}; + +static const char *const ccu_async_in4_groups[] =3D { + "gpio180", +}; + +static const char *const ccu_async_in5_groups[] =3D { + "gpio45", +}; + +static const char *const ccu_i2c_scl0_groups[] =3D { + "gpio16", +}; + +static const char *const ccu_i2c_scl1_groups[] =3D { + "gpio18", +}; + +static const char *const ccu_i2c_scl2_groups[] =3D { + "gpio20", +}; + +static const char *const ccu_i2c_scl3_groups[] =3D { + "gpio22", +}; + +static const char *const ccu_i2c_scl4_groups[] =3D { + "gpio24", +}; + +static const char *const ccu_i2c_scl5_groups[] =3D { + "gpio114", +}; + +static const char *const ccu_i2c_scl6_groups[] =3D { + "gpio116", +}; + +static const char *const ccu_i2c_scl7_groups[] =3D { + "gpio126", +}; + +static const char *const ccu_i2c_scl8_groups[] =3D { + "gpio130", +}; + +static const char *const ccu_i2c_scl9_groups[] =3D { + "gpio132", +}; + +static const char *const ccu_i2c_sda0_groups[] =3D { + "gpio15", +}; + +static const char *const ccu_i2c_sda1_groups[] =3D { + "gpio17", +}; + +static const char *const ccu_i2c_sda2_groups[] =3D { + "gpio19", +}; + +static const char *const ccu_i2c_sda3_groups[] =3D { + "gpio21", +}; + +static const char *const ccu_i2c_sda4_groups[] =3D { + "gpio23", +}; + +static const char *const ccu_i2c_sda5_groups[] =3D { + "gpio113", +}; + +static const char *const ccu_i2c_sda6_groups[] =3D { + "gpio115", +}; + +static const char *const ccu_i2c_sda7_groups[] =3D { + "gpio125", +}; + +static const char *const ccu_i2c_sda8_groups[] =3D { + "gpio129", +}; + +static const char *const ccu_i2c_sda9_groups[] =3D { + "gpio131", +}; + +static const char *const ccu_timer0_groups[] =3D { + "gpio25", +}; + +static const char *const ccu_timer1_groups[] =3D { + "gpio26", +}; + +static const char *const ccu_timer10_groups[] =3D { + "gpio143", +}; + +static const char *const ccu_timer11_groups[] =3D { + "gpio144", +}; + +static const char *const ccu_timer12_groups[] =3D { + "gpio150", +}; + +static const char *const ccu_timer13_groups[] =3D { + "gpio151", +}; + +static const char *const ccu_timer14_groups[] =3D { + "gpio152", +}; + +static const char *const ccu_timer15_groups[] =3D { + "gpio153", +}; + +static const char *const ccu_timer2_groups[] =3D { + "gpio27", +}; + +static const char *const ccu_timer3_groups[] =3D { + "gpio28", +}; + +static const char *const ccu_timer4_groups[] =3D { + "gpio29", +}; + +static const char *const ccu_timer5_groups[] =3D { + "gpio30", +}; + +static const char *const ccu_timer6_groups[] =3D { + "gpio31", +}; + +static const char *const ccu_timer7_groups[] =3D { + "gpio32", +}; + +static const char *const ccu_timer8_groups[] =3D { + "gpio33", +}; + +static const char *const ccu_timer9_groups[] =3D { + "gpio34", +}; + +static const char *const clink_debug_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio51", + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const dbg_out_groups[] =3D { + "gpio113", +}; + +static const char *const dbg_out_clk_groups[] =3D { + "gpio165", +}; + +static const char *const ddr_bist_complete_groups[] =3D { + "gpio37", +}; + +static const char *const ddr_bist_fail_groups[] =3D { + "gpio39", +}; + +static const char *const ddr_bist_start_groups[] =3D { + "gpio36", +}; + +static const char *const ddr_bist_stop_groups[] =3D { + "gpio38", +}; + +static const char *const ddr_pxi0_groups[] =3D { + "gpio99", + "gpio100", +}; + +static const char *const ddr_pxi1_groups[] =3D { + "gpio109", + "gpio110", +}; + +static const char *const ddr_pxi10_groups[] =3D { + "gpio130", + "gpio131", +}; + +static const char *const ddr_pxi11_groups[] =3D { + "gpio132", + "gpio133", +}; + +static const char *const ddr_pxi12_groups[] =3D { + "gpio134", + "gpio135", +}; + +static const char *const ddr_pxi13_groups[] =3D { + "gpio136", + "gpio137", +}; + +static const char *const ddr_pxi14_groups[] =3D { + "gpio138", + "gpio139", +}; + +static const char *const ddr_pxi15_groups[] =3D { + "gpio162", + "gpio163", +}; + +static const char *const ddr_pxi2_groups[] =3D { + "gpio113", + "gpio114", +}; + +static const char *const ddr_pxi3_groups[] =3D { + "gpio115", + "gpio116", +}; + +static const char *const ddr_pxi4_groups[] =3D { + "gpio117", + "gpio118", +}; + +static const char *const ddr_pxi5_groups[] =3D { + "gpio164", + "gpio165", +}; + +static const char *const ddr_pxi6_groups[] =3D { + "gpio119", + "gpio120", +}; + +static const char *const ddr_pxi7_groups[] =3D { + "gpio121", + "gpio122", +}; + +static const char *const ddr_pxi8_groups[] =3D { + "gpio126", + "gpio127", +}; + +static const char *const ddr_pxi9_groups[] =3D { + "gpio128", + "gpio129", +}; + +static const char *const dp_rx0_groups[] =3D { + "gpio55", "gpio83", "gpio84", "gpio85", "gpio86", + "gpio88", "gpio89", "gpio137", "gpio138", +}; + +static const char *const dp_rx00_groups[] =3D { + "gpio99", +}; + +static const char *const dp_rx01_groups[] =3D { + "gpio100", +}; + +static const char *const dp_rx0_mute_groups[] =3D { + "gpio35", +}; + +static const char *const dp_rx1_groups[] =3D { + "gpio56", "gpio92", "gpio93", "gpio95", "gpio96", + "gpio97", "gpio98", "gpio158", "gpio159", +}; + +static const char *const dp_rx10_groups[] =3D { + "gpio121", +}; + +static const char *const dp_rx11_groups[] =3D { + "gpio122", +}; + +static const char *const dp_rx1_mute_groups[] =3D { + "gpio36", +}; + +static const char *const edp0_hot_groups[] =3D { + "gpio51", +}; + +static const char *const edp0_lcd_groups[] =3D { + "gpio47", +}; + +static const char *const edp1_hot_groups[] =3D { + "gpio52", +}; + +static const char *const edp1_lcd_groups[] =3D { + "gpio48", +}; + +static const char *const edp2_hot_groups[] =3D { + "gpio53", +}; + +static const char *const edp2_lcd_groups[] =3D { + "gpio49", +}; + +static const char *const edp3_hot_groups[] =3D { + "gpio54", +}; + +static const char *const edp3_lcd_groups[] =3D { + "gpio50", +}; + +static const char *const emac0_mcg0_groups[] =3D { + "gpio16", +}; + +static const char *const emac0_mcg1_groups[] =3D { + "gpio17", +}; + +static const char *const emac0_mcg2_groups[] =3D { + "gpio18", +}; + +static const char *const emac0_mcg3_groups[] =3D { + "gpio19", +}; + +static const char *const emac0_mdc_groups[] =3D { + "gpio47", +}; + +static const char *const emac0_mdio_groups[] =3D { + "gpio48", +}; + +static const char *const emac0_ptp_groups[] =3D { + "gpio133", "gpio134", "gpio135", "gpio136", + "gpio139", "gpio140", "gpio141", "gpio142", +}; + +static const char *const emac1_mcg0_groups[] =3D { + "gpio20", +}; + +static const char *const emac1_mcg1_groups[] =3D { + "gpio21", +}; + +static const char *const emac1_mcg2_groups[] =3D { + "gpio22", +}; + +static const char *const emac1_mcg3_groups[] =3D { + "gpio23", +}; + +static const char *const emac1_mdc_groups[] =3D { + "gpio49", +}; + +static const char *const emac1_mdio_groups[] =3D { + "gpio50", +}; + +static const char *const emac1_ptp_groups[] =3D { + "gpio37", "gpio38", "gpio39", "gpio40", + "gpio41", "gpio42", "gpio43", "gpio44", +}; + +static const char *const gcc_gp1_clk_groups[] =3D { + "gpio51", +}; + +static const char *const gcc_gp2_clk_groups[] =3D { + "gpio52", +}; + +static const char *const gcc_gp3_clk_groups[] =3D { + "gpio42", +}; + +static const char *const gcc_gp4_clk_groups[] =3D { + "gpio43", +}; + +static const char *const gcc_gp5_clk_groups[] =3D { + "gpio105", +}; + +static const char *const gcc_gp6_clk_groups[] =3D { + "gpio106", +}; + +static const char *const gcc_gp7_clk_groups[] =3D { + "gpio13", +}; + +static const char *const gcc_gp8_clk_groups[] =3D { + "gpio14", +}; + +static const char *const jitter_bist_groups[] =3D { + "gpio123", + "gpio138", +}; + +static const char *const lbist_pass_groups[] =3D { + "gpio121", +}; + +static const char *const mbist_pass_groups[] =3D { + "gpio122", +}; + +static const char *const mdp0_vsync0_out_groups[] =3D { + "gpio113", +}; + +static const char *const mdp0_vsync10_out_groups[] =3D { + "gpio143", +}; + +static const char *const mdp0_vsync1_out_groups[] =3D { + "gpio114", +}; + +static const char *const mdp0_vsync2_out_groups[] =3D { + "gpio115", +}; + +static const char *const mdp0_vsync3_out_groups[] =3D { + "gpio116", +}; + +static const char *const mdp0_vsync4_out_groups[] =3D { + "gpio121", +}; + +static const char *const mdp0_vsync5_out_groups[] =3D { + "gpio122", +}; + +static const char *const mdp0_vsync6_out_groups[] =3D { + "gpio139", +}; + +static const char *const mdp0_vsync7_out_groups[] =3D { + "gpio140", +}; + +static const char *const mdp0_vsync8_out_groups[] =3D { + "gpio141", +}; + +static const char *const mdp0_vsync9_out_groups[] =3D { + "gpio142", +}; + +static const char *const mdp1_vsync0_out_groups[] =3D { + "gpio123", +}; + +static const char *const mdp1_vsync10_out_groups[] =3D { + "gpio135", +}; + +static const char *const mdp1_vsync1_out_groups[] =3D { + "gpio124", +}; + +static const char *const mdp1_vsync2_out_groups[] =3D { + "gpio125", +}; + +static const char *const mdp1_vsync3_out_groups[] =3D { + "gpio126", +}; + +static const char *const mdp1_vsync4_out_groups[] =3D { + "gpio129", +}; + +static const char *const mdp1_vsync5_out_groups[] =3D { + "gpio130", +}; + +static const char *const mdp1_vsync6_out_groups[] =3D { + "gpio131", +}; + +static const char *const mdp1_vsync7_out_groups[] =3D { + "gpio132", +}; + +static const char *const mdp1_vsync8_out_groups[] =3D { + "gpio133", +}; + +static const char *const mdp1_vsync9_out_groups[] =3D { + "gpio134", +}; + +static const char *const mdp_vsync_e_groups[] =3D { + "gpio109", +}; + +static const char *const mdp_vsync_p_groups[] =3D { + "gpio110", +}; + +static const char *const mdp_vsync_s_groups[] =3D { + "gpio144", +}; + +static const char *const pcie0_clk_req_n_groups[] =3D { + "gpio1", +}; + +static const char *const pcie1_clk_req_n_groups[] =3D { + "gpio4", +}; + +static const char *const pcie2_clk_req_n_groups[] =3D { + "gpio7", +}; + +static const char *const pcie3_clk_req_n_groups[] =3D { + "gpio10", +}; + +static const char *const phase_flag0_groups[] =3D { + "gpio98", +}; + +static const char *const phase_flag1_groups[] =3D { + "gpio82", +}; + +static const char *const phase_flag10_groups[] =3D { + "gpio90", +}; + +static const char *const phase_flag11_groups[] =3D { + "gpio91", +}; + +static const char *const phase_flag12_groups[] =3D { + "gpio92", +}; + +static const char *const phase_flag13_groups[] =3D { + "gpio93", +}; + +static const char *const phase_flag14_groups[] =3D { + "gpio94", +}; + +static const char *const phase_flag15_groups[] =3D { + "gpio95", +}; + +static const char *const phase_flag16_groups[] =3D { + "gpio96", +}; + +static const char *const phase_flag17_groups[] =3D { + "gpio101", +}; + +static const char *const phase_flag18_groups[] =3D { + "gpio67", +}; + +static const char *const phase_flag19_groups[] =3D { + "gpio68", +}; + +static const char *const phase_flag2_groups[] =3D { + "gpio81", +}; + +static const char *const phase_flag20_groups[] =3D { + "gpio69", +}; + +static const char *const phase_flag21_groups[] =3D { + "gpio70", +}; + +static const char *const phase_flag22_groups[] =3D { + "gpio71", +}; + +static const char *const phase_flag23_groups[] =3D { + "gpio72", +}; + +static const char *const phase_flag24_groups[] =3D { + "gpio73", +}; + +static const char *const phase_flag25_groups[] =3D { + "gpio74", +}; + +static const char *const phase_flag26_groups[] =3D { + "gpio75", +}; + +static const char *const phase_flag27_groups[] =3D { + "gpio76", +}; + +static const char *const phase_flag28_groups[] =3D { + "gpio83", +}; + +static const char *const phase_flag29_groups[] =3D { + "gpio84", +}; + +static const char *const phase_flag3_groups[] =3D { + "gpio80", +}; + +static const char *const phase_flag30_groups[] =3D { + "gpio85", +}; + +static const char *const phase_flag31_groups[] =3D { + "gpio86", +}; + +static const char *const phase_flag4_groups[] =3D { + "gpio79", +}; + +static const char *const phase_flag5_groups[] =3D { + "gpio78", +}; + +static const char *const phase_flag6_groups[] =3D { + "gpio77", +}; + +static const char *const phase_flag7_groups[] =3D { + "gpio87", +}; + +static const char *const phase_flag8_groups[] =3D { + "gpio88", +}; + +static const char *const phase_flag9_groups[] =3D { + "gpio89", +}; + +static const char *const pll_bist_sync_groups[] =3D { + "gpio176", +}; + +static const char *const pll_clk_aux_groups[] =3D { + "gpio100", +}; + +static const char *const prng_rosc0_groups[] =3D { + "gpio117", +}; + +static const char *const prng_rosc1_groups[] =3D { + "gpio118", +}; + +static const char *const pwrbrk_i_n_groups[] =3D { + "gpio167", +}; + +static const char *const qdss_cti_groups[] =3D { + "gpio41", "gpio42", "gpio110", "gpio138", + "gpio142", "gpio144", "gpio162", "gpio163", +}; + +static const char *const qdss_gpio_groups[] =3D { + "gpio75", + "gpio76", + "gpio93", + "gpio108", +}; + +static const char *const qdss_gpio0_groups[] =3D { + "gpio67", + "gpio85", +}; + +static const char *const qdss_gpio1_groups[] =3D { + "gpio68", + "gpio86", +}; + +static const char *const qdss_gpio10_groups[] =3D { + "gpio79", + "gpio96", +}; + +static const char *const qdss_gpio11_groups[] =3D { + "gpio80", + "gpio97", +}; + +static const char *const qdss_gpio12_groups[] =3D { + "gpio81", + "gpio98", +}; + +static const char *const qdss_gpio13_groups[] =3D { + "gpio82", + "gpio99", +}; + +static const char *const qdss_gpio14_groups[] =3D { + "gpio83", + "gpio100", +}; + +static const char *const qdss_gpio15_groups[] =3D { + "gpio84", + "gpio101", +}; + +static const char *const qdss_gpio2_groups[] =3D { + "gpio69", + "gpio87", +}; + +static const char *const qdss_gpio3_groups[] =3D { + "gpio70", + "gpio88", +}; + +static const char *const qdss_gpio4_groups[] =3D { + "gpio71", + "gpio89", +}; + +static const char *const qdss_gpio5_groups[] =3D { + "gpio72", + "gpio90", +}; + +static const char *const qdss_gpio6_groups[] =3D { + "gpio73", + "gpio91", +}; + +static const char *const qdss_gpio7_groups[] =3D { + "gpio74", + "gpio92", +}; + +static const char *const qdss_gpio8_groups[] =3D { + "gpio77", + "gpio94", +}; + +static const char *const qdss_gpio9_groups[] =3D { + "gpio78", + "gpio95", +}; + +static const char *const qspi0_groups[] =3D { + "gpio102", +}; + +static const char *const qspi1_groups[] =3D { + "gpio103", +}; + +static const char *const qspi2_groups[] =3D { + "gpio106", +}; + +static const char *const qspi3_groups[] =3D { + "gpio107", +}; + +static const char *const qspi_clk_groups[] =3D { + "gpio104", +}; + +static const char *const qspi_cs0_n_groups[] =3D { + "gpio105", +}; + +static const char *const qspi_cs1_n_groups[] =3D { + "gpio108", +}; + +static const char *const qup0_se0_l0_groups[] =3D { + "gpio111", +}; + +static const char *const qup0_se0_l1_groups[] =3D { + "gpio112", +}; + +static const char *const qup0_se0_l2_groups[] =3D { + "gpio109", +}; + +static const char *const qup0_se0_l3_groups[] =3D { + "gpio110", +}; + +static const char *const qup0_se1_l0_groups[] =3D { + "gpio111", +}; + +static const char *const qup0_se1_l1_groups[] =3D { + "gpio112", +}; + +static const char *const qup0_se1_l2_groups[] =3D { + "gpio109", +}; + +static const char *const qup0_se1_l3_groups[] =3D { + "gpio110", +}; + +static const char *const qup0_se2_l0_groups[] =3D { + "gpio113", +}; + +static const char *const qup0_se2_l1_groups[] =3D { + "gpio114", +}; + +static const char *const qup0_se2_l2_groups[] =3D { + "gpio115", +}; + +static const char *const qup0_se2_l3_groups[] =3D { + "gpio116", +}; + +static const char *const qup0_se3_l0_groups[] =3D { + "gpio115", +}; + +static const char *const qup0_se3_l1_groups[] =3D { + "gpio116", +}; + +static const char *const qup0_se3_l2_groups[] =3D { + "gpio113", +}; + +static const char *const qup0_se3_l3_groups[] =3D { + "gpio114", +}; + +static const char *const qup0_se4_l0_groups[] =3D { + "gpio117", +}; + +static const char *const qup0_se4_l1_groups[] =3D { + "gpio118", +}; + +static const char *const qup0_se4_l2_groups[] =3D { + "gpio119", +}; + +static const char *const qup0_se4_l3_groups[] =3D { + "gpio120", +}; + +static const char *const qup0_se5_l0_groups[] =3D { + "gpio121", +}; + +static const char *const qup0_se5_l1_groups[] =3D { + "gpio122", +}; + +static const char *const qup0_se5_l2_groups[] =3D { + "gpio109", +}; + +static const char *const qup0_se5_l3_groups[] =3D { + "gpio110", +}; + +static const char *const qup1_se0_l0_groups[] =3D { + "gpio123", +}; + +static const char *const qup1_se0_l1_groups[] =3D { + "gpio124", +}; + +static const char *const qup1_se0_l2_groups[] =3D { + "gpio125", +}; + +static const char *const qup1_se0_l3_groups[] =3D { + "gpio126", +}; + +static const char *const qup1_se1_l0_groups[] =3D { + "gpio125", +}; + +static const char *const qup1_se1_l1_groups[] =3D { + "gpio126", +}; + +static const char *const qup1_se1_l2_groups[] =3D { + "gpio123", +}; + +static const char *const qup1_se1_l3_groups[] =3D { + "gpio124", +}; + +static const char *const qup1_se2_l0_groups[] =3D { + "gpio127", +}; + +static const char *const qup1_se2_l1_groups[] =3D { + "gpio128", +}; + +static const char *const qup1_se2_l2_groups[] =3D { + "gpio127", +}; + +static const char *const qup1_se2_l3_groups[] =3D { + "gpio128", +}; + +static const char *const qup1_se3_l0_groups[] =3D { + "gpio129", +}; + +static const char *const qup1_se3_l1_groups[] =3D { + "gpio130", +}; + +static const char *const qup1_se3_l2_groups[] =3D { + "gpio129", +}; + +static const char *const qup1_se3_l3_groups[] =3D { + "gpio130", +}; + +static const char *const qup1_se4_l0_groups[] =3D { + "gpio131", +}; + +static const char *const qup1_se4_l1_groups[] =3D { + "gpio132", +}; + +static const char *const qup1_se4_l2_groups[] =3D { + "gpio137", +}; + +static const char *const qup1_se4_l3_groups[] =3D { + "gpio138", +}; + +static const char *const qup1_se5_l0_groups[] =3D { + "gpio133", +}; + +static const char *const qup1_se5_l1_groups[] =3D { + "gpio134", +}; + +static const char *const qup1_se5_l2_groups[] =3D { + "gpio135", +}; + +static const char *const qup1_se5_l3_groups[] =3D { + "gpio136", +}; + +static const char *const qup1_se6_l0_groups[] =3D { + "gpio137", +}; + +static const char *const qup1_se6_l1_groups[] =3D { + "gpio138", +}; + +static const char *const qup1_se6_l2_groups[] =3D { + "gpio131", +}; + +static const char *const qup1_se6_l3_groups[] =3D { + "gpio132", +}; + +static const char *const qup2_se0_l0_groups[] =3D { + "gpio139", +}; + +static const char *const qup2_se0_l1_groups[] =3D { + "gpio140", +}; + +static const char *const qup2_se0_l2_groups[] =3D { + "gpio141", +}; + +static const char *const qup2_se0_l3_groups[] =3D { + "gpio142", +}; + +static const char *const qup2_se1_l0_groups[] =3D { + "gpio154", +}; + +static const char *const qup2_se1_l1_groups[] =3D { + "gpio155", +}; + +static const char *const qup2_se1_l2_groups[] =3D { + "gpio143", +}; + +static const char *const qup2_se1_l3_groups[] =3D { + "gpio144", +}; + +static const char *const qup2_se2_l0_groups[] =3D { + "gpio145", +}; + +static const char *const qup2_se2_l1_groups[] =3D { + "gpio146", +}; + +static const char *const qup2_se2_l2_groups[] =3D { + "gpio147", +}; + +static const char *const qup2_se2_l3_groups[] =3D { + "gpio148", +}; + +static const char *const qup2_se2_l4_groups[] =3D { + "gpio149", +}; + +static const char *const qup2_se3_l0_groups[] =3D { + "gpio150", +}; + +static const char *const qup2_se3_l1_groups[] =3D { + "gpio151", +}; + +static const char *const qup2_se3_l2_groups[] =3D { + "gpio152", +}; + +static const char *const qup2_se3_l3_groups[] =3D { + "gpio153", +}; + +static const char *const qup2_se4_l0_groups[] =3D { + "gpio154", +}; + +static const char *const qup2_se4_l1_groups[] =3D { + "gpio155", +}; + +static const char *const qup2_se4_l2_groups[] =3D { + "gpio143", +}; + +static const char *const qup2_se4_l3_groups[] =3D { + "gpio144", +}; + +static const char *const qup2_se4_l4_groups[] =3D { + "gpio150", +}; + +static const char *const qup2_se4_l5_groups[] =3D { + "gpio151", +}; + +static const char *const qup2_se4_l6_groups[] =3D { + "gpio152", +}; + +static const char *const qup2_se5_l0_groups[] =3D { + "gpio156", +}; + +static const char *const qup2_se5_l1_groups[] =3D { + "gpio157", +}; + +static const char *const qup2_se5_l2_groups[] =3D { + "gpio158", +}; + +static const char *const qup2_se5_l3_groups[] =3D { + "gpio159", +}; + +static const char *const qup2_se6_l0_groups[] =3D { + "gpio158", +}; + +static const char *const qup2_se6_l1_groups[] =3D { + "gpio159", +}; + +static const char *const qup2_se6_l2_groups[] =3D { + "gpio156", +}; + +static const char *const qup2_se6_l3_groups[] =3D { + "gpio157", +}; + +static const char *const qup3_se0_l0_mira_groups[] =3D { + "gpio102", +}; + +static const char *const qup3_se0_l0_mirb_groups[] =3D { + "gpio103", +}; + +static const char *const qup3_se0_l1_mira_groups[] =3D { + "gpio103", +}; + +static const char *const qup3_se0_l1_mirb_groups[] =3D { + "gpio102", +}; + +static const char *const qup3_se0_l2_groups[] =3D { + "gpio104", +}; + +static const char *const qup3_se0_l3_groups[] =3D { + "gpio105", +}; + +static const char *const qup3_se0_l4_groups[] =3D { + "gpio106", +}; + +static const char *const qup3_se0_l5_groups[] =3D { + "gpio107", +}; + +static const char *const qup3_se0_l6_groups[] =3D { + "gpio108", +}; + +static const char *const sailss_ospi_groups[] =3D { + "gpio164", + "gpio165", +}; + +static const char *const sdc4_clk_groups[] =3D { + "gpio175", +}; + +static const char *const sdc4_cmd_groups[] =3D { + "gpio174", +}; + +static const char *const sdc4_data_groups[] =3D { + "gpio170", + "gpio171", + "gpio172", + "gpio173", +}; + +static const char *const smb_alert_groups[] =3D { + "gpio110", +}; + +static const char *const smb_alert_n_groups[] =3D { + "gpio109", +}; + +static const char *const smb_clk_groups[] =3D { + "gpio112", +}; + +static const char *const smb_dat_groups[] =3D { + "gpio111", +}; + +static const char *const tb_trig_sdc4_groups[] =3D { + "gpio169", +}; + +static const char *const tmess_prng0_groups[] =3D { + "gpio94", +}; + +static const char *const tmess_prng1_groups[] =3D { + "gpio95", +}; + +static const char *const tsc_timer0_groups[] =3D { + "gpio25", +}; + +static const char *const tsc_timer1_groups[] =3D { + "gpio26", +}; + +static const char *const tsc_timer2_groups[] =3D { + "gpio27", +}; + +static const char *const tsc_timer3_groups[] =3D { + "gpio28", +}; + +static const char *const tsc_timer4_groups[] =3D { + "gpio29", +}; + +static const char *const tsc_timer5_groups[] =3D { + "gpio30", +}; + +static const char *const tsc_timer6_groups[] =3D { + "gpio31", +}; + +static const char *const tsc_timer7_groups[] =3D { + "gpio32", +}; + +static const char *const tsc_timer8_groups[] =3D { + "gpio33", +}; + +static const char *const tsc_timer9_groups[] =3D { + "gpio34", +}; + +static const char *const tsense_pwm1_groups[] =3D { + "gpio43", +}; + +static const char *const tsense_pwm2_groups[] =3D { + "gpio44", +}; + +static const char *const tsense_pwm3_groups[] =3D { + "gpio45", +}; + +static const char *const tsense_pwm4_groups[] =3D { + "gpio46", +}; + +static const char *const tsense_pwm5_groups[] =3D { + "gpio47", +}; + +static const char *const tsense_pwm6_groups[] =3D { + "gpio48", +}; + +static const char *const tsense_pwm7_groups[] =3D { + "gpio49", +}; + +static const char *const tsense_pwm8_groups[] =3D { + "gpio50", +}; + +static const char *const usb0_hs_groups[] =3D { + "gpio12", +}; + +static const char *const usb0_phy_ps_groups[] =3D { + "gpio164", +}; + +static const char *const usb1_hs_groups[] =3D { + "gpio13", +}; + +static const char *const usb1_phy_ps_groups[] =3D { + "gpio165", +}; + +static const char *const usb2_hs_groups[] =3D { + "gpio14", +}; + +static const char *const usxgmii0_phy_groups[] =3D { + "gpio45", +}; + +static const char *const usxgmii1_phy_groups[] =3D { + "gpio46", +}; + +static const char *const vsense_trigger_mirnat_groups[] =3D { + "gpio132", +}; + +static const char *const wcn_sw_groups[] =3D { + "gpio161", +}; + +static const char *const wcn_sw_ctrl_groups[] =3D { + "gpio160", +}; + +static const struct pinfunction nord_functions[] =3D { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(aud_intfc0_clk), + MSM_PIN_FUNCTION(aud_intfc0_data0), + MSM_PIN_FUNCTION(aud_intfc0_data1), + MSM_PIN_FUNCTION(aud_intfc0_data2), + MSM_PIN_FUNCTION(aud_intfc0_data3), + MSM_PIN_FUNCTION(aud_intfc0_data4), + MSM_PIN_FUNCTION(aud_intfc0_data5), + MSM_PIN_FUNCTION(aud_intfc0_data6), + MSM_PIN_FUNCTION(aud_intfc0_data7), + MSM_PIN_FUNCTION(aud_intfc0_ws), + MSM_PIN_FUNCTION(aud_intfc10_clk), + MSM_PIN_FUNCTION(aud_intfc10_data0), + MSM_PIN_FUNCTION(aud_intfc10_data1), + MSM_PIN_FUNCTION(aud_intfc10_ws), + MSM_PIN_FUNCTION(aud_intfc1_clk), + MSM_PIN_FUNCTION(aud_intfc1_data0), + MSM_PIN_FUNCTION(aud_intfc1_data1), + MSM_PIN_FUNCTION(aud_intfc1_data2), + MSM_PIN_FUNCTION(aud_intfc1_data3), + MSM_PIN_FUNCTION(aud_intfc1_data4), + MSM_PIN_FUNCTION(aud_intfc1_data5), + MSM_PIN_FUNCTION(aud_intfc1_data6), + MSM_PIN_FUNCTION(aud_intfc1_data7), + MSM_PIN_FUNCTION(aud_intfc1_ws), + MSM_PIN_FUNCTION(aud_intfc2_clk), + MSM_PIN_FUNCTION(aud_intfc2_data0), + MSM_PIN_FUNCTION(aud_intfc2_data1), + MSM_PIN_FUNCTION(aud_intfc2_data2), + MSM_PIN_FUNCTION(aud_intfc2_data3), + MSM_PIN_FUNCTION(aud_intfc2_ws), + MSM_PIN_FUNCTION(aud_intfc3_clk), + MSM_PIN_FUNCTION(aud_intfc3_data0), + MSM_PIN_FUNCTION(aud_intfc3_data1), + MSM_PIN_FUNCTION(aud_intfc3_ws), + MSM_PIN_FUNCTION(aud_intfc4_clk), + MSM_PIN_FUNCTION(aud_intfc4_data0), + MSM_PIN_FUNCTION(aud_intfc4_data1), + MSM_PIN_FUNCTION(aud_intfc4_ws), + MSM_PIN_FUNCTION(aud_intfc5_clk), + MSM_PIN_FUNCTION(aud_intfc5_data0), + MSM_PIN_FUNCTION(aud_intfc5_data1), + MSM_PIN_FUNCTION(aud_intfc5_ws), + MSM_PIN_FUNCTION(aud_intfc6_clk), + MSM_PIN_FUNCTION(aud_intfc6_data0), + MSM_PIN_FUNCTION(aud_intfc6_data1), + MSM_PIN_FUNCTION(aud_intfc6_ws), + MSM_PIN_FUNCTION(aud_intfc7_clk), + MSM_PIN_FUNCTION(aud_intfc7_data0), + MSM_PIN_FUNCTION(aud_intfc7_data1), + MSM_PIN_FUNCTION(aud_intfc7_ws), + MSM_PIN_FUNCTION(aud_intfc8_clk), + MSM_PIN_FUNCTION(aud_intfc8_data0), + MSM_PIN_FUNCTION(aud_intfc8_data1), + MSM_PIN_FUNCTION(aud_intfc8_ws), + MSM_PIN_FUNCTION(aud_intfc9_clk), + MSM_PIN_FUNCTION(aud_intfc9_data0), + MSM_PIN_FUNCTION(aud_intfc9_ws), + MSM_PIN_FUNCTION(aud_mclk0_mira), + MSM_PIN_FUNCTION(aud_mclk0_mirb), + MSM_PIN_FUNCTION(aud_mclk1_mira), + MSM_PIN_FUNCTION(aud_mclk1_mirb), + MSM_PIN_FUNCTION(aud_mclk2_mira), + MSM_PIN_FUNCTION(aud_mclk2_mirb), + MSM_PIN_FUNCTION(aud_refclk0), + MSM_PIN_FUNCTION(aud_refclk1), + MSM_PIN_FUNCTION(bist_done), + MSM_PIN_FUNCTION(ccu_async_in0), + MSM_PIN_FUNCTION(ccu_async_in1), + MSM_PIN_FUNCTION(ccu_async_in2), + MSM_PIN_FUNCTION(ccu_async_in3), + MSM_PIN_FUNCTION(ccu_async_in4), + MSM_PIN_FUNCTION(ccu_async_in5), + MSM_PIN_FUNCTION(ccu_i2c_scl0), + MSM_PIN_FUNCTION(ccu_i2c_scl1), + MSM_PIN_FUNCTION(ccu_i2c_scl2), + MSM_PIN_FUNCTION(ccu_i2c_scl3), + MSM_PIN_FUNCTION(ccu_i2c_scl4), + MSM_PIN_FUNCTION(ccu_i2c_scl5), + MSM_PIN_FUNCTION(ccu_i2c_scl6), + MSM_PIN_FUNCTION(ccu_i2c_scl7), + MSM_PIN_FUNCTION(ccu_i2c_scl8), + MSM_PIN_FUNCTION(ccu_i2c_scl9), + MSM_PIN_FUNCTION(ccu_i2c_sda0), + MSM_PIN_FUNCTION(ccu_i2c_sda1), + MSM_PIN_FUNCTION(ccu_i2c_sda2), + MSM_PIN_FUNCTION(ccu_i2c_sda3), + MSM_PIN_FUNCTION(ccu_i2c_sda4), + MSM_PIN_FUNCTION(ccu_i2c_sda5), + MSM_PIN_FUNCTION(ccu_i2c_sda6), + MSM_PIN_FUNCTION(ccu_i2c_sda7), + MSM_PIN_FUNCTION(ccu_i2c_sda8), + MSM_PIN_FUNCTION(ccu_i2c_sda9), + MSM_PIN_FUNCTION(ccu_timer0), + MSM_PIN_FUNCTION(ccu_timer1), + MSM_PIN_FUNCTION(ccu_timer10), + MSM_PIN_FUNCTION(ccu_timer11), + MSM_PIN_FUNCTION(ccu_timer12), + MSM_PIN_FUNCTION(ccu_timer13), + MSM_PIN_FUNCTION(ccu_timer14), + MSM_PIN_FUNCTION(ccu_timer15), + MSM_PIN_FUNCTION(ccu_timer2), + MSM_PIN_FUNCTION(ccu_timer3), + MSM_PIN_FUNCTION(ccu_timer4), + MSM_PIN_FUNCTION(ccu_timer5), + MSM_PIN_FUNCTION(ccu_timer6), + MSM_PIN_FUNCTION(ccu_timer7), + MSM_PIN_FUNCTION(ccu_timer8), + MSM_PIN_FUNCTION(ccu_timer9), + MSM_PIN_FUNCTION(clink_debug), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi10), + MSM_PIN_FUNCTION(ddr_pxi11), + MSM_PIN_FUNCTION(ddr_pxi12), + MSM_PIN_FUNCTION(ddr_pxi13), + MSM_PIN_FUNCTION(ddr_pxi14), + MSM_PIN_FUNCTION(ddr_pxi15), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(ddr_pxi4), + MSM_PIN_FUNCTION(ddr_pxi5), + MSM_PIN_FUNCTION(ddr_pxi6), + MSM_PIN_FUNCTION(ddr_pxi7), + MSM_PIN_FUNCTION(ddr_pxi8), + MSM_PIN_FUNCTION(ddr_pxi9), + MSM_PIN_FUNCTION(dp_rx0), + MSM_PIN_FUNCTION(dp_rx00), + MSM_PIN_FUNCTION(dp_rx01), + MSM_PIN_FUNCTION(dp_rx0_mute), + MSM_PIN_FUNCTION(dp_rx1), + MSM_PIN_FUNCTION(dp_rx10), + MSM_PIN_FUNCTION(dp_rx11), + MSM_PIN_FUNCTION(dp_rx1_mute), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_hot), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(edp2_hot), + MSM_PIN_FUNCTION(edp2_lcd), + MSM_PIN_FUNCTION(edp3_hot), + MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(emac0_mcg0), + MSM_PIN_FUNCTION(emac0_mcg1), + MSM_PIN_FUNCTION(emac0_mcg2), + MSM_PIN_FUNCTION(emac0_mcg3), + MSM_PIN_FUNCTION(emac0_mdc), + MSM_PIN_FUNCTION(emac0_mdio), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_mcg0), + MSM_PIN_FUNCTION(emac1_mcg1), + MSM_PIN_FUNCTION(emac1_mcg2), + MSM_PIN_FUNCTION(emac1_mcg3), + MSM_PIN_FUNCTION(emac1_mdc), + MSM_PIN_FUNCTION(emac1_mdio), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(gcc_gp4_clk), + MSM_PIN_FUNCTION(gcc_gp5_clk), + MSM_PIN_FUNCTION(gcc_gp6_clk), + MSM_PIN_FUNCTION(gcc_gp7_clk), + MSM_PIN_FUNCTION(gcc_gp8_clk), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lbist_pass), + MSM_PIN_FUNCTION(mbist_pass), + MSM_PIN_FUNCTION(mdp0_vsync0_out), + MSM_PIN_FUNCTION(mdp0_vsync10_out), + MSM_PIN_FUNCTION(mdp0_vsync1_out), + MSM_PIN_FUNCTION(mdp0_vsync2_out), + MSM_PIN_FUNCTION(mdp0_vsync3_out), + MSM_PIN_FUNCTION(mdp0_vsync4_out), + MSM_PIN_FUNCTION(mdp0_vsync5_out), + MSM_PIN_FUNCTION(mdp0_vsync6_out), + MSM_PIN_FUNCTION(mdp0_vsync7_out), + MSM_PIN_FUNCTION(mdp0_vsync8_out), + MSM_PIN_FUNCTION(mdp0_vsync9_out), + MSM_PIN_FUNCTION(mdp1_vsync0_out), + MSM_PIN_FUNCTION(mdp1_vsync10_out), + MSM_PIN_FUNCTION(mdp1_vsync1_out), + MSM_PIN_FUNCTION(mdp1_vsync2_out), + MSM_PIN_FUNCTION(mdp1_vsync3_out), + MSM_PIN_FUNCTION(mdp1_vsync4_out), + MSM_PIN_FUNCTION(mdp1_vsync5_out), + MSM_PIN_FUNCTION(mdp1_vsync6_out), + MSM_PIN_FUNCTION(mdp1_vsync7_out), + MSM_PIN_FUNCTION(mdp1_vsync8_out), + MSM_PIN_FUNCTION(mdp1_vsync9_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(phase_flag0), + MSM_PIN_FUNCTION(phase_flag1), + MSM_PIN_FUNCTION(phase_flag10), + MSM_PIN_FUNCTION(phase_flag11), + MSM_PIN_FUNCTION(phase_flag12), + MSM_PIN_FUNCTION(phase_flag13), + MSM_PIN_FUNCTION(phase_flag14), + MSM_PIN_FUNCTION(phase_flag15), + MSM_PIN_FUNCTION(phase_flag16), + MSM_PIN_FUNCTION(phase_flag17), + MSM_PIN_FUNCTION(phase_flag18), + MSM_PIN_FUNCTION(phase_flag19), + MSM_PIN_FUNCTION(phase_flag2), + MSM_PIN_FUNCTION(phase_flag20), + MSM_PIN_FUNCTION(phase_flag21), + MSM_PIN_FUNCTION(phase_flag22), + MSM_PIN_FUNCTION(phase_flag23), + MSM_PIN_FUNCTION(phase_flag24), + MSM_PIN_FUNCTION(phase_flag25), + MSM_PIN_FUNCTION(phase_flag26), + MSM_PIN_FUNCTION(phase_flag27), + MSM_PIN_FUNCTION(phase_flag28), + MSM_PIN_FUNCTION(phase_flag29), + MSM_PIN_FUNCTION(phase_flag3), + MSM_PIN_FUNCTION(phase_flag30), + MSM_PIN_FUNCTION(phase_flag31), + MSM_PIN_FUNCTION(phase_flag4), + MSM_PIN_FUNCTION(phase_flag5), + MSM_PIN_FUNCTION(phase_flag6), + MSM_PIN_FUNCTION(phase_flag7), + MSM_PIN_FUNCTION(phase_flag8), + MSM_PIN_FUNCTION(phase_flag9), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(pwrbrk_i_n), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qdss_gpio0), + MSM_PIN_FUNCTION(qdss_gpio1), + MSM_PIN_FUNCTION(qdss_gpio10), + MSM_PIN_FUNCTION(qdss_gpio11), + MSM_PIN_FUNCTION(qdss_gpio12), + MSM_PIN_FUNCTION(qdss_gpio13), + MSM_PIN_FUNCTION(qdss_gpio14), + MSM_PIN_FUNCTION(qdss_gpio15), + MSM_PIN_FUNCTION(qdss_gpio2), + MSM_PIN_FUNCTION(qdss_gpio3), + MSM_PIN_FUNCTION(qdss_gpio4), + MSM_PIN_FUNCTION(qdss_gpio5), + MSM_PIN_FUNCTION(qdss_gpio6), + MSM_PIN_FUNCTION(qdss_gpio7), + MSM_PIN_FUNCTION(qdss_gpio8), + MSM_PIN_FUNCTION(qdss_gpio9), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs0_n), + MSM_PIN_FUNCTION(qspi_cs1_n), + MSM_PIN_FUNCTION(qup0_se0_l0), + MSM_PIN_FUNCTION(qup0_se0_l1), + MSM_PIN_FUNCTION(qup0_se0_l2), + MSM_PIN_FUNCTION(qup0_se0_l3), + MSM_PIN_FUNCTION(qup0_se1_l0), + MSM_PIN_FUNCTION(qup0_se1_l1), + MSM_PIN_FUNCTION(qup0_se1_l2), + MSM_PIN_FUNCTION(qup0_se1_l3), + MSM_PIN_FUNCTION(qup0_se2_l0), + MSM_PIN_FUNCTION(qup0_se2_l1), + MSM_PIN_FUNCTION(qup0_se2_l2), + MSM_PIN_FUNCTION(qup0_se2_l3), + MSM_PIN_FUNCTION(qup0_se3_l0), + MSM_PIN_FUNCTION(qup0_se3_l1), + MSM_PIN_FUNCTION(qup0_se3_l2), + MSM_PIN_FUNCTION(qup0_se3_l3), + MSM_PIN_FUNCTION(qup0_se4_l0), + MSM_PIN_FUNCTION(qup0_se4_l1), + MSM_PIN_FUNCTION(qup0_se4_l2), + MSM_PIN_FUNCTION(qup0_se4_l3), + MSM_PIN_FUNCTION(qup0_se5_l0), + MSM_PIN_FUNCTION(qup0_se5_l1), + MSM_PIN_FUNCTION(qup0_se5_l2), + MSM_PIN_FUNCTION(qup0_se5_l3), + MSM_PIN_FUNCTION(qup1_se0_l0), + MSM_PIN_FUNCTION(qup1_se0_l1), + MSM_PIN_FUNCTION(qup1_se0_l2), + MSM_PIN_FUNCTION(qup1_se0_l3), + MSM_PIN_FUNCTION(qup1_se1_l0), + MSM_PIN_FUNCTION(qup1_se1_l1), + MSM_PIN_FUNCTION(qup1_se1_l2), + MSM_PIN_FUNCTION(qup1_se1_l3), + MSM_PIN_FUNCTION(qup1_se2_l0), + MSM_PIN_FUNCTION(qup1_se2_l1), + MSM_PIN_FUNCTION(qup1_se2_l2), + MSM_PIN_FUNCTION(qup1_se2_l3), + MSM_PIN_FUNCTION(qup1_se3_l0), + MSM_PIN_FUNCTION(qup1_se3_l1), + MSM_PIN_FUNCTION(qup1_se3_l2), + MSM_PIN_FUNCTION(qup1_se3_l3), + MSM_PIN_FUNCTION(qup1_se4_l0), + MSM_PIN_FUNCTION(qup1_se4_l1), + MSM_PIN_FUNCTION(qup1_se4_l2), + MSM_PIN_FUNCTION(qup1_se4_l3), + MSM_PIN_FUNCTION(qup1_se5_l0), + MSM_PIN_FUNCTION(qup1_se5_l1), + MSM_PIN_FUNCTION(qup1_se5_l2), + MSM_PIN_FUNCTION(qup1_se5_l3), + MSM_PIN_FUNCTION(qup1_se6_l0), + MSM_PIN_FUNCTION(qup1_se6_l1), + MSM_PIN_FUNCTION(qup1_se6_l2), + MSM_PIN_FUNCTION(qup1_se6_l3), + MSM_PIN_FUNCTION(qup2_se0_l0), + MSM_PIN_FUNCTION(qup2_se0_l1), + MSM_PIN_FUNCTION(qup2_se0_l2), + MSM_PIN_FUNCTION(qup2_se0_l3), + MSM_PIN_FUNCTION(qup2_se1_l0), + MSM_PIN_FUNCTION(qup2_se1_l1), + MSM_PIN_FUNCTION(qup2_se1_l2), + MSM_PIN_FUNCTION(qup2_se1_l3), + MSM_PIN_FUNCTION(qup2_se2_l0), + MSM_PIN_FUNCTION(qup2_se2_l1), + MSM_PIN_FUNCTION(qup2_se2_l2), + MSM_PIN_FUNCTION(qup2_se2_l3), + MSM_PIN_FUNCTION(qup2_se2_l4), + MSM_PIN_FUNCTION(qup2_se3_l0), + MSM_PIN_FUNCTION(qup2_se3_l1), + MSM_PIN_FUNCTION(qup2_se3_l2), + MSM_PIN_FUNCTION(qup2_se3_l3), + MSM_PIN_FUNCTION(qup2_se4_l0), + MSM_PIN_FUNCTION(qup2_se4_l1), + MSM_PIN_FUNCTION(qup2_se4_l2), + MSM_PIN_FUNCTION(qup2_se4_l3), + MSM_PIN_FUNCTION(qup2_se4_l4), + MSM_PIN_FUNCTION(qup2_se4_l5), + MSM_PIN_FUNCTION(qup2_se4_l6), + MSM_PIN_FUNCTION(qup2_se5_l0), + MSM_PIN_FUNCTION(qup2_se5_l1), + MSM_PIN_FUNCTION(qup2_se5_l2), + MSM_PIN_FUNCTION(qup2_se5_l3), + MSM_PIN_FUNCTION(qup2_se6_l0), + MSM_PIN_FUNCTION(qup2_se6_l1), + MSM_PIN_FUNCTION(qup2_se6_l2), + MSM_PIN_FUNCTION(qup2_se6_l3), + MSM_PIN_FUNCTION(qup3_se0_l0_mira), + MSM_PIN_FUNCTION(qup3_se0_l0_mirb), + MSM_PIN_FUNCTION(qup3_se0_l1_mira), + MSM_PIN_FUNCTION(qup3_se0_l1_mirb), + MSM_PIN_FUNCTION(qup3_se0_l2), + MSM_PIN_FUNCTION(qup3_se0_l3), + MSM_PIN_FUNCTION(qup3_se0_l4), + MSM_PIN_FUNCTION(qup3_se0_l5), + MSM_PIN_FUNCTION(qup3_se0_l6), + MSM_PIN_FUNCTION(sailss_ospi), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(smb_alert), + MSM_PIN_FUNCTION(smb_alert_n), + MSM_PIN_FUNCTION(smb_clk), + MSM_PIN_FUNCTION(smb_dat), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tsc_timer0), + MSM_PIN_FUNCTION(tsc_timer1), + MSM_PIN_FUNCTION(tsc_timer2), + MSM_PIN_FUNCTION(tsc_timer3), + MSM_PIN_FUNCTION(tsc_timer4), + MSM_PIN_FUNCTION(tsc_timer5), + MSM_PIN_FUNCTION(tsc_timer6), + MSM_PIN_FUNCTION(tsc_timer7), + MSM_PIN_FUNCTION(tsc_timer8), + MSM_PIN_FUNCTION(tsc_timer9), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(tsense_pwm5), + MSM_PIN_FUNCTION(tsense_pwm6), + MSM_PIN_FUNCTION(tsense_pwm7), + MSM_PIN_FUNCTION(tsense_pwm8), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb1_phy_ps), + MSM_PIN_FUNCTION(usb2_hs), + MSM_PIN_FUNCTION(usxgmii0_phy), + MSM_PIN_FUNCTION(usxgmii1_phy), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* Every pin is maintained as a single group, and missing or non-existing = pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup nord_groups[] =3D { + [0] =3D PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _), + [1] =3D PINGROUP(1, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [2] =3D PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _), + [3] =3D PINGROUP(3, _, _, _, _, _, _, _, _, _, _, _), + [4] =3D PINGROUP(4, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [5] =3D PINGROUP(5, _, _, _, _, _, _, _, _, _, _, _), + [6] =3D PINGROUP(6, _, _, _, _, _, _, _, _, _, _, _), + [7] =3D PINGROUP(7, pcie2_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [8] =3D PINGROUP(8, _, _, _, _, _, _, _, _, _, _, _), + [9] =3D PINGROUP(9, _, _, _, _, _, _, _, _, _, _, _), + [10] =3D PINGROUP(10, pcie3_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [11] =3D PINGROUP(11, _, _, _, _, _, _, _, _, _, _, _), + [12] =3D PINGROUP(12, usb0_hs, clink_debug, _, _, _, _, _, _, _, _, _), + [13] =3D PINGROUP(13, usb1_hs, clink_debug, gcc_gp7_clk, _, _, _, _, _, _= , _, _), + [14] =3D PINGROUP(14, usb2_hs, clink_debug, gcc_gp8_clk, _, _, _, _, _, _= , _, _), + [15] =3D PINGROUP(15, ccu_i2c_sda0, _, _, _, _, _, _, _, _, _, _), + [16] =3D PINGROUP(16, ccu_i2c_scl0, emac0_mcg0, _, _, _, _, _, _, _, _, _= ), + [17] =3D PINGROUP(17, ccu_i2c_sda1, emac0_mcg1, _, _, _, _, _, _, _, _, _= ), + [18] =3D PINGROUP(18, ccu_i2c_scl1, emac0_mcg2, _, _, _, _, _, _, _, _, _= ), + [19] =3D PINGROUP(19, ccu_i2c_sda2, emac0_mcg3, _, _, _, _, _, _, _, _, _= ), + [20] =3D PINGROUP(20, ccu_i2c_scl2, emac1_mcg0, _, _, _, _, _, _, _, _, _= ), + [21] =3D PINGROUP(21, ccu_i2c_sda3, emac1_mcg1, _, _, _, _, _, _, _, _, _= ), + [22] =3D PINGROUP(22, ccu_i2c_scl3, emac1_mcg2, _, _, _, _, _, _, _, _, _= ), + [23] =3D PINGROUP(23, ccu_i2c_sda4, emac1_mcg3, _, _, _, _, _, _, _, _, _= ), + [24] =3D PINGROUP(24, ccu_i2c_scl4, _, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, ccu_timer0, tsc_timer0, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, ccu_timer1, tsc_timer1, _, _, _, _, _, _, _, _, _), + [27] =3D PINGROUP(27, ccu_timer2, tsc_timer2, _, _, _, _, _, _, _, _, _), + [28] =3D PINGROUP(28, ccu_timer3, tsc_timer3, _, _, _, _, _, _, _, _, _), + [29] =3D PINGROUP(29, ccu_timer4, tsc_timer4, _, _, _, _, _, _, _, _, _), + [30] =3D PINGROUP(30, ccu_timer5, tsc_timer5, _, _, _, _, _, _, _, _, _), + [31] =3D PINGROUP(31, ccu_timer6, tsc_timer6, _, _, _, _, _, _, _, _, _), + [32] =3D PINGROUP(32, ccu_timer7, tsc_timer7, _, _, _, _, _, _, _, _, _), + [33] =3D PINGROUP(33, ccu_timer8, tsc_timer8, _, _, _, _, _, _, _, _, _), + [34] =3D PINGROUP(34, ccu_timer9, tsc_timer9, _, _, _, _, _, _, _, _, _), + [35] =3D PINGROUP(35, dp_rx0_mute, _, _, _, _, _, _, _, _, _, _), + [36] =3D PINGROUP(36, dp_rx1_mute, ddr_bist_start, _, _, _, _, _, _, _, _= , _), + [37] =3D PINGROUP(37, emac1_ptp, ddr_bist_complete, _, _, _, _, _, _, _, = _, _), + [38] =3D PINGROUP(38, emac1_ptp, ddr_bist_stop, _, _, _, _, _, _, _, _, _= ), + [39] =3D PINGROUP(39, emac1_ptp, ddr_bist_fail, _, _, _, _, _, _, _, _, _= ), + [40] =3D PINGROUP(40, emac1_ptp, _, _, _, _, _, _, _, _, _, _), + [41] =3D PINGROUP(41, emac1_ptp, qdss_cti, _, _, _, _, _, _, _, _, _), + [42] =3D PINGROUP(42, emac1_ptp, qdss_cti, gcc_gp3_clk, _, _, _, _, _, _,= _, _), + [43] =3D PINGROUP(43, emac1_ptp, gcc_gp4_clk, tsense_pwm1, _, _, _, _, _,= _, _, _), + [44] =3D PINGROUP(44, emac1_ptp, tsense_pwm2, _, _, _, _, _, _, _, _, _), + [45] =3D PINGROUP(45, usxgmii0_phy, ccu_async_in5, tsense_pwm3, _, _, _, = _, _, _, _, _), + [46] =3D PINGROUP(46, usxgmii1_phy, tsense_pwm4, _, _, _, _, _, _, _, _, = _), + [47] =3D PINGROUP(47, emac0_mdc, edp0_lcd, tsense_pwm5, _, _, _, _, _, _,= _, _), + [48] =3D PINGROUP(48, emac0_mdio, edp1_lcd, tsense_pwm6, _, _, _, _, _, _= , _, _), + [49] =3D PINGROUP(49, emac1_mdc, edp2_lcd, tsense_pwm7, _, _, _, _, _, _,= _, _), + [50] =3D PINGROUP(50, emac1_mdio, edp3_lcd, tsense_pwm8, _, _, _, _, _, _= , _, _), + [51] =3D PINGROUP(51, edp0_hot, clink_debug, gcc_gp1_clk, _, _, _, _, _, = _, _, _), + [52] =3D PINGROUP(52, edp1_hot, clink_debug, gcc_gp2_clk, _, _, _, _, _, = _, _, _), + [53] =3D PINGROUP(53, edp2_hot, clink_debug, _, _, _, _, _, _, _, _, _), + [54] =3D PINGROUP(54, edp3_hot, clink_debug, _, _, _, _, _, _, _, _, _), + [55] =3D PINGROUP(55, dp_rx0, clink_debug, _, _, _, _, _, _, _, _, _), + [56] =3D PINGROUP(56, dp_rx1, _, _, _, _, _, _, _, _, _, _), + [57] =3D PINGROUP(57, aud_intfc0_clk, _, _, _, _, _, _, _, _, _, _), + [58] =3D PINGROUP(58, aud_intfc0_ws, _, _, _, _, _, _, _, _, _, _), + [59] =3D PINGROUP(59, aud_intfc0_data0, _, _, _, _, _, _, _, _, _, _), + [60] =3D PINGROUP(60, aud_intfc0_data1, _, _, _, _, _, _, _, _, _, _), + [61] =3D PINGROUP(61, aud_intfc0_data2, aud_intfc10_clk, _, _, _, _, _, _= , _, _, _), + [62] =3D PINGROUP(62, aud_intfc0_data3, aud_intfc10_ws, _, _, _, _, _, _,= _, _, _), + [63] =3D PINGROUP(63, aud_intfc0_data4, aud_intfc7_clk, _, _, _, _, _, _,= _, _, _), + [64] =3D PINGROUP(64, aud_intfc0_data5, aud_intfc7_ws, _, _, _, _, _, _, = _, _, _), + [65] =3D PINGROUP(65, aud_intfc0_data6, aud_intfc7_data0, _, _, _, _, _, = _, _, _, _), + [66] =3D PINGROUP(66, aud_intfc0_data7, aud_intfc7_data1, _, _, _, _, _, = _, _, _, _), + [67] =3D PINGROUP(67, aud_intfc1_clk, phase_flag18, _, qdss_gpio0, _, _, = _, _, _, _, _), + [68] =3D PINGROUP(68, aud_intfc1_ws, phase_flag19, _, qdss_gpio1, _, _, _= , _, _, _, _), + [69] =3D PINGROUP(69, aud_intfc1_data0, phase_flag20, _, qdss_gpio2, _, _= , _, _, _, _, _), + [70] =3D PINGROUP(70, aud_intfc1_data1, aud_intfc9_clk, phase_flag21, _, = qdss_gpio3, + _, _, _, _, _, _), + [71] =3D PINGROUP(71, aud_intfc1_data2, aud_intfc9_ws, phase_flag22, _, q= dss_gpio4, _, _, + _, _, _, _), + [72] =3D PINGROUP(72, aud_intfc1_data3, aud_intfc9_data0, phase_flag23, _= , qdss_gpio5, _, + _, _, _, _, _), + [73] =3D PINGROUP(73, aud_intfc1_data4, aud_intfc8_clk, phase_flag24, _, = qdss_gpio6, _, + _, _, _, _, _), + [74] =3D PINGROUP(74, aud_intfc1_data5, aud_intfc8_ws, phase_flag25, _, q= dss_gpio7, _, + _, _, _, _, _), + [75] =3D PINGROUP(75, aud_intfc1_data6, aud_intfc8_data0, phase_flag26, _= , qdss_gpio, + _, _, _, _, _, _), + [76] =3D PINGROUP(76, aud_intfc1_data7, aud_intfc8_data1, phase_flag27, _= , qdss_gpio, + _, _, _, _, _, _), + [77] =3D PINGROUP(77, aud_intfc2_clk, phase_flag6, _, qdss_gpio8, _, _, _= , _, _, _, _), + [78] =3D PINGROUP(78, aud_intfc2_ws, phase_flag5, _, qdss_gpio9, _, _, _,= _, _, _, _), + [79] =3D PINGROUP(79, aud_intfc2_data0, phase_flag4, _, qdss_gpio10, _, _= , _, _, _, _, _), + [80] =3D PINGROUP(80, aud_intfc2_data1, phase_flag3, _, _, qdss_gpio11, _= , _, _, _, _, _), + [81] =3D PINGROUP(81, aud_intfc2_data2, aud_intfc10_data0, phase_flag2, _= , _, qdss_gpio12, + _, _, _, _, _), + [82] =3D PINGROUP(82, aud_intfc2_data3, aud_intfc10_data1, phase_flag1, _= , qdss_gpio13, + _, _, _, _, _, _), + [83] =3D PINGROUP(83, aud_intfc3_clk, dp_rx0, aoss_cti, phase_flag28, _, = qdss_gpio14, + _, _, _, _, _), + [84] =3D PINGROUP(84, aud_intfc3_ws, dp_rx0, aoss_cti, phase_flag29, _, q= dss_gpio15, + _, _, _, _, _), + [85] =3D PINGROUP(85, aud_intfc3_data0, dp_rx0, aoss_cti, phase_flag30, _= , qdss_gpio0, + _, _, _, _, _), + [86] =3D PINGROUP(86, aud_intfc3_data1, aud_mclk0_mirb, dp_rx0, aoss_cti,= phase_flag31, + _, qdss_gpio1, _, _, _, _), + [87] =3D PINGROUP(87, aud_intfc4_clk, phase_flag7, _, qdss_gpio2, _, _, _= , _, _, _, _), + [88] =3D PINGROUP(88, aud_intfc4_ws, dp_rx0, phase_flag8, _, qdss_gpio3, = _, _, _, _, _, _), + [89] =3D PINGROUP(89, aud_intfc4_data0, dp_rx0, phase_flag9, _, qdss_gpio= 4, + _, _, _, _, _, _), + [90] =3D PINGROUP(90, aud_intfc4_data1, aud_mclk1_mirb, phase_flag10, _, = qdss_gpio5, + _, _, _, _, _, _), + [91] =3D PINGROUP(91, aud_intfc5_clk, phase_flag11, _, qdss_gpio6, _, _, = _, _, _, _, _), + [92] =3D PINGROUP(92, aud_intfc5_ws, dp_rx1, phase_flag12, _, qdss_gpio7,= _, _, _, _, _, _), + [93] =3D PINGROUP(93, aud_intfc5_data0, dp_rx1, phase_flag13, _, qdss_gpi= o, + _, _, _, _, _, _), + [94] =3D PINGROUP(94, aud_intfc5_data1, aud_mclk2_mirb, phase_flag14, tme= ss_prng0, _, + qdss_gpio8, _, _, _, _, _), + [95] =3D PINGROUP(95, aud_intfc6_clk, dp_rx1, phase_flag15, tmess_prng1, = _, qdss_gpio9, + _, _, _, _, _), + [96] =3D PINGROUP(96, aud_intfc6_ws, dp_rx1, phase_flag16, _, qdss_gpio10= , _, _, _, _, _, _), + [97] =3D PINGROUP(97, aud_intfc6_data0, dp_rx1, qdss_gpio11, _, _, _, _, = _, _, _, _), + [98] =3D PINGROUP(98, aud_intfc6_data1, dp_rx1, phase_flag0, _, qdss_gpio= 12, + _, _, _, _, _, _), + [99] =3D PINGROUP(99, aud_mclk0_mira, qdss_gpio13, dp_rx00, ddr_pxi0, _, = _, _, _, _, _, _), + [100] =3D PINGROUP(100, aud_mclk1_mira, aud_refclk0, pll_clk_aux, qdss_gp= io14, dp_rx01, + ddr_pxi0, _, _, _, _, _), + [101] =3D PINGROUP(101, aud_mclk2_mira, aud_refclk1, phase_flag17, _, qds= s_gpio15, + _, _, _, _, _, _), + [102] =3D PINGROUP(102, qspi0, qup3_se0_l0_mira, qup3_se0_l1_mirb, _, _, = _, _, _, _, _, _), + [103] =3D PINGROUP(103, qspi1, qup3_se0_l1_mira, qup3_se0_l0_mirb, _, _, = _, _, _, _, _, _), + [104] =3D PINGROUP(104, qspi_clk, qup3_se0_l2, _, _, _, _, _, _, _, _, _), + [105] =3D PINGROUP(105, qspi_cs0_n, qup3_se0_l3, gcc_gp5_clk, _, _, _, _,= _, _, _, _), + [106] =3D PINGROUP(106, qspi2, qup3_se0_l4, gcc_gp6_clk, _, _, _, _, _, _= , _, _), + [107] =3D PINGROUP(107, qspi3, qup3_se0_l5, _, _, _, _, _, _, _, _, _), + [108] =3D PINGROUP(108, qspi_cs1_n, qup3_se0_l6, qdss_gpio, _, _, _, _, _= , _, _, _), + [109] =3D PINGROUP(109, qup0_se0_l2, qup0_se1_l2, qup0_se5_l2, mdp_vsync_= e, smb_alert_n, + _, ddr_pxi1, _, _, _, _), + [110] =3D PINGROUP(110, qup0_se0_l3, qup0_se1_l3, qup0_se5_l3, qdss_cti, = mdp_vsync_p, + smb_alert, _, ddr_pxi1, _, _, _), + [111] =3D PINGROUP(111, qup0_se1_l0, qup0_se0_l0, smb_dat, _, _, _, _, _,= _, _, _), + [112] =3D PINGROUP(112, qup0_se1_l1, qup0_se0_l1, smb_clk, _, _, _, _, _,= _, _, _), + [113] =3D PINGROUP(113, qup0_se2_l0, qup0_se3_l2, ccu_i2c_sda5, mdp0_vsyn= c0_out, + dbg_out, ddr_pxi2, _, _, _, _, _), + [114] =3D PINGROUP(114, qup0_se2_l1, qup0_se3_l3, ccu_i2c_scl5, mdp0_vsyn= c1_out, + _, ddr_pxi2, _, _, _, _, _), + [115] =3D PINGROUP(115, qup0_se3_l0, qup0_se2_l2, ccu_i2c_sda6, mdp0_vsyn= c2_out, + _, ddr_pxi3, _, _, _, _, _), + [116] =3D PINGROUP(116, qup0_se3_l1, qup0_se2_l3, ccu_i2c_scl6, mdp0_vsyn= c3_out, _, + ddr_pxi3, _, _, _, _, _), + [117] =3D PINGROUP(117, qup0_se4_l0, prng_rosc0, _, ddr_pxi4, _, _, _, _,= _, _, _), + [118] =3D PINGROUP(118, qup0_se4_l1, prng_rosc1, _, ddr_pxi4, _, _, _, _,= _, _, _), + [119] =3D PINGROUP(119, qup0_se4_l2, _, ddr_pxi6, _, _, _, _, _, _, _, _), + [120] =3D PINGROUP(120, qup0_se4_l3, _, ddr_pxi6, _, _, _, _, _, _, _, _), + [121] =3D PINGROUP(121, qup0_se5_l0, lbist_pass, mdp0_vsync4_out, _, dp_r= x10, ddr_pxi7, + _, _, _, _, _), + [122] =3D PINGROUP(122, qup0_se5_l1, mbist_pass, mdp0_vsync5_out, _, dp_r= x11, ddr_pxi7, + _, _, _, _, _), + [123] =3D PINGROUP(123, qup1_se0_l0, qup1_se1_l2, mdp1_vsync0_out, jitter= _bist, + _, _, _, _, _, _, _), + [124] =3D PINGROUP(124, qup1_se0_l1, qup1_se1_l3, mdp1_vsync1_out, _, _, = _, _, _, _, _, _), + [125] =3D PINGROUP(125, qup1_se1_l0, qup1_se0_l2, ccu_i2c_sda7, mdp1_vsyn= c2_out, + _, _, _, _, _, _, _), + [126] =3D PINGROUP(126, qup1_se1_l1, qup1_se0_l3, ccu_i2c_scl7, mdp1_vsyn= c3_out, _, + atest_usb20, ddr_pxi8, _, _, _, _), + [127] =3D PINGROUP(127, qup1_se2_l2, qup1_se2_l0, _, atest_usb21, ddr_pxi= 8, + _, _, _, _, _, _), + [128] =3D PINGROUP(128, qup1_se2_l3, qup1_se2_l1, _, atest_usb20, ddr_pxi= 9, + _, _, _, _, _, _), + [129] =3D PINGROUP(129, qup1_se3_l2, qup1_se3_l0, ccu_i2c_sda8, mdp1_vsyn= c4_out, _, + atest_usb21, ddr_pxi9, _, _, _, _), + [130] =3D PINGROUP(130, qup1_se3_l3, qup1_se3_l1, ccu_i2c_scl8, mdp1_vsyn= c5_out, _, + atest_usb20, ddr_pxi10, _, _, _, _), + [131] =3D PINGROUP(131, qup1_se4_l0, qup1_se6_l2, ccu_i2c_sda9, mdp1_vsyn= c6_out, _, + atest_usb21, ddr_pxi10, _, _, _, _), + [132] =3D PINGROUP(132, qup1_se4_l1, qup1_se6_l3, ccu_i2c_scl9, mdp1_vsyn= c7_out, _, + vsense_trigger_mirnat, ddr_pxi11, _, _, _, _), + [133] =3D PINGROUP(133, qup1_se5_l0, emac0_ptp, mdp1_vsync8_out, _, ddr_p= xi11, + _, _, _, _, _, _), + [134] =3D PINGROUP(134, qup1_se5_l1, emac0_ptp, mdp1_vsync9_out, _, ddr_p= xi12, + _, _, _, _, _, _), + [135] =3D PINGROUP(135, qup1_se5_l2, emac0_ptp, mdp1_vsync10_out, _, ddr_= pxi12, + _, _, _, _, _, _), + [136] =3D PINGROUP(136, qup1_se5_l3, emac0_ptp, _, ddr_pxi13, _, _, _, _,= _, _, _), + [137] =3D PINGROUP(137, qup1_se6_l0, qup1_se4_l2, dp_rx0, _, ddr_pxi13, _= , _, _, _, _, _), + [138] =3D PINGROUP(138, qup1_se6_l1, qup1_se4_l3, dp_rx0, qdss_cti, jitte= r_bist, + ddr_pxi14, _, _, _, _, _), + [139] =3D PINGROUP(139, qup2_se0_l0, emac0_ptp, mdp0_vsync6_out, ddr_pxi1= 4, + _, _, _, _, _, _, _), + [140] =3D PINGROUP(140, qup2_se0_l1, emac0_ptp, mdp0_vsync7_out, _, _, _,= _, _, _, _, _), + [141] =3D PINGROUP(141, qup2_se0_l2, emac0_ptp, mdp0_vsync8_out, _, _, _,= _, _, _, _, _), + [142] =3D PINGROUP(142, qup2_se0_l3, emac0_ptp, qdss_cti, mdp0_vsync9_out, + _, _, _, _, _, _, _), + [143] =3D PINGROUP(143, qup2_se1_l2, qup2_se4_l2, ccu_timer10, mdp0_vsync= 10_out, + _, _, _, _, _, _, _), + [144] =3D PINGROUP(144, qup2_se1_l3, qup2_se4_l3, ccu_timer11, qdss_cti, = mdp_vsync_s, + _, _, _, _, _, _), + [145] =3D PINGROUP(145, qup2_se2_l0, _, _, _, _, _, _, _, _, _, _), + [146] =3D PINGROUP(146, qup2_se2_l1, _, _, _, _, _, _, _, _, _, _), + [147] =3D PINGROUP(147, qup2_se2_l2, _, _, _, _, _, _, _, _, _, _), + [148] =3D PINGROUP(148, qup2_se2_l3, _, _, _, _, _, _, _, _, _, _), + [149] =3D PINGROUP(149, qup2_se2_l4, _, _, _, _, _, _, _, _, _, _), + [150] =3D PINGROUP(150, qup2_se3_l0, qup2_se4_l4, ccu_timer12, _, _, _, _= , _, _, _, _), + [151] =3D PINGROUP(151, qup2_se3_l1, qup2_se4_l5, ccu_timer13, _, _, _, _= , _, _, _, _), + [152] =3D PINGROUP(152, qup2_se3_l2, qup2_se4_l6, ccu_timer14, _, _, _, _= , _, _, _, _), + [153] =3D PINGROUP(153, qup2_se3_l3, ccu_timer15, _, _, _, _, _, _, _, _,= _), + [154] =3D PINGROUP(154, qup2_se4_l0, qup2_se1_l0, _, _, _, _, _, _, _, _,= _), + [155] =3D PINGROUP(155, qup2_se4_l1, qup2_se1_l1, _, _, _, _, _, _, _, _,= _), + [156] =3D PINGROUP(156, qup2_se5_l0, qup2_se6_l2, _, _, _, _, _, _, _, _,= _), + [157] =3D PINGROUP(157, qup2_se5_l1, qup2_se6_l3, _, _, _, _, _, _, _, _,= _), + [158] =3D PINGROUP(158, qup2_se6_l0, qup2_se5_l2, dp_rx1, _, _, _, _, _, = _, _, _), + [159] =3D PINGROUP(159, qup2_se6_l1, qup2_se5_l3, dp_rx1, _, _, _, _, _, = _, _, _), + [160] =3D PINGROUP(160, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [161] =3D PINGROUP(161, wcn_sw, _, _, _, _, _, _, _, _, _, _), + [162] =3D PINGROUP(162, qdss_cti, _, ddr_pxi15, _, _, _, _, _, _, _, _), + [163] =3D PINGROUP(163, qdss_cti, _, ddr_pxi15, _, _, _, _, _, _, _, _), + [164] =3D PINGROUP(164, usb0_phy_ps, _, sailss_ospi, ddr_pxi5, _, _, _, _= , _, _, _), + [165] =3D PINGROUP(165, usb1_phy_ps, dbg_out_clk, sailss_ospi, ddr_pxi5, + _, _, _, _, _, _, _), + [166] =3D PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _), + [167] =3D PINGROUP(167, pwrbrk_i_n, _, _, _, _, _, _, _, _, _, _), + [168] =3D PINGROUP(168, bist_done, _, _, _, _, _, _, _, _, _, _), + [169] =3D PINGROUP(169, tb_trig_sdc4, _, _, _, _, _, _, _, _, _, _), + [170] =3D PINGROUP(170, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [171] =3D PINGROUP(171, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [172] =3D PINGROUP(172, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [173] =3D PINGROUP(173, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [174] =3D PINGROUP(174, sdc4_cmd, _, _, _, _, _, _, _, _, _, _), + [175] =3D PINGROUP(175, sdc4_clk, _, _, _, _, _, _, _, _, _, _), + [176] =3D PINGROUP(176, ccu_async_in0, pll_bist_sync, atest_char_start, + _, _, _, _, _, _, _, _), + [177] =3D PINGROUP(177, ccu_async_in1, atest_char0, _, _, _, _, _, _, _, = _, _), + [178] =3D PINGROUP(178, ccu_async_in2, atest_char1, _, _, _, _, _, _, _, = _, _), + [179] =3D PINGROUP(179, ccu_async_in3, atest_char2, _, _, _, _, _, _, _, = _, _), + [180] =3D PINGROUP(180, ccu_async_in4, atest_char3, _, _, _, _, _, _, _, = _, _), + [181] =3D UFS_RESET(ufs_reset, 0xBD004), +}; + +static const struct msm_gpio_wakeirq_map nord_pdc_map[] =3D { + { 0, 67 }, { 1, 68 }, { 2, 82 }, { 3, 69 }, { 4, 70 }, + { 5, 83 }, { 6, 71 }, { 7, 72 }, { 8, 84 }, { 9, 73 }, + { 10, 119 }, { 11, 85 }, { 45, 107 }, { 46, 98 }, { 102, 77 }, + { 108, 78 }, { 110, 120 }, { 114, 80 }, { 116, 81 }, { 120, 117 }, + { 124, 108 }, { 126, 99 }, { 128, 100 }, { 132, 101 }, { 138, 87 }, + { 142, 88 }, { 144, 89 }, { 153, 90 }, { 157, 91 }, { 159, 118 }, + { 160, 110 }, { 161, 79 }, { 166, 109 }, { 168, 111 }, +}; + +static const struct msm_pinctrl_soc_data nord_tlmm =3D { + .pins =3D nord_pins, + .npins =3D ARRAY_SIZE(nord_pins), + .functions =3D nord_functions, + .nfunctions =3D ARRAY_SIZE(nord_functions), + .groups =3D nord_groups, + .ngroups =3D ARRAY_SIZE(nord_groups), + .ngpios =3D 182, + .wakeirq_map =3D nord_pdc_map, + .nwakeirq_map =3D ARRAY_SIZE(nord_pdc_map), + .egpio_func =3D 11, +}; + +static const struct of_device_id nord_tlmm_of_match[] =3D { + { .compatible =3D "qcom,nord-tlmm", .data =3D &nord_tlmm }, + {}, +}; +MODULE_DEVICE_TABLE(of, nord_tlmm_of_match); + +static int nord_tlmm_probe(struct platform_device *pdev) +{ + const struct msm_pinctrl_soc_data *pinctrl_data; + struct device *dev =3D &pdev->dev; + + pinctrl_data =3D device_get_match_data(dev); + if (!pinctrl_data) + return -EINVAL; + + return msm_pinctrl_probe(pdev, &nord_tlmm); +} + +static struct platform_driver nord_tlmm_driver =3D { + .driver =3D { + .name =3D "nord-tlmm", + .of_match_table =3D nord_tlmm_of_match, + }, + .probe =3D nord_tlmm_probe, +}; + +static int __init nord_tlmm_init(void) +{ + return platform_driver_register(&nord_tlmm_driver); +} +arch_initcall(nord_tlmm_init); + +static void __exit nord_tlmm_exit(void) +{ + platform_driver_unregister(&nord_tlmm_driver); +} +module_exit(nord_tlmm_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies Inc. 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Signed-off-by: Bartosz Golaszewski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 163b7f0314c90fc45eb6c4aa5e8faa549c60fdf7..31f8cd7cde6fcc8c8da8e69950d= d4976ae04cfc4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -675,6 +675,7 @@ CONFIG_PINCTRL_QDF2XXX=3Dy CONFIG_PINCTRL_QDU1000=3Dy CONFIG_PINCTRL_RP1=3Dm CONFIG_PINCTRL_SA8775P=3Dy +CONFIG_PINCTRL_NORD=3Dy CONFIG_PINCTRL_SC7180=3Dy CONFIG_PINCTRL_SC7280=3Dy CONFIG_PINCTRL_SC8180X=3Dy --=20 2.47.3