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Signed-off-by: Taniya Das [Shawn: Use compatible qcom,nord-tcsrcc rather than qcom,nord-tcsr] Signed-off-by: Shawn Guo Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 2 ++ include/dt-bindings/clock/qcom,nord-tcsrcc.h | 26 ++++++++++++++++++= ++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index ae9aef0e54e8b8b85bc70e6096d524447091f39e..1ccdf4b0f5dd390417821494cdb= 97d8f4ed26c58 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -17,6 +17,7 @@ description: | See also: - include/dt-bindings/clock/qcom,eliza-tcsr.h - include/dt-bindings/clock/qcom,glymur-tcsr.h + - include/dt-bindings/clock/qcom,nord-tcsrcc.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h - include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -29,6 +30,7 @@ properties: - qcom,glymur-tcsr - qcom,kaanapali-tcsr - qcom,milos-tcsr + - qcom,nord-tcsrcc - qcom,sar2130p-tcsr - qcom,sm8550-tcsr - qcom,sm8650-tcsr diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bind= ings/clock/qcom,nord-tcsrcc.h new file mode 100644 index 0000000000000000000000000000000000000000..3f0e2ff7acc72c10d00488c48ec= 17af8ea6de06e --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H + +/* TCSR_CC clocks */ +#define TCSR_DP_RX_0_CLKREF_EN 0 +#define TCSR_DP_RX_1_CLKREF_EN 1 +#define TCSR_DP_TX_0_CLKREF_EN 2 +#define TCSR_DP_TX_1_CLKREF_EN 3 +#define TCSR_DP_TX_2_CLKREF_EN 4 +#define TCSR_DP_TX_3_CLKREF_EN 5 +#define TCSR_PCIE_CLKREF_EN 6 +#define TCSR_UFS_CLKREF_EN 7 +#define TCSR_USB2_0_CLKREF_EN 8 +#define TCSR_USB2_1_CLKREF_EN 9 +#define TCSR_USB2_2_CLKREF_EN 10 +#define TCSR_USB3_0_CLKREF_EN 11 +#define TCSR_USB3_1_CLKREF_EN 12 +#define TCSR_UX_SGMII_0_CLKREF_EN 13 +#define TCSR_UX_SGMII_1_CLKREF_EN 14 + +#endif --=20 2.47.3 From nobody Tue Apr 7 12:23:28 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46C8827FD5B for ; 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Signed-off-by: Taniya Das Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 9690169baa4697bbd3ab9197f9661368a0827bf7..a2c404a579812dae073241ea71b= 63e55e798e80e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -21,6 +21,7 @@ properties: - qcom,glymur-rpmh-clk - qcom,kaanapali-rpmh-clk - qcom,milos-rpmh-clk + - qcom,nord-rpmh-clk - qcom,qcs615-rpmh-clk - qcom,qdu1000-rpmh-clk - qcom,sa8775p-rpmh-clk --=20 2.47.3 From nobody Tue Apr 7 12:23:28 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F3CD3C454E for ; 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The global clock controller on Nord SoC is divided into multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of the bindings to define the clock controllers. Signed-off-by: Taniya Das Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,nord-gcc.yaml | 58 ++++++++ .../devicetree/bindings/clock/qcom,nord-negcc.yaml | 60 +++++++++ .../devicetree/bindings/clock/qcom,nord-nwgcc.yaml | 55 ++++++++ include/dt-bindings/clock/qcom,nord-gcc.h | 147 +++++++++++++++++= ++++ include/dt-bindings/clock/qcom,nord-negcc.h | 124 +++++++++++++++++ include/dt-bindings/clock/qcom,nord-nwgcc.h | 69 ++++++++++ include/dt-bindings/clock/qcom,nord-segcc.h | 98 ++++++++++++++ 7 files changed, 611 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml b/D= ocumentation/devicetree/bindings/clock/qcom,nord-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e35136722a931ef76f80d36ad2b= c07fe618490d5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Nord SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on Nord SoC. + + See also: include/dt-bindings/clock/qcom,nord-gcc.h + +properties: + compatible: + const: qcom,nord-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE A Pipe clock source + - description: PCIE B Pipe clock source + - description: PCIE C Pipe clock source + - description: PCIE D Pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible =3D "qcom,nord-gcc"; + reg =3D <0x00100000 0x1f4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie_a_pipe_clk>, + <&pcie_b_pipe_clk>, + <&pcie_c_pipe_clk>, + <&pcie_d_pipe_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml b= /Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..749389f65ee14999b3a195256e3= 4f486e9aace1d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global North East Clock & Reset Controller on Nord SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm global clock control (NE) module provides the clocks, resets + and power domains on Nord SoC. + + See also: include/dt-bindings/clock/qcom,nord-negcc.h + +properties: + compatible: + const: qcom,nord-negcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy sec wrapper pipe clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@8900000 { + compatible =3D "qcom,nord-negcc"; + reg =3D <0x08900000 0xf4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_sec_pipe_clk>, + <&usb3_phy_pipe_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml b= /Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ce33f966bdfdf0b0ccebc40944e= 3d961c79c6fe0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global North West and South East Clock & Reset Controller + on Nord SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm global clock control (NW, SE) module provides the clocks, resets + and power domains on Nord SoC. + + See also: + include/dt-bindings/clock/qcom,nord-nwgcc.h + include/dt-bindings/clock/qcom,nord-segcc.h + +properties: + compatible: + enum: + - qcom,nord-nwgcc + - qcom,nord-segcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@8b00000 { + compatible =3D "qcom,nord-nwgcc"; + reg =3D <0x08b00000 0xf4200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-binding= s/clock/qcom,nord-gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..8fbde162c8598d75b42136350fb= 23b33c29c339f --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gcc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H + +/* GCC clocks */ +#define GCC_BOOT_ROM_AHB_CLK 0 +#define GCC_GP1_CLK 1 +#define GCC_GP1_CLK_SRC 2 +#define GCC_GP2_CLK 3 +#define GCC_GP2_CLK_SRC 4 +#define GCC_GPLL0 5 +#define GCC_GPLL0_OUT_EVEN 6 +#define GCC_MMU_0_TCU_VOTE_CLK 7 +#define GCC_PCIE_A_AUX_CLK 8 +#define GCC_PCIE_A_AUX_CLK_SRC 9 +#define GCC_PCIE_A_CFG_AHB_CLK 10 +#define GCC_PCIE_A_DTI_QTC_CLK 11 +#define GCC_PCIE_A_MSTR_AXI_CLK 12 +#define GCC_PCIE_A_PHY_AUX_CLK 13 +#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14 +#define GCC_PCIE_A_PHY_RCHNG_CLK 15 +#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16 +#define GCC_PCIE_A_PIPE_CLK 17 +#define GCC_PCIE_A_PIPE_CLK_SRC 18 +#define GCC_PCIE_A_SLV_AXI_CLK 19 +#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20 +#define GCC_PCIE_B_AUX_CLK 21 +#define GCC_PCIE_B_AUX_CLK_SRC 22 +#define GCC_PCIE_B_CFG_AHB_CLK 23 +#define GCC_PCIE_B_DTI_QTC_CLK 24 +#define GCC_PCIE_B_MSTR_AXI_CLK 25 +#define GCC_PCIE_B_PHY_AUX_CLK 26 +#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27 +#define GCC_PCIE_B_PHY_RCHNG_CLK 28 +#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29 +#define GCC_PCIE_B_PIPE_CLK 30 +#define GCC_PCIE_B_PIPE_CLK_SRC 31 +#define GCC_PCIE_B_SLV_AXI_CLK 32 +#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33 +#define GCC_PCIE_C_AUX_CLK 34 +#define GCC_PCIE_C_AUX_CLK_SRC 35 +#define GCC_PCIE_C_CFG_AHB_CLK 36 +#define GCC_PCIE_C_DTI_QTC_CLK 37 +#define GCC_PCIE_C_MSTR_AXI_CLK 38 +#define GCC_PCIE_C_PHY_AUX_CLK 39 +#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40 +#define GCC_PCIE_C_PHY_RCHNG_CLK 41 +#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_C_PIPE_CLK 43 +#define GCC_PCIE_C_PIPE_CLK_SRC 44 +#define GCC_PCIE_C_SLV_AXI_CLK 45 +#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46 +#define GCC_PCIE_D_AUX_CLK 47 +#define GCC_PCIE_D_AUX_CLK_SRC 48 +#define GCC_PCIE_D_CFG_AHB_CLK 49 +#define GCC_PCIE_D_DTI_QTC_CLK 50 +#define GCC_PCIE_D_MSTR_AXI_CLK 51 +#define GCC_PCIE_D_PHY_AUX_CLK 52 +#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53 +#define GCC_PCIE_D_PHY_RCHNG_CLK 54 +#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55 +#define GCC_PCIE_D_PIPE_CLK 56 +#define GCC_PCIE_D_PIPE_CLK_SRC 57 +#define GCC_PCIE_D_SLV_AXI_CLK 58 +#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59 +#define GCC_PCIE_LINK_AHB_CLK 60 +#define GCC_PCIE_LINK_XO_CLK 61 +#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62 +#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63 +#define GCC_PCIE_NOC_M_CFG_CLK 64 +#define GCC_PCIE_NOC_M_PDB_CLK 65 +#define GCC_PCIE_NOC_MSTR_AXI_CLK 66 +#define GCC_PCIE_NOC_PWRCTL_CLK 67 +#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68 +#define GCC_PCIE_NOC_REFGEN_CLK 69 +#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70 +#define GCC_PCIE_NOC_S_CFG_CLK 71 +#define GCC_PCIE_NOC_S_PDB_CLK 72 +#define GCC_PCIE_NOC_SAFETY_CLK 73 +#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74 +#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75 +#define GCC_PCIE_NOC_TSCTR_CLK 76 +#define GCC_PCIE_NOC_XO_CLK 77 +#define GCC_PDM2_CLK 78 +#define GCC_PDM2_CLK_SRC 79 +#define GCC_PDM_AHB_CLK 80 +#define GCC_PDM_XO4_CLK 81 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82 +#define GCC_QUPV3_WRAP3_CORE_CLK 83 +#define GCC_QUPV3_WRAP3_M_CLK 84 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86 +#define GCC_QUPV3_WRAP3_S0_CLK 87 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88 +#define GCC_QUPV3_WRAP3_S_AHB_CLK 89 +#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90 + +/* GCC power domains */ +#define GCC_PCIE_A_GDSC 0 +#define GCC_PCIE_A_PHY_GDSC 1 +#define GCC_PCIE_B_GDSC 2 +#define GCC_PCIE_B_PHY_GDSC 3 +#define GCC_PCIE_C_GDSC 4 +#define GCC_PCIE_C_PHY_GDSC 5 +#define GCC_PCIE_D_GDSC 6 +#define GCC_PCIE_D_PHY_GDSC 7 +#define GCC_PCIE_NOC_GDSC 8 + +/* GCC resets */ +#define GCC_PCIE_A_BCR 0 +#define GCC_PCIE_A_LINK_DOWN_BCR 1 +#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2 +#define GCC_PCIE_A_PHY_BCR 3 +#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4 +#define GCC_PCIE_A_PHY_COM_BCR 5 +#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_B_BCR 7 +#define GCC_PCIE_B_LINK_DOWN_BCR 8 +#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_B_PHY_BCR 10 +#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11 +#define GCC_PCIE_B_PHY_COM_BCR 12 +#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_C_BCR 14 +#define GCC_PCIE_C_LINK_DOWN_BCR 15 +#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_C_PHY_BCR 17 +#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18 +#define GCC_PCIE_C_PHY_COM_BCR 19 +#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20 +#define GCC_PCIE_D_BCR 21 +#define GCC_PCIE_D_LINK_DOWN_BCR 22 +#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23 +#define GCC_PCIE_D_PHY_BCR 24 +#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25 +#define GCC_PCIE_D_PHY_COM_BCR 26 +#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27 +#define GCC_PCIE_NOC_BCR 28 +#define GCC_PDM_BCR 29 +#define GCC_QUPV3_WRAPPER_3_BCR 30 +#define GCC_TCSR_PCIE_BCR 31 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindi= ngs/clock/qcom,nord-negcc.h new file mode 100644 index 0000000000000000000000000000000000000000..95f333d8e1aa7cf1e386b692638= 0b2c853f7cf43 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-negcc.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H + +/* NE_GCC clocks */ +#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0 +#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1 +#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2 +#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3 +#define NE_GCC_AHB2PHY_CLK 4 +#define NE_GCC_CNOC_USB2_AXI_CLK 5 +#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6 +#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7 +#define NE_GCC_FRQ_MEASURE_REF_CLK 8 +#define NE_GCC_GP1_CLK 9 +#define NE_GCC_GP1_CLK_SRC 10 +#define NE_GCC_GP2_CLK 11 +#define NE_GCC_GP2_CLK_SRC 12 +#define NE_GCC_GPLL0 13 +#define NE_GCC_GPLL0_OUT_EVEN 14 +#define NE_GCC_GPLL2 15 +#define NE_GCC_GPU_2_CFG_CLK 16 +#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17 +#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18 +#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19 +#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20 +#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21 +#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22 +#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23 +#define NE_GCC_QUPV3_WRAP2_S0_CLK 24 +#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25 +#define NE_GCC_QUPV3_WRAP2_S1_CLK 26 +#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27 +#define NE_GCC_QUPV3_WRAP2_S2_CLK 28 +#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29 +#define NE_GCC_QUPV3_WRAP2_S3_CLK 30 +#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31 +#define NE_GCC_QUPV3_WRAP2_S4_CLK 32 +#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33 +#define NE_GCC_QUPV3_WRAP2_S5_CLK 34 +#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35 +#define NE_GCC_QUPV3_WRAP2_S6_CLK 36 +#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37 +#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38 +#define NE_GCC_SDCC4_APPS_CLK 39 +#define NE_GCC_SDCC4_APPS_CLK_SRC 40 +#define NE_GCC_SDCC4_AXI_CLK 41 +#define NE_GCC_UFS_PHY_AHB_CLK 42 +#define NE_GCC_UFS_PHY_AXI_CLK 43 +#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56 +#define NE_GCC_USB20_MASTER_CLK 57 +#define NE_GCC_USB20_MASTER_CLK_SRC 58 +#define NE_GCC_USB20_MOCK_UTMI_CLK 59 +#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60 +#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61 +#define NE_GCC_USB20_SLEEP_CLK 62 +#define NE_GCC_USB31_PRIM_ATB_CLK 63 +#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64 +#define NE_GCC_USB31_PRIM_MASTER_CLK 65 +#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define NE_GCC_USB31_PRIM_SLEEP_CLK 70 +#define NE_GCC_USB31_SEC_ATB_CLK 71 +#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72 +#define NE_GCC_USB31_SEC_MASTER_CLK 73 +#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76 +#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77 +#define NE_GCC_USB31_SEC_SLEEP_CLK 78 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80 +#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85 +#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88 + +/* NE_GCC power domains */ +#define NE_GCC_UFS_MEM_PHY_GDSC 0 +#define NE_GCC_UFS_PHY_GDSC 1 +#define NE_GCC_USB20_PRIM_GDSC 2 +#define NE_GCC_USB31_PRIM_GDSC 3 +#define NE_GCC_USB31_SEC_GDSC 4 +#define NE_GCC_USB3_PHY_GDSC 5 +#define NE_GCC_USB3_SEC_PHY_GDSC 6 + +/* NE_GCC resets */ +#define NE_GCC_GPU_2_BCR 0 +#define NE_GCC_QUPV3_WRAPPER_2_BCR 1 +#define NE_GCC_SDCC4_BCR 2 +#define NE_GCC_UFS_PHY_BCR 3 +#define NE_GCC_USB20_PRIM_BCR 4 +#define NE_GCC_USB31_PRIM_BCR 5 +#define NE_GCC_USB31_SEC_BCR 6 +#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7 +#define NE_GCC_USB3_DP_PHY_SEC_BCR 8 +#define NE_GCC_USB3_PHY_PRIM_BCR 9 +#define NE_GCC_USB3_PHY_SEC_BCR 10 +#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11 +#define NE_GCC_USB3PHY_PHY_SEC_BCR 12 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindi= ngs/clock/qcom,nord-nwgcc.h new file mode 100644 index 0000000000000000000000000000000000000000..b6253dd2aa85a3152f99447a60a= 6f8a3e85d8f3c --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H + +/* NW_GCC clocks */ +#define NW_GCC_ACMU_MUX_CLK 0 +#define NW_GCC_CAMERA_AHB_CLK 1 +#define NW_GCC_CAMERA_HF_AXI_CLK 2 +#define NW_GCC_CAMERA_SF_AXI_CLK 3 +#define NW_GCC_CAMERA_TRIG_CLK 4 +#define NW_GCC_CAMERA_XO_CLK 5 +#define NW_GCC_DISP_0_AHB_CLK 6 +#define NW_GCC_DISP_0_HF_AXI_CLK 7 +#define NW_GCC_DISP_0_TRIG_CLK 8 +#define NW_GCC_DISP_1_AHB_CLK 9 +#define NW_GCC_DISP_1_HF_AXI_CLK 10 +#define NW_GCC_DISP_1_TRIG_CLK 11 +#define NW_GCC_DPRX0_AXI_HF_CLK 12 +#define NW_GCC_DPRX0_CFG_AHB_CLK 13 +#define NW_GCC_DPRX1_AXI_HF_CLK 14 +#define NW_GCC_DPRX1_CFG_AHB_CLK 15 +#define NW_GCC_EVA_AHB_CLK 16 +#define NW_GCC_EVA_AXI0_CLK 17 +#define NW_GCC_EVA_AXI0C_CLK 18 +#define NW_GCC_EVA_TRIG_CLK 19 +#define NW_GCC_EVA_XO_CLK 20 +#define NW_GCC_FRQ_MEASURE_REF_CLK 21 +#define NW_GCC_GP1_CLK 22 +#define NW_GCC_GP1_CLK_SRC 23 +#define NW_GCC_GP2_CLK 24 +#define NW_GCC_GP2_CLK_SRC 25 +#define NW_GCC_GPLL0 26 +#define NW_GCC_GPLL0_OUT_EVEN 27 +#define NW_GCC_GPU_2_CFG_AHB_CLK 28 +#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29 +#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30 +#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31 +#define NW_GCC_GPU_CFG_AHB_CLK 32 +#define NW_GCC_GPU_GPLL0_CLK_SRC 33 +#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34 +#define NW_GCC_GPU_HSCNOC_GFX_CLK 35 +#define NW_GCC_GPU_SMMU_VOTE_CLK 36 +#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37 +#define NW_GCC_HSCNOC_GPU_AXI_CLK 38 +#define NW_GCC_MMU_1_TCU_VOTE_CLK 39 +#define NW_GCC_VIDEO_AHB_CLK 40 +#define NW_GCC_VIDEO_AXI0_CLK 41 +#define NW_GCC_VIDEO_AXI0C_CLK 42 +#define NW_GCC_VIDEO_AXI1_CLK 43 +#define NW_GCC_VIDEO_XO_CLK 44 + +/* NW_GCC power domains */ + +/* NW_GCC resets */ +#define NW_GCC_CAMERA_BCR 0 +#define NW_GCC_DISPLAY_0_BCR 1 +#define NW_GCC_DISPLAY_1_BCR 2 +#define NW_GCC_DPRX0_BCR 3 +#define NW_GCC_DPRX1_BCR 4 +#define NW_GCC_EVA_BCR 5 +#define NW_GCC_GPU_2_BCR 6 +#define NW_GCC_GPU_BCR 7 +#define NW_GCC_VIDEO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindi= ngs/clock/qcom,nord-segcc.h new file mode 100644 index 0000000000000000000000000000000000000000..f0f7422af692d05417d126c1011= a22faf3bdc611 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-segcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H + +/* SE_GCC clocks */ +#define SE_GCC_EEE_EMAC0_CLK 0 +#define SE_GCC_EEE_EMAC0_CLK_SRC 1 +#define SE_GCC_EEE_EMAC1_CLK 2 +#define SE_GCC_EEE_EMAC1_CLK_SRC 3 +#define SE_GCC_EMAC0_AXI_CLK 4 +#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5 +#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6 +#define SE_GCC_EMAC0_PHY_AUX_CLK 7 +#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8 +#define SE_GCC_EMAC0_PTP_CLK 9 +#define SE_GCC_EMAC0_PTP_CLK_SRC 10 +#define SE_GCC_EMAC0_RGMII_CLK 11 +#define SE_GCC_EMAC0_RGMII_CLK_SRC 12 +#define SE_GCC_EMAC0_RPCS_RX_CLK 13 +#define SE_GCC_EMAC0_RPCS_TX_CLK 14 +#define SE_GCC_EMAC0_XGXS_RX_CLK 15 +#define SE_GCC_EMAC0_XGXS_TX_CLK 16 +#define SE_GCC_EMAC1_AXI_CLK 17 +#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18 +#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19 +#define SE_GCC_EMAC1_PHY_AUX_CLK 20 +#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21 +#define SE_GCC_EMAC1_PTP_CLK 22 +#define SE_GCC_EMAC1_PTP_CLK_SRC 23 +#define SE_GCC_EMAC1_RGMII_CLK 24 +#define SE_GCC_EMAC1_RGMII_CLK_SRC 25 +#define SE_GCC_EMAC1_RPCS_RX_CLK 26 +#define SE_GCC_EMAC1_RPCS_TX_CLK 27 +#define SE_GCC_EMAC1_XGXS_RX_CLK 28 +#define SE_GCC_EMAC1_XGXS_TX_CLK 29 +#define SE_GCC_FRQ_MEASURE_REF_CLK 30 +#define SE_GCC_GP1_CLK 31 +#define SE_GCC_GP1_CLK_SRC 32 +#define SE_GCC_GP2_CLK 33 +#define SE_GCC_GP2_CLK_SRC 34 +#define SE_GCC_GPLL0 35 +#define SE_GCC_GPLL0_OUT_EVEN 36 +#define SE_GCC_GPLL2 37 +#define SE_GCC_GPLL4 38 +#define SE_GCC_GPLL5 39 +#define SE_GCC_MMU_2_TCU_VOTE_CLK 40 +#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41 +#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42 +#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43 +#define SE_GCC_QUPV3_WRAP0_S0_CLK 44 +#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45 +#define SE_GCC_QUPV3_WRAP0_S1_CLK 46 +#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47 +#define SE_GCC_QUPV3_WRAP0_S2_CLK 48 +#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49 +#define SE_GCC_QUPV3_WRAP0_S3_CLK 50 +#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51 +#define SE_GCC_QUPV3_WRAP0_S4_CLK 52 +#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53 +#define SE_GCC_QUPV3_WRAP0_S5_CLK 54 +#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55 +#define SE_GCC_QUPV3_WRAP0_S6_CLK 56 +#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57 +#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58 +#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59 +#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60 +#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61 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List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-nord-clks-v1-4-018af14979fd@oss.qualcomm.com> References: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com> In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Taniya Das , Richard Cochran , Shawn Guo , Deepti Jaggi Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11446; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=WngLlsIJYc2VIn1dcAieQln8rLCNCDVE6moeVof9C0I=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBpz8p+Dir+221cIHEjFe9bHg3dZpfJH9yxCPp4f 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engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_04,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604030126 From: Taniya Das Add a clock driver for the TCSR clock controller found on Nord SoC, which provides refclks for PCIE, USB, SGMII, UFS subsystems. Signed-off-by: Taniya Das [Shawn: - Use compatible qcom,nord-tcsrcc - Drop include of as the driver doesn't use any OF APIs] Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Signed-off-by: Bartosz Golaszewski --- drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-nord.c | 337 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 345 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 8f55f10261ec2dd4add61101c5619cc4516f7d66..10c74db7e072f560f4bc26f81b4= 378034d1f9bf6 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -674,6 +674,13 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. =20 +config CLK_NORD_TCSRCC + tristate "Nord TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + help + Support for the TCSR clock controller on Nord devices. + Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc. + config SA_CAMCC_8775P tristate "SA8775P Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 103d6c4b860ccbc6b4ad552e9e6af43298a4474d..1a7ff1986b834f48dbaa2fd8c25= 59f0046ea7579 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o diff --git a/drivers/clk/qcom/tcsrcc-nord.c b/drivers/clk/qcom/tcsrcc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..ed0f4909158f6e7e073e111549a= 8740f6a7fc94c --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-nord.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_dp_rx_0_clkref_en =3D { + .halt_reg =3D 0xa008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xa008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_dp_rx_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_rx_1_clkref_en =3D { + .halt_reg =3D 0xb008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xb008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_dp_rx_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_0_clkref_en =3D { + .halt_reg =3D 0xc008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xc008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_dp_tx_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_1_clkref_en =3D { + .halt_reg =3D 0xd008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xd008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_dp_tx_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_2_clkref_en =3D { + .halt_reg =3D 0xe008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xe008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_dp_tx_2_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_dp_tx_3_clkref_en =3D { + .halt_reg =3D 0xf008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xf008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_dp_tx_3_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_clkref_en =3D { + .halt_reg =3D 0x8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_pcie_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en =3D { + .halt_reg =3D 0x3008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x3008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_ufs_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_0_clkref_en =3D { + .halt_reg =3D 0x4008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x4008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_1_clkref_en =3D { + .halt_reg =3D 0x5008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x5008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_2_clkref_en =3D { + .halt_reg =3D 0x6008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x6008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb2_2_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_0_clkref_en =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb3_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_1_clkref_en =3D { + .halt_reg =3D 0x7008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_usb3_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ux_sgmii_0_clkref_en =3D { + .halt_reg =3D 0x1008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_ux_sgmii_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ux_sgmii_1_clkref_en =3D { + .halt_reg =3D 0x2008, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "tcsr_ux_sgmii_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_nord_clocks[] =3D { + [TCSR_DP_RX_0_CLKREF_EN] =3D &tcsr_dp_rx_0_clkref_en.clkr, + [TCSR_DP_RX_1_CLKREF_EN] =3D &tcsr_dp_rx_1_clkref_en.clkr, + [TCSR_DP_TX_0_CLKREF_EN] =3D &tcsr_dp_tx_0_clkref_en.clkr, + [TCSR_DP_TX_1_CLKREF_EN] =3D &tcsr_dp_tx_1_clkref_en.clkr, + [TCSR_DP_TX_2_CLKREF_EN] =3D &tcsr_dp_tx_2_clkref_en.clkr, + [TCSR_DP_TX_3_CLKREF_EN] =3D &tcsr_dp_tx_3_clkref_en.clkr, + [TCSR_PCIE_CLKREF_EN] =3D &tcsr_pcie_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] =3D &tcsr_ufs_clkref_en.clkr, + [TCSR_USB2_0_CLKREF_EN] =3D &tcsr_usb2_0_clkref_en.clkr, + [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, + [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, + [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, + [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, + [TCSR_UX_SGMII_0_CLKREF_EN] =3D &tcsr_ux_sgmii_0_clkref_en.clkr, + [TCSR_UX_SGMII_1_CLKREF_EN] =3D &tcsr_ux_sgmii_1_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf008, + .fast_io =3D true, +}; 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Signed-off-by: Taniya Das Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6a54481cc6ae175b8238117eefb4f38af0ec40a4..0c423a72662ede52a3ec9367985= 9ae5697a9d7c4 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -349,6 +349,10 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); =20 +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a1, "lnbclka1", 1); +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a1, "lnbclka2", 1); +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a1, "lnbclka3", 1); + DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); @@ -965,6 +969,21 @@ static const struct clk_rpmh_desc clk_rpmh_eliza =3D { .num_clks =3D ARRAY_SIZE(eliza_rpmh_clocks), }; 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Introduce driver support for each of these controllers. Signed-off-by: Taniya Das [Shawn: Drop include of as the driver doesn't use any OF APIs] Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Signed-off-by: Bartosz Golaszewski --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-nord.c | 1901 +++++++++++++++++++++++++++++++++++++= ++ drivers/clk/qcom/negcc-nord.c | 1987 +++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/nwgcc-nord.c | 688 ++++++++++++++ drivers/clk/qcom/segcc-nord.c | 1609 +++++++++++++++++++++++++++++++++ 6 files changed, 6196 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 10c74db7e072f560f4bc26f81b4378034d1f9bf6..87efdf67124b3e1c2b6c5b976ef= 404aaa2ab5c23 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -145,6 +145,16 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config CLK_NORD_GCC + tristate "Nord Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on Nord devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination + of GCC, SE_GCC, NE_GCC and NW_GCC. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1a7ff1986b834f48dbaa2fd8c2559f0046ea7579..397261e9e387b4a161229682207= 6c1c001787ad7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..ab24ebeadbdd23b2094d915bd8a= 8c83ae91e0e4f --- /dev/null +++ b/drivers/clk/qcom/gcc-nord.c @@ -0,0 +1,1901 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_PCIE_A_PIPE_CLK, + DT_PCIE_B_PIPE_CLK, + DT_PCIE_C_PIPE_CLK, + DT_PCIE_D_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPLL0_OUT_EVEN, + P_GCC_GPLL0_OUT_MAIN, + P_PCIE_A_PIPE_CLK, + P_PCIE_B_PIPE_CLK, + P_PCIE_C_PIPE_CLK, + P_PCIE_D_PIPE_CLK, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x9d020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src =3D { + .reg =3D 0x49094, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_A_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src =3D { + .reg =3D 0x4a094, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_B_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src =3D { + .reg =3D 0x4b094, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_C_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src =3D { + .reg =3D 0x4c094, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_D_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x30004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x31004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_a_aux_clk_src =3D { + .cmd_rcgr =3D 0x49098, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x4d020, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] =3D { + F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x4907c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_b_aux_clk_src =3D { + .cmd_rcgr =3D 0x4a098, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x4e020, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x4a07c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_c_aux_clk_src =3D { + .cmd_rcgr =3D 0x4b098, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x4f020, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x4b07c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_d_aux_clk_src =3D { + .cmd_rcgr =3D 0x4c098, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x50020, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x4c07c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_a_phy_rchng_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src =3D { + .cmd_rcgr =3D 0x52094, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_refgen_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_noc_safety_clk_src =3D { + .cmd_rcgr =3D 0x520ac, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_a_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_safety_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0), + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x1a010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap3_qspi_ref_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src =3D { + .cmd_rcgr =3D 0x23174, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &gcc_qupv3_wrap3_qspi_ref_clk_src_init, +}; + +static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src =3D { + .reg =3D 0x2316c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_s0_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x1f004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1f004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x30000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x30000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x31000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmu_0_tcu_vote_clk =3D { + .halt_reg =3D 0x7d094, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mmu_0_tcu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_aux_clk =3D { + .halt_reg =3D 0x49058, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x49058, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_a_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_cfg_ahb_clk =3D { + .halt_reg =3D 0x49054, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x49054, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_dti_qtc_clk =3D { + .halt_reg =3D 0x49018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x49018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_dti_qtc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_mstr_axi_clk =3D { + .halt_reg =3D 0x49040, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x49040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_phy_aux_clk =3D { + .halt_reg =3D 0x4d01c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_a_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_phy_rchng_clk =3D { + .halt_reg =3D 0x49078, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x49078, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_a_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_pipe_clk =3D { + .halt_reg =3D 0x49068, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x49068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_a_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_slv_axi_clk =3D { + .halt_reg =3D 0x4902c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4902c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x49024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x49024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_a_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_aux_clk =3D { + .halt_reg =3D 0x4a058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_b_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_cfg_ahb_clk =3D { + .halt_reg =3D 0x4a054, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4a054, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_dti_qtc_clk =3D { + .halt_reg =3D 0x4a018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4a018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_dti_qtc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_mstr_axi_clk =3D { + .halt_reg =3D 0x4a040, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4a040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_phy_aux_clk =3D { + .halt_reg =3D 0x4e01c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_b_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_phy_rchng_clk =3D { + .halt_reg =3D 0x4a078, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_b_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_pipe_clk =3D { + .halt_reg =3D 0x4a068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_b_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_slv_axi_clk =3D { + .halt_reg =3D 0x4a02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4a02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x4a024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_b_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_aux_clk =3D { + .halt_reg =3D 0x4b058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_c_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_cfg_ahb_clk =3D { + .halt_reg =3D 0x4b054, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4b054, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_dti_qtc_clk =3D { + .halt_reg =3D 0x4b018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4b018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_dti_qtc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_mstr_axi_clk =3D { + .halt_reg =3D 0x4b040, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4b040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_phy_aux_clk =3D { + .halt_reg =3D 0x4f01c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_c_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_phy_rchng_clk =3D { + .halt_reg =3D 0x4b078, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_c_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_pipe_clk =3D { + .halt_reg =3D 0x4b068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_c_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_slv_axi_clk =3D { + .halt_reg =3D 0x4b02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4b02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x4b024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d008, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_c_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_aux_clk =3D { + .halt_reg =3D 0x4c058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_d_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_cfg_ahb_clk =3D { + .halt_reg =3D 0x4c054, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4c054, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_dti_qtc_clk =3D { + .halt_reg =3D 0x4c018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4c018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_dti_qtc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_mstr_axi_clk =3D { + .halt_reg =3D 0x4c040, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4c040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_phy_aux_clk =3D { + .halt_reg =3D 0x5001c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_d_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_phy_rchng_clk =3D { + .halt_reg =3D 0x4c078, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_d_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_pipe_clk =3D { + .halt_reg =3D 0x4c068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_d_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_slv_axi_clk =3D { + .halt_reg =3D 0x4c02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4c02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x4c024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_d_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_link_ahb_clk =3D { + .halt_reg =3D 0x52464, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x52464, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_link_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_link_xo_clk =3D { + .halt_reg =3D 0x52468, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x52468, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52468, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_link_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_async_bridge_clk =3D { + .halt_reg =3D 0x52048, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x52048, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_async_bridge_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk =3D { + .halt_reg =3D 0x52040, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x52040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_cnoc_sf_qx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_m_cfg_clk =3D { + .halt_reg =3D 0x52060, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x52060, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_m_cfg_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_m_pdb_clk =3D { + .halt_reg =3D 0x52084, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x52084, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_m_pdb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_mstr_axi_clk =3D { + .halt_reg =3D 0x52050, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x52050, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_pwrctl_clk =3D { + .halt_reg =3D 0x52080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_pwrctl_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_qosgen_extref_clk =3D { + .halt_reg =3D 0x52074, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_qosgen_extref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_refgen_clk =3D { + .halt_reg =3D 0x52078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x52078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_refgen_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_noc_refgen_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_s_cfg_clk =3D { + .halt_reg =3D 0x52064, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_s_cfg_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_s_pdb_clk =3D { + .halt_reg =3D 0x5208c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x5208c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_s_pdb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_safety_clk =3D { + .halt_reg =3D 0x5207c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5207c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_safety_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_noc_safety_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_slave_axi_clk =3D { + .halt_reg =3D 0x52058, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x52058, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_slave_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_tsctr_clk =3D { + .halt_reg =3D 0x52070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_tsctr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_noc_xo_clk =3D { + .halt_reg =3D 0x52068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d018, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_noc_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x1a00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1a00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x1a004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1a004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x1a008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_core_2x_clk =3D { + .halt_reg =3D 0x23020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d000, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_core_clk =3D { + .halt_reg =3D 0x2300c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d000, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_m_clk =3D { + .halt_reg =3D 0x23004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d000, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_m_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk =3D { + .halt_reg =3D 0x23170, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d000, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_qspi_ref_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_s0_clk =3D { + .halt_reg =3D 0x2315c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9d000, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9d010, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap3_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_smmu_pcie_qtc_vote_clk =3D { + .halt_reg =3D 0x7d0b8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d0b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_smmu_pcie_qtc_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gcc_pcie_a_gdsc =3D { + .gdscr =3D 0x49004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(1), + .pd =3D { + .name =3D "gcc_pcie_a_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_a_phy_gdsc =3D { + .gdscr =3D 0x4d004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(5), + .pd =3D { + .name =3D "gcc_pcie_a_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_b_gdsc =3D { + .gdscr =3D 0x4a004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(2), + .pd =3D { + .name =3D "gcc_pcie_b_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_b_phy_gdsc =3D { + .gdscr =3D 0x4e004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(6), + .pd =3D { + .name =3D "gcc_pcie_b_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_c_gdsc =3D { + .gdscr =3D 0x4b004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(3), + .pd =3D { + .name =3D "gcc_pcie_c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_c_phy_gdsc =3D { + .gdscr =3D 0x4f004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(7), + .pd =3D { + .name =3D "gcc_pcie_c_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_d_gdsc =3D { + .gdscr =3D 0x4c004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(4), + .pd =3D { + .name =3D "gcc_pcie_d_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_d_phy_gdsc =3D { + .gdscr =3D 0x50004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(8), + .pd =3D { + .name =3D "gcc_pcie_d_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_noc_gdsc =3D { + .gdscr =3D 0x52004, + .gds_hw_ctrl =3D 0x52018, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .collapse_ctrl =3D 0x8d02c, + .collapse_mask =3D BIT(0), + .pd =3D { + .name =3D "gcc_pcie_noc_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gcc_nord_clocks[] =3D { + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GPLL0] =3D &gcc_gpll0.clkr, + [GCC_GPLL0_OUT_EVEN] =3D &gcc_gpll0_out_even.clkr, + [GCC_MMU_0_TCU_VOTE_CLK] =3D &gcc_mmu_0_tcu_vote_clk.clkr, + [GCC_PCIE_A_AUX_CLK] =3D &gcc_pcie_a_aux_clk.clkr, + [GCC_PCIE_A_AUX_CLK_SRC] =3D &gcc_pcie_a_aux_clk_src.clkr, + [GCC_PCIE_A_CFG_AHB_CLK] =3D &gcc_pcie_a_cfg_ahb_clk.clkr, + [GCC_PCIE_A_DTI_QTC_CLK] =3D &gcc_pcie_a_dti_qtc_clk.clkr, + [GCC_PCIE_A_MSTR_AXI_CLK] =3D &gcc_pcie_a_mstr_axi_clk.clkr, + [GCC_PCIE_A_PHY_AUX_CLK] =3D &gcc_pcie_a_phy_aux_clk.clkr, + [GCC_PCIE_A_PHY_AUX_CLK_SRC] =3D &gcc_pcie_a_phy_aux_clk_src.clkr, + [GCC_PCIE_A_PHY_RCHNG_CLK] =3D &gcc_pcie_a_phy_rchng_clk.clkr, + [GCC_PCIE_A_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_a_phy_rchng_clk_src.clkr, + [GCC_PCIE_A_PIPE_CLK] =3D &gcc_pcie_a_pipe_clk.clkr, + [GCC_PCIE_A_PIPE_CLK_SRC] =3D &gcc_pcie_a_pipe_clk_src.clkr, + [GCC_PCIE_A_SLV_AXI_CLK] =3D &gcc_pcie_a_slv_axi_clk.clkr, + [GCC_PCIE_A_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_a_slv_q2a_axi_clk.clkr, + [GCC_PCIE_B_AUX_CLK] =3D &gcc_pcie_b_aux_clk.clkr, + [GCC_PCIE_B_AUX_CLK_SRC] =3D &gcc_pcie_b_aux_clk_src.clkr, + [GCC_PCIE_B_CFG_AHB_CLK] =3D &gcc_pcie_b_cfg_ahb_clk.clkr, + [GCC_PCIE_B_DTI_QTC_CLK] =3D &gcc_pcie_b_dti_qtc_clk.clkr, + [GCC_PCIE_B_MSTR_AXI_CLK] =3D &gcc_pcie_b_mstr_axi_clk.clkr, + [GCC_PCIE_B_PHY_AUX_CLK] =3D &gcc_pcie_b_phy_aux_clk.clkr, + [GCC_PCIE_B_PHY_AUX_CLK_SRC] =3D &gcc_pcie_b_phy_aux_clk_src.clkr, + [GCC_PCIE_B_PHY_RCHNG_CLK] =3D &gcc_pcie_b_phy_rchng_clk.clkr, + [GCC_PCIE_B_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_b_phy_rchng_clk_src.clkr, + [GCC_PCIE_B_PIPE_CLK] =3D &gcc_pcie_b_pipe_clk.clkr, + [GCC_PCIE_B_PIPE_CLK_SRC] =3D &gcc_pcie_b_pipe_clk_src.clkr, + [GCC_PCIE_B_SLV_AXI_CLK] =3D &gcc_pcie_b_slv_axi_clk.clkr, + [GCC_PCIE_B_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_b_slv_q2a_axi_clk.clkr, + [GCC_PCIE_C_AUX_CLK] =3D &gcc_pcie_c_aux_clk.clkr, + [GCC_PCIE_C_AUX_CLK_SRC] =3D &gcc_pcie_c_aux_clk_src.clkr, + [GCC_PCIE_C_CFG_AHB_CLK] =3D &gcc_pcie_c_cfg_ahb_clk.clkr, + [GCC_PCIE_C_DTI_QTC_CLK] =3D &gcc_pcie_c_dti_qtc_clk.clkr, + [GCC_PCIE_C_MSTR_AXI_CLK] =3D &gcc_pcie_c_mstr_axi_clk.clkr, + [GCC_PCIE_C_PHY_AUX_CLK] =3D &gcc_pcie_c_phy_aux_clk.clkr, + [GCC_PCIE_C_PHY_AUX_CLK_SRC] =3D &gcc_pcie_c_phy_aux_clk_src.clkr, + [GCC_PCIE_C_PHY_RCHNG_CLK] =3D &gcc_pcie_c_phy_rchng_clk.clkr, + [GCC_PCIE_C_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_c_phy_rchng_clk_src.clkr, + [GCC_PCIE_C_PIPE_CLK] =3D &gcc_pcie_c_pipe_clk.clkr, + [GCC_PCIE_C_PIPE_CLK_SRC] =3D &gcc_pcie_c_pipe_clk_src.clkr, + [GCC_PCIE_C_SLV_AXI_CLK] =3D &gcc_pcie_c_slv_axi_clk.clkr, + [GCC_PCIE_C_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_c_slv_q2a_axi_clk.clkr, + [GCC_PCIE_D_AUX_CLK] =3D &gcc_pcie_d_aux_clk.clkr, + [GCC_PCIE_D_AUX_CLK_SRC] =3D &gcc_pcie_d_aux_clk_src.clkr, + [GCC_PCIE_D_CFG_AHB_CLK] =3D &gcc_pcie_d_cfg_ahb_clk.clkr, + [GCC_PCIE_D_DTI_QTC_CLK] =3D &gcc_pcie_d_dti_qtc_clk.clkr, + [GCC_PCIE_D_MSTR_AXI_CLK] =3D &gcc_pcie_d_mstr_axi_clk.clkr, + [GCC_PCIE_D_PHY_AUX_CLK] =3D &gcc_pcie_d_phy_aux_clk.clkr, + [GCC_PCIE_D_PHY_AUX_CLK_SRC] =3D &gcc_pcie_d_phy_aux_clk_src.clkr, + [GCC_PCIE_D_PHY_RCHNG_CLK] =3D &gcc_pcie_d_phy_rchng_clk.clkr, + [GCC_PCIE_D_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_d_phy_rchng_clk_src.clkr, + [GCC_PCIE_D_PIPE_CLK] =3D &gcc_pcie_d_pipe_clk.clkr, + [GCC_PCIE_D_PIPE_CLK_SRC] =3D &gcc_pcie_d_pipe_clk_src.clkr, + [GCC_PCIE_D_SLV_AXI_CLK] =3D &gcc_pcie_d_slv_axi_clk.clkr, + [GCC_PCIE_D_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_d_slv_q2a_axi_clk.clkr, + [GCC_PCIE_LINK_AHB_CLK] =3D &gcc_pcie_link_ahb_clk.clkr, + [GCC_PCIE_LINK_XO_CLK] =3D &gcc_pcie_link_xo_clk.clkr, + [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] =3D &gcc_pcie_noc_async_bridge_clk.clkr, + [GCC_PCIE_NOC_CNOC_SF_QX_CLK] =3D &gcc_pcie_noc_cnoc_sf_qx_clk.clkr, + [GCC_PCIE_NOC_M_CFG_CLK] =3D &gcc_pcie_noc_m_cfg_clk.clkr, + [GCC_PCIE_NOC_M_PDB_CLK] =3D &gcc_pcie_noc_m_pdb_clk.clkr, + [GCC_PCIE_NOC_MSTR_AXI_CLK] =3D &gcc_pcie_noc_mstr_axi_clk.clkr, + [GCC_PCIE_NOC_PWRCTL_CLK] =3D &gcc_pcie_noc_pwrctl_clk.clkr, + [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] =3D &gcc_pcie_noc_qosgen_extref_clk.clkr, + [GCC_PCIE_NOC_REFGEN_CLK] =3D &gcc_pcie_noc_refgen_clk.clkr, + [GCC_PCIE_NOC_REFGEN_CLK_SRC] =3D &gcc_pcie_noc_refgen_clk_src.clkr, + [GCC_PCIE_NOC_S_CFG_CLK] =3D &gcc_pcie_noc_s_cfg_clk.clkr, + [GCC_PCIE_NOC_S_PDB_CLK] =3D &gcc_pcie_noc_s_pdb_clk.clkr, + [GCC_PCIE_NOC_SAFETY_CLK] =3D &gcc_pcie_noc_safety_clk.clkr, + [GCC_PCIE_NOC_SAFETY_CLK_SRC] =3D &gcc_pcie_noc_safety_clk_src.clkr, + [GCC_PCIE_NOC_SLAVE_AXI_CLK] =3D &gcc_pcie_noc_slave_axi_clk.clkr, + [GCC_PCIE_NOC_TSCTR_CLK] =3D &gcc_pcie_noc_tsctr_clk.clkr, + [GCC_PCIE_NOC_XO_CLK] =3D &gcc_pcie_noc_xo_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QUPV3_WRAP3_CORE_2X_CLK] =3D &gcc_qupv3_wrap3_core_2x_clk.clkr, + [GCC_QUPV3_WRAP3_CORE_CLK] =3D &gcc_qupv3_wrap3_core_clk.clkr, + [GCC_QUPV3_WRAP3_M_CLK] =3D &gcc_qupv3_wrap3_m_clk.clkr, + [GCC_QUPV3_WRAP3_QSPI_REF_CLK] =3D &gcc_qupv3_wrap3_qspi_ref_clk.clkr, + [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] =3D &gcc_qupv3_wrap3_qspi_ref_clk_src.= clkr, + [GCC_QUPV3_WRAP3_S0_CLK] =3D &gcc_qupv3_wrap3_s0_clk.clkr, + [GCC_QUPV3_WRAP3_S0_CLK_SRC] =3D &gcc_qupv3_wrap3_s0_clk_src.clkr, + [GCC_QUPV3_WRAP3_S_AHB_CLK] =3D &gcc_qupv3_wrap3_s_ahb_clk.clkr, + [GCC_SMMU_PCIE_QTC_VOTE_CLK] =3D &gcc_smmu_pcie_qtc_vote_clk.clkr, +}; + +static struct gdsc *gcc_nord_gdscs[] =3D { + [GCC_PCIE_A_GDSC] =3D &gcc_pcie_a_gdsc, + [GCC_PCIE_A_PHY_GDSC] =3D &gcc_pcie_a_phy_gdsc, + [GCC_PCIE_B_GDSC] =3D &gcc_pcie_b_gdsc, + [GCC_PCIE_B_PHY_GDSC] =3D &gcc_pcie_b_phy_gdsc, + [GCC_PCIE_C_GDSC] =3D &gcc_pcie_c_gdsc, + [GCC_PCIE_C_PHY_GDSC] =3D &gcc_pcie_c_phy_gdsc, + [GCC_PCIE_D_GDSC] =3D &gcc_pcie_d_gdsc, + [GCC_PCIE_D_PHY_GDSC] =3D &gcc_pcie_d_phy_gdsc, + [GCC_PCIE_NOC_GDSC] =3D &gcc_pcie_noc_gdsc, +}; + +static const struct qcom_reset_map gcc_nord_resets[] =3D { + [GCC_PCIE_A_BCR] =3D { 0x49000 }, + [GCC_PCIE_A_LINK_DOWN_BCR] =3D { 0xb9000 }, + [GCC_PCIE_A_NOCSR_COM_PHY_BCR] =3D { 0xb900c }, + [GCC_PCIE_A_PHY_BCR] =3D { 0x4d000 }, + [GCC_PCIE_A_PHY_CFG_AHB_BCR] =3D { 0xb9014 }, + [GCC_PCIE_A_PHY_COM_BCR] =3D { 0xb9018 }, + [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] =3D { 0xb9010 }, + [GCC_PCIE_B_BCR] =3D { 0x4a000 }, + [GCC_PCIE_B_LINK_DOWN_BCR] =3D { 0xba000 }, + [GCC_PCIE_B_NOCSR_COM_PHY_BCR] =3D { 0xba008 }, + [GCC_PCIE_B_PHY_BCR] =3D { 0x4e000 }, + [GCC_PCIE_B_PHY_CFG_AHB_BCR] =3D { 0xba010 }, + [GCC_PCIE_B_PHY_COM_BCR] =3D { 0xba014 }, + [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] =3D { 0xba00c }, + [GCC_PCIE_C_BCR] =3D { 0x4b000 }, + [GCC_PCIE_C_LINK_DOWN_BCR] =3D { 0xbb07c }, + [GCC_PCIE_C_NOCSR_COM_PHY_BCR] =3D { 0xbb084 }, + [GCC_PCIE_C_PHY_BCR] =3D { 0x4f000 }, + [GCC_PCIE_C_PHY_CFG_AHB_BCR] =3D { 0xbb08c }, + [GCC_PCIE_C_PHY_COM_BCR] =3D { 0xbb090 }, + [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] =3D { 0xbb088 }, + [GCC_PCIE_D_BCR] =3D { 0x4c000 }, + [GCC_PCIE_D_LINK_DOWN_BCR] =3D { 0xbc000 }, + [GCC_PCIE_D_NOCSR_COM_PHY_BCR] =3D { 0xbc008 }, + [GCC_PCIE_D_PHY_BCR] =3D { 0x50000 }, + [GCC_PCIE_D_PHY_CFG_AHB_BCR] =3D { 0xbc010 }, + [GCC_PCIE_D_PHY_COM_BCR] =3D { 0xbc014 }, + [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] =3D { 0xbc00c }, + [GCC_PCIE_NOC_BCR] =3D { 0x52000 }, + [GCC_PDM_BCR] =3D { 0x1a000 }, + [GCC_QUPV3_WRAPPER_3_BCR] =3D { 0x23000 }, + [GCC_TCSR_PCIE_BCR] =3D { 0xb901c }, +}; + +static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src), +}; + +static const struct regmap_config gcc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data gcc_nord_driver_data =3D { + .dfs_rcgs =3D gcc_nord_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_nord_dfs_clocks), +}; + +static const struct qcom_cc_desc gcc_nord_desc =3D { + .config =3D &gcc_nord_regmap_config, + .clks =3D gcc_nord_clocks, + .num_clks =3D ARRAY_SIZE(gcc_nord_clocks), + .resets =3D gcc_nord_resets, + .num_resets =3D ARRAY_SIZE(gcc_nord_resets), + .gdscs =3D gcc_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_nord_gdscs), + .driver_data =3D &gcc_nord_driver_data, +}; + +static const struct of_device_id gcc_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_nord_match_table); + +static int gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_nord_desc); +} + +static struct platform_driver gcc_nord_driver =3D { + .probe =3D gcc_nord_probe, + .driver =3D { + .name =3D "gcc-nord", + .of_match_table =3D gcc_nord_match_table, + }, +}; + +static int __init gcc_nord_init(void) +{ + return platform_driver_register(&gcc_nord_driver); +} +subsys_initcall(gcc_nord_init); + +static void __exit gcc_nord_exit(void) +{ + platform_driver_unregister(&gcc_nord_driver); +} +module_exit(gcc_nord_exit); + +MODULE_DESCRIPTION("QTI GCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..1aa24e2784e536e6b6e76f488ab= d0e2fcc435380 --- /dev/null +++ b/drivers/clk/qcom/negcc-nord.c @@ -0,0 +1,1987 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_UFS_PHY_RX_SYMBOL_0_CLK, + DT_UFS_PHY_RX_SYMBOL_1_CLK, + DT_UFS_PHY_TX_SYMBOL_0_CLK, + DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, + DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_NE_GCC_GPLL0_OUT_EVEN, + P_NE_GCC_GPLL0_OUT_MAIN, + P_NE_GCC_GPLL2_OUT_MAIN, + P_SLEEP_CLK, + P_UFS_PHY_RX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_1_CLK, + P_UFS_PHY_TX_SYMBOL_0_CLK, + P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, + P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, +}; + +static struct clk_alpha_pll ne_gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_ne_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll ne_gcc_gpll2 =3D { + .offset =3D 0x2000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map ne_gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &ne_gcc_gpll0.clkr.hw }, +}; + +static const struct parent_map ne_gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_NE_GCC_GPLL0_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &ne_gcc_gpll0.clkr.hw }, + { .hw =3D &ne_gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map ne_gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_NE_GCC_GPLL2_OUT_MAIN, 3 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &ne_gcc_gpll0.clkr.hw }, + { .hw =3D &ne_gcc_gpll2.clkr.hw }, +}; + +static const struct parent_map ne_gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map ne_gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_NE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &ne_gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map ne_gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map ne_gcc_parent_map_6[] =3D { + { P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_6[] =3D { + { .index =3D DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map ne_gcc_parent_map_7[] =3D { + { P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data ne_gcc_parent_data_7[] =3D { + { .index =3D DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src =3D { + .reg =3D 0x33068, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_rx_symbol_0_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_UFS_PHY_RX_SYMBOL_0_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src =3D { + .reg =3D 0x330f0, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_rx_symbol_1_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_UFS_PHY_RX_SYMBOL_1_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src =3D { + .reg =3D 0x33058, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_tx_symbol_0_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_UFS_PHY_TX_SYMBOL_0_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src =3D { + .reg =3D 0x2a078, + .shift =3D 0, + .width =3D 2, + .parent_map =3D ne_gcc_parent_map_6, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_prim_phy_pipe_clk_src", + .parent_data =3D ne_gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_6), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src =3D { + .reg =3D 0x2c078, + .shift =3D 0, + .width =3D 2, + .parent_map =3D ne_gcc_parent_map_7, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_sec_phy_pipe_clk_src", + .parent_data =3D ne_gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_7), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] =3D { + F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x21004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_4, + .freq_tbl =3D ftbl_ne_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gp1_clk_src", + .parent_data =3D ne_gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x22004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_4, + .freq_tbl =3D ftbl_ne_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gp2_clk_src", + .parent_data =3D ne_gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] =3D { + F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), + F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), + F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), + F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s0_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src =3D { + .cmd_rcgr =3D 0x3816c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s0_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s1_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src =3D { + .cmd_rcgr =3D 0x382a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] =3D { + F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s2_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src =3D { + .cmd_rcgr =3D 0x383e4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s2_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s3_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src =3D { + .cmd_rcgr =3D 0x38520, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s3_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s4_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src =3D { + .cmd_rcgr =3D 0x3865c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s4_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s5_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src =3D { + .cmd_rcgr =3D 0x38798, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s5_clk_src_init, +}; + +static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init =3D { + .name =3D "ne_gcc_qupv3_wrap2_s6_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src =3D { + .cmd_rcgr =3D 0x388d4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_qupv3_wrap2_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &ne_gcc_qupv3_wrap2_s6_clk_src_init, +}; + +static const struct freq_tbl ftbl_ne_gcc_sdcc4_apps_clk_src[] =3D { + F(37500000, P_NE_GCC_GPLL0_OUT_MAIN, 16, 0, 0), + F(50000000, P_NE_GCC_GPLL0_OUT_MAIN, 12, 0, 0), + F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x1801c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_sdcc4_apps_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_sdcc4_apps_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_ufs_phy_axi_clk_src[] =3D { + F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(201500000, P_NE_GCC_GPLL2_OUT_MAIN, 4, 0, 0), + F(300000000, P_NE_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(403000000, P_NE_GCC_GPLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x33034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_2, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_axi_clk_src", + .parent_data =3D ne_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x3308c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_2, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D ne_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_ufs_phy_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x330c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_5, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D ne_gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x330a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_2, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D ne_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_usb20_master_clk_src[] =3D { + F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_usb20_master_clk_src =3D { + .cmd_rcgr =3D 0x31030, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_usb20_master_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb20_master_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb20_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x31048, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb20_mock_utmi_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ne_gcc_usb31_prim_master_clk_src[] =3D { + F(85714286, P_NE_GCC_GPLL0_OUT_MAIN, 7, 0, 0), + F(133333333, P_NE_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_NE_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 ne_gcc_usb31_prim_master_clk_src =3D { + .cmd_rcgr =3D 0x2a038, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_1, + .freq_tbl =3D ftbl_ne_gcc_usb31_prim_master_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_master_clk_src", + .parent_data =3D ne_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb31_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2a050, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_mock_utmi_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb31_sec_master_clk_src =3D { + .cmd_rcgr =3D 0x2c038, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_usb31_prim_master_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_master_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb31_sec_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2c050, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_0, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_mock_utmi_clk_src", + .parent_data =3D ne_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x2a07c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_3, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D ne_gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ne_gcc_usb3_sec_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x2c07c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D ne_gcc_parent_map_3, + .freq_tbl =3D ftbl_ne_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_sec_phy_aux_clk_src", + .parent_data =3D ne_gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(ne_gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div ne_gcc_usb20_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x31060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src = =3D { + .reg =3D 0x2a068, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src = =3D { + .reg =3D 0x2c068, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x330f4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x330f4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x330f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_aggre_noc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_usb2_axi_clk =3D { + .halt_reg =3D 0x31068, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x31068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x31068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_aggre_noc_usb2_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x2a098, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2a098, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2a098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_aggre_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_aggre_noc_usb3_sec_axi_clk =3D { + .halt_reg =3D 0x2c098, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2c098, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2c098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_aggre_noc_usb3_sec_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ahb2phy_clk =3D { + .halt_reg =3D 0x30004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x30004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x30004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ahb2phy_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_cnoc_usb2_axi_clk =3D { + .halt_reg =3D 0x31064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x31064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x31064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_cnoc_usb2_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_cnoc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x2a094, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2a094, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2a094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_cnoc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_cnoc_usb3_sec_axi_clk =3D { + .halt_reg =3D 0x2c094, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2c094, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2c094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_cnoc_usb3_sec_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_frq_measure_ref_clk =3D { + .halt_reg =3D 0x20008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_frq_measure_ref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gp1_clk =3D { + .halt_reg =3D 0x21000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gp2_clk =3D { + .halt_reg =3D 0x22000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x22000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_cfg_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x34004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x34004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpu_2_cfg_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpu_2_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpu_2_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_hscnoc_gfx_clk =3D { + .halt_reg =3D 0x34014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x34014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x34014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpu_2_hscnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_gpu_2_smmu_vote_clk =3D { + .halt_reg =3D 0x57028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_gpu_2_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_core_2x_clk =3D { + .halt_reg =3D 0x38020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_core_clk =3D { + .halt_reg =3D 0x3800c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_m_ahb_clk =3D { + .halt_reg =3D 0x38004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s0_clk =3D { + .halt_reg =3D 0x3815c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s1_clk =3D { + .halt_reg =3D 0x38298, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s2_clk =3D { + .halt_reg =3D 0x383d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s3_clk =3D { + .halt_reg =3D 0x38510, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s4_clk =3D { + .halt_reg =3D 0x3864c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s5_clk =3D { + .halt_reg =3D 0x38788, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s6_clk =3D { + .halt_reg =3D 0x388c4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_qupv3_wrap2_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_qupv3_wrap2_s_ahb_clk =3D { + .halt_reg =3D 0x38008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_qupv3_wrap2_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x18004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x18004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_sdcc4_axi_clk =3D { + .halt_reg =3D 0x18014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x18014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_sdcc4_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x33028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x33028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x33018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x33018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x3307c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3307c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3307c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x330bc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x330bc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x330bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x33030, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x33030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_rx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x330d8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x330d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_rx_symbol_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x3302c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x3302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_tx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x3306c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3306c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3306c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb20_master_clk =3D { + .halt_reg =3D 0x31018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb20_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb20_mock_utmi_clk =3D { + .halt_reg =3D 0x3102c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3102c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb20_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb20_sleep_clk =3D { + .halt_reg =3D 0x31028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x31028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb20_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_atb_clk =3D { + .halt_reg =3D 0x2a018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2a018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_eud_ahb_clk =3D { + .halt_reg =3D 0x2a02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2a02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2a02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_eud_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_master_clk =3D { + .halt_reg =3D 0x2a01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_mock_utmi_clk =3D { + .halt_reg =3D 0x2a034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_prim_sleep_clk =3D { + .halt_reg =3D 0x2a030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_atb_clk =3D { + .halt_reg =3D 0x2c018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_eud_ahb_clk =3D { + .halt_reg =3D 0x2c02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2c02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2c02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_eud_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_master_clk =3D { + .halt_reg =3D 0x2c01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_mock_utmi_clk =3D { + .halt_reg =3D 0x2c034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb31_sec_sleep_clk =3D { + .halt_reg =3D 0x2c030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb31_sec_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0x2a06c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a06c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0x2a070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0x2a074, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2a074, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2a074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_prim_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_sec_phy_aux_clk =3D { + .halt_reg =3D 0x2c06c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c06c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_sec_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk =3D { + .halt_reg =3D 0x2c070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2c070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_sec_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk =3D { + .halt_reg =3D 0x2c074, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2c074, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2c074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ne_gcc_usb3_sec_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc ne_gcc_ufs_mem_phy_gdsc =3D { + .gdscr =3D 0x32000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "ne_gcc_ufs_mem_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_ufs_phy_gdsc =3D { + .gdscr =3D 0x33004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ne_gcc_ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb20_prim_gdsc =3D { + .gdscr =3D 0x31004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ne_gcc_usb20_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb31_prim_gdsc =3D { + .gdscr =3D 0x2a004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ne_gcc_usb31_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb31_sec_gdsc =3D { + .gdscr =3D 0x2c004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "ne_gcc_usb31_sec_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb3_phy_gdsc =3D { + .gdscr =3D 0x2b00c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "ne_gcc_usb3_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc ne_gcc_usb3_sec_phy_gdsc =3D { + .gdscr =3D 0x2d00c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "ne_gcc_usb3_sec_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *ne_gcc_nord_clocks[] =3D { + [NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK] =3D &ne_gcc_aggre_noc_ufs_phy_axi_clk.= clkr, + [NE_GCC_AGGRE_NOC_USB2_AXI_CLK] =3D &ne_gcc_aggre_noc_usb2_axi_clk.clkr, + [NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK] =3D &ne_gcc_aggre_noc_usb3_prim_axi_= clk.clkr, + [NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK] =3D &ne_gcc_aggre_noc_usb3_sec_axi_cl= k.clkr, + [NE_GCC_AHB2PHY_CLK] =3D &ne_gcc_ahb2phy_clk.clkr, + [NE_GCC_CNOC_USB2_AXI_CLK] =3D &ne_gcc_cnoc_usb2_axi_clk.clkr, + [NE_GCC_CNOC_USB3_PRIM_AXI_CLK] =3D &ne_gcc_cnoc_usb3_prim_axi_clk.clkr, + [NE_GCC_CNOC_USB3_SEC_AXI_CLK] =3D &ne_gcc_cnoc_usb3_sec_axi_clk.clkr, + [NE_GCC_FRQ_MEASURE_REF_CLK] =3D &ne_gcc_frq_measure_ref_clk.clkr, + [NE_GCC_GP1_CLK] =3D &ne_gcc_gp1_clk.clkr, + [NE_GCC_GP1_CLK_SRC] =3D &ne_gcc_gp1_clk_src.clkr, + [NE_GCC_GP2_CLK] =3D &ne_gcc_gp2_clk.clkr, + [NE_GCC_GP2_CLK_SRC] =3D &ne_gcc_gp2_clk_src.clkr, + [NE_GCC_GPLL0] =3D &ne_gcc_gpll0.clkr, + [NE_GCC_GPLL0_OUT_EVEN] =3D &ne_gcc_gpll0_out_even.clkr, + [NE_GCC_GPLL2] =3D &ne_gcc_gpll2.clkr, + [NE_GCC_GPU_2_CFG_CLK] =3D &ne_gcc_gpu_2_cfg_clk.clkr, + [NE_GCC_GPU_2_GPLL0_CLK_SRC] =3D &ne_gcc_gpu_2_gpll0_clk_src.clkr, + [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] =3D &ne_gcc_gpu_2_gpll0_div_clk_src.clkr, + [NE_GCC_GPU_2_HSCNOC_GFX_CLK] =3D &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr, + [NE_GCC_GPU_2_SMMU_VOTE_CLK] =3D &ne_gcc_gpu_2_smmu_vote_clk.clkr, + [NE_GCC_QUPV3_WRAP2_CORE_2X_CLK] =3D &ne_gcc_qupv3_wrap2_core_2x_clk.clkr, + [NE_GCC_QUPV3_WRAP2_CORE_CLK] =3D &ne_gcc_qupv3_wrap2_core_clk.clkr, + [NE_GCC_QUPV3_WRAP2_M_AHB_CLK] =3D &ne_gcc_qupv3_wrap2_m_ahb_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S0_CLK] =3D &ne_gcc_qupv3_wrap2_s0_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S0_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s0_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S1_CLK] =3D &ne_gcc_qupv3_wrap2_s1_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S1_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s1_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S2_CLK] =3D &ne_gcc_qupv3_wrap2_s2_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S2_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s2_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S3_CLK] =3D &ne_gcc_qupv3_wrap2_s3_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S3_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s3_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S4_CLK] =3D &ne_gcc_qupv3_wrap2_s4_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S4_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s4_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S5_CLK] =3D &ne_gcc_qupv3_wrap2_s5_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S5_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s5_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S6_CLK] =3D &ne_gcc_qupv3_wrap2_s6_clk.clkr, + [NE_GCC_QUPV3_WRAP2_S6_CLK_SRC] =3D &ne_gcc_qupv3_wrap2_s6_clk_src.clkr, + [NE_GCC_QUPV3_WRAP2_S_AHB_CLK] =3D &ne_gcc_qupv3_wrap2_s_ahb_clk.clkr, + [NE_GCC_SDCC4_APPS_CLK] =3D &ne_gcc_sdcc4_apps_clk.clkr, + [NE_GCC_SDCC4_APPS_CLK_SRC] =3D &ne_gcc_sdcc4_apps_clk_src.clkr, + [NE_GCC_SDCC4_AXI_CLK] =3D &ne_gcc_sdcc4_axi_clk.clkr, + [NE_GCC_UFS_PHY_AHB_CLK] =3D &ne_gcc_ufs_phy_ahb_clk.clkr, + [NE_GCC_UFS_PHY_AXI_CLK] =3D &ne_gcc_ufs_phy_axi_clk.clkr, + [NE_GCC_UFS_PHY_AXI_CLK_SRC] =3D &ne_gcc_ufs_phy_axi_clk_src.clkr, + [NE_GCC_UFS_PHY_ICE_CORE_CLK] =3D &ne_gcc_ufs_phy_ice_core_clk.clkr, + [NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &ne_gcc_ufs_phy_ice_core_clk_src.cl= kr, + [NE_GCC_UFS_PHY_PHY_AUX_CLK] =3D &ne_gcc_ufs_phy_phy_aux_clk.clkr, + [NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &ne_gcc_ufs_phy_phy_aux_clk_src.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &ne_gcc_ufs_phy_rx_symbol_0_clk.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =3D &ne_gcc_ufs_phy_rx_symbol_0_clk_= src.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &ne_gcc_ufs_phy_rx_symbol_1_clk.clkr, + [NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =3D &ne_gcc_ufs_phy_rx_symbol_1_clk_= src.clkr, + [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &ne_gcc_ufs_phy_tx_symbol_0_clk.clkr, + [NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =3D &ne_gcc_ufs_phy_tx_symbol_0_clk_= src.clkr, + [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &ne_gcc_ufs_phy_unipro_core_clk.clkr, + [NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D &ne_gcc_ufs_phy_unipro_core_clk_= src.clkr, + [NE_GCC_USB20_MASTER_CLK] =3D &ne_gcc_usb20_master_clk.clkr, + [NE_GCC_USB20_MASTER_CLK_SRC] =3D &ne_gcc_usb20_master_clk_src.clkr, + [NE_GCC_USB20_MOCK_UTMI_CLK] =3D &ne_gcc_usb20_mock_utmi_clk.clkr, + [NE_GCC_USB20_MOCK_UTMI_CLK_SRC] =3D &ne_gcc_usb20_mock_utmi_clk_src.clkr, + [NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &ne_gcc_usb20_mock_utmi_post= div_clk_src.clkr, + [NE_GCC_USB20_SLEEP_CLK] =3D &ne_gcc_usb20_sleep_clk.clkr, + [NE_GCC_USB31_PRIM_ATB_CLK] =3D &ne_gcc_usb31_prim_atb_clk.clkr, + [NE_GCC_USB31_PRIM_EUD_AHB_CLK] =3D &ne_gcc_usb31_prim_eud_ahb_clk.clkr, + [NE_GCC_USB31_PRIM_MASTER_CLK] =3D &ne_gcc_usb31_prim_master_clk.clkr, + [NE_GCC_USB31_PRIM_MASTER_CLK_SRC] =3D &ne_gcc_usb31_prim_master_clk_src.= clkr, + [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK] =3D &ne_gcc_usb31_prim_mock_utmi_clk.cl= kr, + [NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC] =3D &ne_gcc_usb31_prim_mock_utmi_cl= k_src.clkr, + [NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =3D + &ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr, + [NE_GCC_USB31_PRIM_SLEEP_CLK] =3D &ne_gcc_usb31_prim_sleep_clk.clkr, + [NE_GCC_USB31_SEC_ATB_CLK] =3D &ne_gcc_usb31_sec_atb_clk.clkr, + [NE_GCC_USB31_SEC_EUD_AHB_CLK] =3D &ne_gcc_usb31_sec_eud_ahb_clk.clkr, + [NE_GCC_USB31_SEC_MASTER_CLK] =3D &ne_gcc_usb31_sec_master_clk.clkr, + [NE_GCC_USB31_SEC_MASTER_CLK_SRC] =3D &ne_gcc_usb31_sec_master_clk_src.cl= kr, + [NE_GCC_USB31_SEC_MOCK_UTMI_CLK] =3D &ne_gcc_usb31_sec_mock_utmi_clk.clkr, + [NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC] =3D &ne_gcc_usb31_sec_mock_utmi_clk_= src.clkr, + [NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =3D + &ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr, + [NE_GCC_USB31_SEC_SLEEP_CLK] =3D &ne_gcc_usb31_sec_sleep_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_AUX_CLK] =3D &ne_gcc_usb3_prim_phy_aux_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &ne_gcc_usb3_prim_phy_aux_clk_src.= clkr, + [NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &ne_gcc_usb3_prim_phy_com_aux_clk.= clkr, + [NE_GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &ne_gcc_usb3_prim_phy_pipe_clk.clkr, + [NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] =3D &ne_gcc_usb3_prim_phy_pipe_clk_sr= c.clkr, + [NE_GCC_USB3_SEC_PHY_AUX_CLK] =3D &ne_gcc_usb3_sec_phy_aux_clk.clkr, + [NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC] =3D &ne_gcc_usb3_sec_phy_aux_clk_src.cl= kr, + [NE_GCC_USB3_SEC_PHY_COM_AUX_CLK] =3D &ne_gcc_usb3_sec_phy_com_aux_clk.cl= kr, + [NE_GCC_USB3_SEC_PHY_PIPE_CLK] =3D &ne_gcc_usb3_sec_phy_pipe_clk.clkr, + [NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC] =3D &ne_gcc_usb3_sec_phy_pipe_clk_src.= clkr, +}; + +static struct gdsc *ne_gcc_nord_gdscs[] =3D { + [NE_GCC_UFS_MEM_PHY_GDSC] =3D &ne_gcc_ufs_mem_phy_gdsc, + [NE_GCC_UFS_PHY_GDSC] =3D &ne_gcc_ufs_phy_gdsc, + [NE_GCC_USB20_PRIM_GDSC] =3D &ne_gcc_usb20_prim_gdsc, + [NE_GCC_USB31_PRIM_GDSC] =3D &ne_gcc_usb31_prim_gdsc, + [NE_GCC_USB31_SEC_GDSC] =3D &ne_gcc_usb31_sec_gdsc, + [NE_GCC_USB3_PHY_GDSC] =3D &ne_gcc_usb3_phy_gdsc, + [NE_GCC_USB3_SEC_PHY_GDSC] =3D &ne_gcc_usb3_sec_phy_gdsc, +}; + +static const struct qcom_reset_map ne_gcc_nord_resets[] =3D { + [NE_GCC_GPU_2_BCR] =3D { 0x34000 }, + [NE_GCC_QUPV3_WRAPPER_2_BCR] =3D { 0x38000 }, + [NE_GCC_SDCC4_BCR] =3D { 0x18000 }, + [NE_GCC_UFS_PHY_BCR] =3D { 0x33000 }, + [NE_GCC_USB20_PRIM_BCR] =3D { 0x31000 }, + [NE_GCC_USB31_PRIM_BCR] =3D { 0x2a000 }, + [NE_GCC_USB31_SEC_BCR] =3D { 0x2c000 }, + [NE_GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x2b008 }, + [NE_GCC_USB3_DP_PHY_SEC_BCR] =3D { 0x2d008 }, + [NE_GCC_USB3_PHY_PRIM_BCR] =3D { 0x2b000 }, + [NE_GCC_USB3_PHY_SEC_BCR] =3D { 0x2d000 }, + [NE_GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x2b004 }, + [NE_GCC_USB3PHY_PHY_SEC_BCR] =3D { 0x2d004 }, +}; + +static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] =3D { + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s0_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s1_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s2_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s3_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s4_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s5_clk_src), + DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s6_clk_src), +}; + +static const struct regmap_config ne_gcc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf41f0, + .fast_io =3D true, +}; + +static void clk_nord_regs_configure(struct device *dev, struct regmap *reg= map) +{ + /* FORCE_MEM_CORE_ON for ne_gcc_ufs_phy_ice_core_clk and ne_gcc_ufs_phy_= axi_clk */ + qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true); +} + +static struct qcom_cc_driver_data ne_gcc_nord_driver_data =3D { + .dfs_rcgs =3D ne_gcc_nord_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(ne_gcc_nord_dfs_clocks), + .clk_regs_configure =3D clk_nord_regs_configure, +}; + +static const struct qcom_cc_desc ne_gcc_nord_desc =3D { + .config =3D &ne_gcc_nord_regmap_config, + .clks =3D ne_gcc_nord_clocks, + .num_clks =3D ARRAY_SIZE(ne_gcc_nord_clocks), + .resets =3D ne_gcc_nord_resets, + .num_resets =3D ARRAY_SIZE(ne_gcc_nord_resets), + .gdscs =3D ne_gcc_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(ne_gcc_nord_gdscs), + .driver_data =3D &ne_gcc_nord_driver_data, +}; + +static const struct of_device_id ne_gcc_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-negcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, ne_gcc_nord_match_table); + +static int ne_gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &ne_gcc_nord_desc); +} + +static struct platform_driver ne_gcc_nord_driver =3D { + .probe =3D ne_gcc_nord_probe, + .driver =3D { + .name =3D "negcc-nord", + .of_match_table =3D ne_gcc_nord_match_table, + }, +}; + +module_platform_driver(ne_gcc_nord_driver); + +MODULE_DESCRIPTION("QTI NEGCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..163ab63c872bc7d5132d68bf0ec= 3e05f5814974d --- /dev/null +++ b/drivers/clk/qcom/nwgcc-nord.c @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_NW_GCC_GPLL0_OUT_EVEN, + P_NW_GCC_GPLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll nw_gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_nw_gcc_gpll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv nw_gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_nw_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_nw_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map nw_gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_NW_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_NW_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data nw_gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &nw_gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &nw_gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct freq_tbl ftbl_nw_gcc_gp1_clk_src[] =3D { + F(60000000, P_NW_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + F(100000000, P_NW_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_NW_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 nw_gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x20004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D nw_gcc_parent_map_0, + .freq_tbl =3D ftbl_nw_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gp1_clk_src", + .parent_data =3D nw_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nw_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 nw_gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x21004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D nw_gcc_parent_map_0, + .freq_tbl =3D ftbl_nw_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gp2_clk_src", + .parent_data =3D nw_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nw_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch nw_gcc_acmu_mux_clk =3D { + .halt_reg =3D 0x1f01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1f01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_acmu_mux_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0x16008, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x16008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x16008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0x1601c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1601c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1601c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_camera_trig_clk =3D { + .halt_reg =3D 0x16034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x16034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x16034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_camera_trig_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_0_hf_axi_clk =3D { + .halt_reg =3D 0x18008, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x18008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x18008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_disp_0_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_0_trig_clk =3D { + .halt_reg =3D 0x1801c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1801c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_disp_0_trig_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_1_hf_axi_clk =3D { + .halt_reg =3D 0x19008, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x19008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x19008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_disp_1_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_disp_1_trig_clk =3D { + .halt_reg =3D 0x1901c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1901c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1901c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_disp_1_trig_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_dprx0_axi_hf_clk =3D { + .halt_reg =3D 0x29004, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x29004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x29004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_dprx0_axi_hf_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_dprx1_axi_hf_clk =3D { + .halt_reg =3D 0x2a004, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x2a004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_dprx1_axi_hf_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_eva_axi0_clk =3D { + .halt_reg =3D 0x1b008, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1b008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1b008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_eva_axi0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_eva_axi0c_clk =3D { + .halt_reg =3D 0x1b01c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1b01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1b01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_eva_axi0c_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_eva_trig_clk =3D { + .halt_reg =3D 0x1b028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1b028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1b028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_eva_trig_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_frq_measure_ref_clk =3D { + .halt_reg =3D 0x1f008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1f008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_frq_measure_ref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gp1_clk =3D { + .halt_reg =3D 0x20000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gp2_clk =3D { + .halt_reg =3D 0x21000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x21000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_2_gpll0_clk_src =3D { + .halt_reg =3D 0x24150, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x24150, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x76000, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_2_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_2_gpll0_div_clk_src =3D { + .halt_reg =3D 0x24158, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x24158, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x76000, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_2_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_2_hscnoc_gfx_clk =3D { + .halt_reg =3D 0x2400c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2400c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_2_hscnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_gpll0_clk_src =3D { + .halt_reg =3D 0x23150, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23150, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x76000, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_gpll0_div_clk_src =3D { + .halt_reg =3D 0x23158, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23158, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x76000, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &nw_gcc_gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_hscnoc_gfx_clk =3D { + .halt_reg =3D 0x2300c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x2300c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_hscnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x86038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x86038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_hscnoc_gpu_2_axi_clk =3D { + .halt_reg =3D 0x24160, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x24160, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x24160, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_hscnoc_gpu_2_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_hscnoc_gpu_axi_clk =3D { + .halt_reg =3D 0x23160, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x23160, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x23160, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_hscnoc_gpu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_mmu_1_tcu_vote_clk =3D { + .halt_reg =3D 0x86040, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x86040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_mmu_1_tcu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_video_axi0_clk =3D { + .halt_reg =3D 0x1a008, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1a008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_video_axi0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_video_axi0c_clk =3D { + .halt_reg =3D 0x1a01c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1a01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1a01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_video_axi0c_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nw_gcc_video_axi1_clk =3D { + .halt_reg =3D 0x1a030, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x1a030, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1a030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nw_gcc_video_axi1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *nw_gcc_nord_clocks[] =3D { + [NW_GCC_ACMU_MUX_CLK] =3D &nw_gcc_acmu_mux_clk.clkr, + [NW_GCC_CAMERA_HF_AXI_CLK] =3D &nw_gcc_camera_hf_axi_clk.clkr, + [NW_GCC_CAMERA_SF_AXI_CLK] =3D &nw_gcc_camera_sf_axi_clk.clkr, + [NW_GCC_CAMERA_TRIG_CLK] =3D &nw_gcc_camera_trig_clk.clkr, + [NW_GCC_DISP_0_HF_AXI_CLK] =3D &nw_gcc_disp_0_hf_axi_clk.clkr, + [NW_GCC_DISP_0_TRIG_CLK] =3D &nw_gcc_disp_0_trig_clk.clkr, + [NW_GCC_DISP_1_HF_AXI_CLK] =3D &nw_gcc_disp_1_hf_axi_clk.clkr, + [NW_GCC_DISP_1_TRIG_CLK] =3D &nw_gcc_disp_1_trig_clk.clkr, + [NW_GCC_DPRX0_AXI_HF_CLK] =3D &nw_gcc_dprx0_axi_hf_clk.clkr, + [NW_GCC_DPRX1_AXI_HF_CLK] =3D &nw_gcc_dprx1_axi_hf_clk.clkr, + [NW_GCC_EVA_AXI0_CLK] =3D &nw_gcc_eva_axi0_clk.clkr, + [NW_GCC_EVA_AXI0C_CLK] =3D &nw_gcc_eva_axi0c_clk.clkr, + [NW_GCC_EVA_TRIG_CLK] =3D &nw_gcc_eva_trig_clk.clkr, + [NW_GCC_FRQ_MEASURE_REF_CLK] =3D &nw_gcc_frq_measure_ref_clk.clkr, + [NW_GCC_GP1_CLK] =3D &nw_gcc_gp1_clk.clkr, + [NW_GCC_GP1_CLK_SRC] =3D &nw_gcc_gp1_clk_src.clkr, + [NW_GCC_GP2_CLK] =3D &nw_gcc_gp2_clk.clkr, + [NW_GCC_GP2_CLK_SRC] =3D &nw_gcc_gp2_clk_src.clkr, + [NW_GCC_GPLL0] =3D &nw_gcc_gpll0.clkr, + [NW_GCC_GPLL0_OUT_EVEN] =3D &nw_gcc_gpll0_out_even.clkr, + [NW_GCC_GPU_2_GPLL0_CLK_SRC] =3D &nw_gcc_gpu_2_gpll0_clk_src.clkr, + [NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC] =3D &nw_gcc_gpu_2_gpll0_div_clk_src.clkr, + [NW_GCC_GPU_2_HSCNOC_GFX_CLK] =3D &nw_gcc_gpu_2_hscnoc_gfx_clk.clkr, + [NW_GCC_GPU_GPLL0_CLK_SRC] =3D &nw_gcc_gpu_gpll0_clk_src.clkr, + [NW_GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &nw_gcc_gpu_gpll0_div_clk_src.clkr, + [NW_GCC_GPU_HSCNOC_GFX_CLK] =3D &nw_gcc_gpu_hscnoc_gfx_clk.clkr, + [NW_GCC_GPU_SMMU_VOTE_CLK] =3D &nw_gcc_gpu_smmu_vote_clk.clkr, + [NW_GCC_HSCNOC_GPU_2_AXI_CLK] =3D &nw_gcc_hscnoc_gpu_2_axi_clk.clkr, + [NW_GCC_HSCNOC_GPU_AXI_CLK] =3D &nw_gcc_hscnoc_gpu_axi_clk.clkr, + [NW_GCC_MMU_1_TCU_VOTE_CLK] =3D &nw_gcc_mmu_1_tcu_vote_clk.clkr, + [NW_GCC_VIDEO_AXI0_CLK] =3D &nw_gcc_video_axi0_clk.clkr, + [NW_GCC_VIDEO_AXI0C_CLK] =3D &nw_gcc_video_axi0c_clk.clkr, + [NW_GCC_VIDEO_AXI1_CLK] =3D &nw_gcc_video_axi1_clk.clkr, +}; + +static const struct qcom_reset_map nw_gcc_nord_resets[] =3D { + [NW_GCC_CAMERA_BCR] =3D { 0x16000 }, + [NW_GCC_DISPLAY_0_BCR] =3D { 0x18000 }, + [NW_GCC_DISPLAY_1_BCR] =3D { 0x19000 }, + [NW_GCC_DPRX0_BCR] =3D { 0x29000 }, + [NW_GCC_DPRX1_BCR] =3D { 0x2a000 }, + [NW_GCC_EVA_BCR] =3D { 0x1b000 }, + [NW_GCC_GPU_2_BCR] =3D { 0x24000 }, + [NW_GCC_GPU_BCR] =3D { 0x23000 }, + [NW_GCC_VIDEO_BCR] =3D { 0x1a000 }, +}; + +static u32 nw_gcc_nord_critical_cbcrs[] =3D { + 0x16004, /* NW_GCC_CAMERA_AHB_CLK */ + 0x16030, /* NW_GCC_CAMERA_XO_CLK */ + 0x18004, /* NW_GCC_DISP_0_AHB_CLK */ + 0x19004, /* NW_GCC_DISP_1_AHB_CLK */ + 0x29018, /* NW_GCC_DPRX0_CFG_AHB_CLK */ + 0x2a018, /* NW_GCC_DPRX1_CFG_AHB_CLK */ + 0x1b004, /* NW_GCC_EVA_AHB_CLK */ + 0x1b024, /* NW_GCC_EVA_XO_CLK */ + 0x23004, /* NW_GCC_GPU_CFG_AHB_CLK */ + 0x24004, /* NW_GCC_GPU_2_CFG_AHB_CLK */ + 0x1a004, /* NW_GCC_VIDEO_AHB_CLK */ + 0x1a044, /* NW_GCC_VIDEO_XO_CLK */ +}; + +static struct qcom_cc_driver_data nw_gcc_nord_driver_data =3D { + .clk_cbcrs =3D nw_gcc_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(nw_gcc_nord_critical_cbcrs), +}; + +static const struct regmap_config nw_gcc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf41f0, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc nw_gcc_nord_desc =3D { + .config =3D &nw_gcc_nord_regmap_config, + .clks =3D nw_gcc_nord_clocks, + .num_clks =3D ARRAY_SIZE(nw_gcc_nord_clocks), + .resets =3D nw_gcc_nord_resets, + .num_resets =3D ARRAY_SIZE(nw_gcc_nord_resets), + .driver_data =3D &nw_gcc_nord_driver_data, +}; + +static const struct of_device_id nw_gcc_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-nwgcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nw_gcc_nord_match_table); + +static int nw_gcc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &nw_gcc_nord_desc); +} + +static struct platform_driver nw_gcc_nord_driver =3D { + .probe =3D nw_gcc_nord_probe, + .driver =3D { + .name =3D "nwgcc-nord", + .of_match_table =3D nw_gcc_nord_match_table, + }, +}; + +module_platform_driver(nw_gcc_nord_driver); + +MODULE_DESCRIPTION("QTI NWGCC NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..1aab0999de4dde7262bd694f7d7= f955b2a9cb66e --- /dev/null +++ b/drivers/clk/qcom/segcc-nord.c @@ -0,0 +1,1609 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SE_GCC_GPLL0_OUT_EVEN, + P_SE_GCC_GPLL0_OUT_MAIN, + P_SE_GCC_GPLL2_OUT_MAIN, + P_SE_GCC_GPLL4_OUT_MAIN, + P_SE_GCC_GPLL5_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll se_gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_se_gcc_gpll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv se_gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_se_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_se_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll se_gcc_gpll2 =3D { + .offset =3D 0x2000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gpll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll se_gcc_gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll se_gcc_gpll5 =3D { + .offset =3D 0x5000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gpll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map se_gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SE_GCC_GPLL0_OUT_EVEN, 2 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &se_gcc_gpll0.clkr.hw }, + { .hw =3D &se_gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map se_gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &se_gcc_gpll0.clkr.hw }, +}; + +static const struct parent_map se_gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &se_gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map se_gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SE_GCC_GPLL5_OUT_MAIN, 3 }, + { P_SE_GCC_GPLL4_OUT_MAIN, 5 }, + { P_SE_GCC_GPLL2_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &se_gcc_gpll0.clkr.hw }, + { .hw =3D &se_gcc_gpll5.clkr.hw }, + { .hw =3D &se_gcc_gpll4.clkr.hw }, + { .hw =3D &se_gcc_gpll2.clkr.hw }, +}; + +static const struct parent_map se_gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SE_GCC_GPLL0_OUT_EVEN, 2 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data se_gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &se_gcc_gpll0.clkr.hw }, + { .hw =3D &se_gcc_gpll0_out_even.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_se_gcc_eee_emac0_clk_src[] =3D { + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_eee_emac0_clk_src =3D { + .cmd_rcgr =3D 0x240b8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_2, + .freq_tbl =3D ftbl_se_gcc_eee_emac0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_eee_emac0_clk_src", + .parent_data =3D se_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_eee_emac1_clk_src =3D { + .cmd_rcgr =3D 0x250b8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_2, + .freq_tbl =3D ftbl_se_gcc_eee_emac0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_eee_emac1_clk_src", + .parent_data =3D se_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_emac0_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_emac0_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x24030, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_2, + .freq_tbl =3D ftbl_se_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_phy_aux_clk_src", + .parent_data =3D se_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_emac0_ptp_clk_src[] =3D { + F(150000000, P_SE_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_emac0_ptp_clk_src =3D { + .cmd_rcgr =3D 0x24084, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_3, + .freq_tbl =3D ftbl_se_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_ptp_clk_src", + .parent_data =3D se_gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_emac0_rgmii_clk_src[] =3D { + F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_emac0_rgmii_clk_src =3D { + .cmd_rcgr =3D 0x2406c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_3, + .freq_tbl =3D ftbl_se_gcc_emac0_rgmii_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_rgmii_clk_src", + .parent_data =3D se_gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_emac1_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x25030, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_2, + .freq_tbl =3D ftbl_se_gcc_emac0_phy_aux_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_phy_aux_clk_src", + .parent_data =3D se_gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_emac1_ptp_clk_src =3D { + .cmd_rcgr =3D 0x25084, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_3, + .freq_tbl =3D ftbl_se_gcc_emac0_ptp_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_ptp_clk_src", + .parent_data =3D se_gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_emac1_rgmii_clk_src =3D { + .cmd_rcgr =3D 0x2506c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_3, + .freq_tbl =3D ftbl_se_gcc_emac0_rgmii_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_rgmii_clk_src", + .parent_data =3D se_gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_gp1_clk_src[] =3D { + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_SE_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 se_gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x19004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_4, + .freq_tbl =3D ftbl_se_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gp1_clk_src", + .parent_data =3D se_gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 se_gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x1a004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_4, + .freq_tbl =3D ftbl_se_gcc_gp1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gp2_clk_src", + .parent_data =3D se_gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 64, 375), + F(112000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 14, 75), + F(117964800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625), + F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x2616c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x262a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s2_clk_src[] =3D { + F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625), + F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75), + F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25), + F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375), + F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75), + F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), + F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0), + F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15), + F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25), + F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x263e4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x26520, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x2665c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x26798, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap0_s6_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap0_s6_clk_src", + .parent_data =3D se_gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap0_s6_clk_src =3D { + .cmd_rcgr =3D 0x268d4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_1, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x2716c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x272a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x273e4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x27520, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x2765c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x27798, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data se_gcc_qupv3_wrap1_s6_clk_src_init =3D { + .name =3D "se_gcc_qupv3_wrap1_s6_clk_src", + .parent_data =3D se_gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(se_gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_no_init_park_ops, +}; + +static struct clk_rcg2 se_gcc_qupv3_wrap1_s6_clk_src =3D { + .cmd_rcgr =3D 0x278d4, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D se_gcc_parent_map_0, + .freq_tbl =3D ftbl_se_gcc_qupv3_wrap0_s2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &se_gcc_qupv3_wrap1_s6_clk_src_init, +}; + +static struct clk_branch se_gcc_eee_emac0_clk =3D { + .halt_reg =3D 0x240b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x240b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_eee_emac0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_eee_emac0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_eee_emac1_clk =3D { + .halt_reg =3D 0x250b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x250b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_eee_emac1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_eee_emac1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_axi_clk =3D { + .halt_reg =3D 0x2401c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2401c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_cc_sgmiiphy_rx_clk =3D { + .halt_reg =3D 0x24064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x24064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_cc_sgmiiphy_rx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk =3D { + .halt_reg =3D 0x2405c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2405c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_cc_sgmiiphy_tx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_phy_aux_clk =3D { + .halt_reg =3D 0x2402c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2402c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_ptp_clk =3D { + .halt_reg =3D 0x24048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x24048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_rgmii_clk =3D { + .halt_reg =3D 0x24058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x24058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_rpcs_rx_clk =3D { + .halt_reg =3D 0x240a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x240a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_rpcs_rx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_rpcs_tx_clk =3D { + .halt_reg =3D 0x240a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x240a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_rpcs_tx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_xgxs_rx_clk =3D { + .halt_reg =3D 0x240b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x240b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_xgxs_rx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac0_xgxs_tx_clk =3D { + .halt_reg =3D 0x240ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x240ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac0_xgxs_tx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_axi_clk =3D { + .halt_reg =3D 0x2501c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2501c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_cc_sgmiiphy_rx_clk =3D { + .halt_reg =3D 0x25064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_cc_sgmiiphy_rx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk =3D { + .halt_reg =3D 0x2505c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2505c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_cc_sgmiiphy_tx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_phy_aux_clk =3D { + .halt_reg =3D 0x2502c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2502c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_emac1_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_ptp_clk =3D { + .halt_reg =3D 0x25048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_emac1_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_rgmii_clk =3D { + .halt_reg =3D 0x25058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_emac1_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_rpcs_rx_clk =3D { + .halt_reg =3D 0x250a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x250a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_rpcs_rx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_rpcs_tx_clk =3D { + .halt_reg =3D 0x250a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x250a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_rpcs_tx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_xgxs_rx_clk =3D { + .halt_reg =3D 0x250b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x250b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_xgxs_rx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_emac1_xgxs_tx_clk =3D { + .halt_reg =3D 0x250ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x250ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_emac1_xgxs_tx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_frq_measure_ref_clk =3D { + .halt_reg =3D 0x18008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x18008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_frq_measure_ref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_gp1_clk =3D { + .halt_reg =3D 0x19000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x19000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_gp2_clk =3D { + .halt_reg =3D 0x1a000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1a000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_mmu_2_tcu_vote_clk =3D { + .halt_reg =3D 0x57040, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_mmu_2_tcu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x26020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x2600c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_m_ahb_clk =3D { + .halt_reg =3D 0x26004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x26004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x2615c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x26298, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x263d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x26510, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x2664c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x26788, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s6_clk =3D { + .halt_reg =3D 0x268c4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap0_s_ahb_clk =3D { + .halt_reg =3D 0x26008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x26008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x27020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x2700c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_m_ahb_clk =3D { + .halt_reg =3D 0x27004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x2715c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x27298, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x273d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x27510, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x2764c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x27788, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s6_clk =3D { + .halt_reg =3D 0x278c4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x57008, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &se_gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch se_gcc_qupv3_wrap1_s_ahb_clk =3D { + .halt_reg =3D 0x27008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x57000, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "se_gcc_qupv3_wrap1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc se_gcc_emac0_gdsc =3D { + .gdscr =3D 0x24004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "se_gcc_emac0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc se_gcc_emac1_gdsc =3D { + .gdscr =3D 0x25004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "se_gcc_emac1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *se_gcc_nord_clocks[] =3D { + [SE_GCC_EEE_EMAC0_CLK] =3D &se_gcc_eee_emac0_clk.clkr, + [SE_GCC_EEE_EMAC0_CLK_SRC] =3D &se_gcc_eee_emac0_clk_src.clkr, + [SE_GCC_EEE_EMAC1_CLK] =3D &se_gcc_eee_emac1_clk.clkr, + [SE_GCC_EEE_EMAC1_CLK_SRC] =3D &se_gcc_eee_emac1_clk_src.clkr, + [SE_GCC_EMAC0_AXI_CLK] =3D &se_gcc_emac0_axi_clk.clkr, + [SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] =3D &se_gcc_emac0_cc_sgmiiphy_rx_clk.cl= kr, + [SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] =3D &se_gcc_emac0_cc_sgmiiphy_tx_clk.cl= kr, + [SE_GCC_EMAC0_PHY_AUX_CLK] =3D &se_gcc_emac0_phy_aux_clk.clkr, + [SE_GCC_EMAC0_PHY_AUX_CLK_SRC] =3D &se_gcc_emac0_phy_aux_clk_src.clkr, + [SE_GCC_EMAC0_PTP_CLK] =3D &se_gcc_emac0_ptp_clk.clkr, + [SE_GCC_EMAC0_PTP_CLK_SRC] =3D &se_gcc_emac0_ptp_clk_src.clkr, + [SE_GCC_EMAC0_RGMII_CLK] =3D &se_gcc_emac0_rgmii_clk.clkr, + [SE_GCC_EMAC0_RGMII_CLK_SRC] =3D &se_gcc_emac0_rgmii_clk_src.clkr, + [SE_GCC_EMAC0_RPCS_RX_CLK] =3D &se_gcc_emac0_rpcs_rx_clk.clkr, + [SE_GCC_EMAC0_RPCS_TX_CLK] =3D &se_gcc_emac0_rpcs_tx_clk.clkr, + [SE_GCC_EMAC0_XGXS_RX_CLK] =3D &se_gcc_emac0_xgxs_rx_clk.clkr, + [SE_GCC_EMAC0_XGXS_TX_CLK] =3D &se_gcc_emac0_xgxs_tx_clk.clkr, + [SE_GCC_EMAC1_AXI_CLK] =3D &se_gcc_emac1_axi_clk.clkr, + [SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] =3D &se_gcc_emac1_cc_sgmiiphy_rx_clk.cl= kr, + [SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] =3D &se_gcc_emac1_cc_sgmiiphy_tx_clk.cl= kr, + [SE_GCC_EMAC1_PHY_AUX_CLK] =3D &se_gcc_emac1_phy_aux_clk.clkr, + [SE_GCC_EMAC1_PHY_AUX_CLK_SRC] =3D &se_gcc_emac1_phy_aux_clk_src.clkr, + [SE_GCC_EMAC1_PTP_CLK] =3D &se_gcc_emac1_ptp_clk.clkr, + [SE_GCC_EMAC1_PTP_CLK_SRC] =3D &se_gcc_emac1_ptp_clk_src.clkr, + [SE_GCC_EMAC1_RGMII_CLK] =3D &se_gcc_emac1_rgmii_clk.clkr, + [SE_GCC_EMAC1_RGMII_CLK_SRC] =3D &se_gcc_emac1_rgmii_clk_src.clkr, + [SE_GCC_EMAC1_RPCS_RX_CLK] =3D &se_gcc_emac1_rpcs_rx_clk.clkr, + [SE_GCC_EMAC1_RPCS_TX_CLK] =3D &se_gcc_emac1_rpcs_tx_clk.clkr, + [SE_GCC_EMAC1_XGXS_RX_CLK] =3D &se_gcc_emac1_xgxs_rx_clk.clkr, + [SE_GCC_EMAC1_XGXS_TX_CLK] =3D &se_gcc_emac1_xgxs_tx_clk.clkr, + [SE_GCC_FRQ_MEASURE_REF_CLK] =3D &se_gcc_frq_measure_ref_clk.clkr, + [SE_GCC_GP1_CLK] =3D &se_gcc_gp1_clk.clkr, + [SE_GCC_GP1_CLK_SRC] =3D &se_gcc_gp1_clk_src.clkr, + [SE_GCC_GP2_CLK] =3D &se_gcc_gp2_clk.clkr, + [SE_GCC_GP2_CLK_SRC] =3D &se_gcc_gp2_clk_src.clkr, + [SE_GCC_GPLL0] =3D &se_gcc_gpll0.clkr, + [SE_GCC_GPLL0_OUT_EVEN] =3D &se_gcc_gpll0_out_even.clkr, + [SE_GCC_GPLL2] =3D &se_gcc_gpll2.clkr, + [SE_GCC_GPLL4] =3D &se_gcc_gpll4.clkr, + [SE_GCC_GPLL5] =3D &se_gcc_gpll5.clkr, + [SE_GCC_MMU_2_TCU_VOTE_CLK] =3D &se_gcc_mmu_2_tcu_vote_clk.clkr, + [SE_GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &se_gcc_qupv3_wrap0_core_2x_clk.clkr, + [SE_GCC_QUPV3_WRAP0_CORE_CLK] =3D &se_gcc_qupv3_wrap0_core_clk.clkr, + [SE_GCC_QUPV3_WRAP0_M_AHB_CLK] =3D &se_gcc_qupv3_wrap0_m_ahb_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S0_CLK] =3D &se_gcc_qupv3_wrap0_s0_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s0_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S1_CLK] =3D &se_gcc_qupv3_wrap0_s1_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s1_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S2_CLK] =3D &se_gcc_qupv3_wrap0_s2_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s2_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S3_CLK] =3D &se_gcc_qupv3_wrap0_s3_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s3_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S4_CLK] =3D &se_gcc_qupv3_wrap0_s4_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s4_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S5_CLK] =3D &se_gcc_qupv3_wrap0_s5_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s5_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S6_CLK] =3D &se_gcc_qupv3_wrap0_s6_clk.clkr, + [SE_GCC_QUPV3_WRAP0_S6_CLK_SRC] =3D &se_gcc_qupv3_wrap0_s6_clk_src.clkr, + [SE_GCC_QUPV3_WRAP0_S_AHB_CLK] =3D &se_gcc_qupv3_wrap0_s_ahb_clk.clkr, + [SE_GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &se_gcc_qupv3_wrap1_core_2x_clk.clkr, + [SE_GCC_QUPV3_WRAP1_CORE_CLK] =3D &se_gcc_qupv3_wrap1_core_clk.clkr, + [SE_GCC_QUPV3_WRAP1_M_AHB_CLK] =3D &se_gcc_qupv3_wrap1_m_ahb_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S0_CLK] =3D &se_gcc_qupv3_wrap1_s0_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s0_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S1_CLK] =3D &se_gcc_qupv3_wrap1_s1_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s1_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S2_CLK] =3D &se_gcc_qupv3_wrap1_s2_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s2_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S3_CLK] =3D &se_gcc_qupv3_wrap1_s3_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s3_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S4_CLK] =3D &se_gcc_qupv3_wrap1_s4_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s4_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S5_CLK] =3D &se_gcc_qupv3_wrap1_s5_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s5_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S6_CLK] =3D &se_gcc_qupv3_wrap1_s6_clk.clkr, + [SE_GCC_QUPV3_WRAP1_S6_CLK_SRC] =3D &se_gcc_qupv3_wrap1_s6_clk_src.clkr, + [SE_GCC_QUPV3_WRAP1_S_AHB_CLK] =3D &se_gcc_qupv3_wrap1_s_ahb_clk.clkr, +}; + +static struct gdsc *se_gcc_nord_gdscs[] =3D { + [SE_GCC_EMAC0_GDSC] =3D &se_gcc_emac0_gdsc, + [SE_GCC_EMAC1_GDSC] =3D &se_gcc_emac1_gdsc, +}; + +static const struct qcom_reset_map se_gcc_nord_resets[] =3D { + [SE_GCC_EMAC0_BCR] =3D { 0x24000 }, + [SE_GCC_EMAC1_BCR] =3D { 0x25000 }, + [SE_GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x26000 }, + [SE_GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x27000 }, +}; + +static const struct clk_rcg_dfs_data se_gcc_nord_dfs_clocks[] =3D { + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s6_clk_src), +}; + +static const struct regmap_config se_gcc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf41f0, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data se_gcc_nord_driver_data =3D { + .dfs_rcgs =3D se_gcc_nord_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(se_gcc_nord_dfs_clocks), +}; + +static const struct qcom_cc_desc se_gcc_nord_desc =3D { + .config =3D &se_gcc_nord_regmap_config, + .clks =3D se_gcc_nord_clocks, + .num_clks =3D ARRAY_SIZE(se_gcc_nord_clocks), + .resets =3D se_gcc_nord_resets, + .num_resets =3D ARRAY_SIZE(se_gcc_nord_resets), + .gdscs =3D se_gcc_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(se_gcc_nord_gdscs), + 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Message-Id: <20260403-nord-clks-v1-7-018af14979fd@oss.qualcomm.com> References: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com> In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Taniya Das , Richard Cochran , Shawn Guo , Deepti Jaggi Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=770; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=pGXUSvvrPCaY9bNA8U6IJfdUVXNbpB60+57XVCPk97s=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBpz8qB9rA6oEtfhw5E1F2I9M0SZW4hSH9QHKa8+ OOr9TGSwh2JAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCac/KgQAKCRAFnS7L/zaE w+lAD/sGSyzHSiDLl10lrRqWadTn4ar0xcomvKgXlKXHrjSyctiLQH7te2z7srmzG3lfa1h5s0B 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Signed-off-by: Bartosz Golaszewski --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 163b7f0314c90fc45eb6c4aa5e8faa549c60fdf7..f1a3333bb07482ef4f8b4ea9154= b0f2c74587a04 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1483,6 +1483,8 @@ CONFIG_CLK_KAANAPALI_GCC=3Dy CONFIG_CLK_KAANAPALI_GPUCC=3Dm CONFIG_CLK_KAANAPALI_TCSRCC=3Dm CONFIG_CLK_KAANAPALI_VIDEOCC=3Dm +CONFIG_CLK_NORD_GCC=3Dy +CONFIG_CLK_NORD_TCSRCC=3Dy CONFIG_CLK_X1E80100_CAMCC=3Dm CONFIG_CLK_X1E80100_DISPCC=3Dm CONFIG_CLK_X1E80100_GCC=3Dy --=20 2.47.3