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[2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3ca9a145sm213492566b.25.2026.04.03.09.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 09:44:04 -0700 (PDT) From: Luca Weiss Date: Fri, 03 Apr 2026 18:43:50 +0200 Subject: [PATCH 4/6] net: ipa: add IPA v5.2 configuration data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260403-milos-ipa-v1-4-01e9e4e03d3e@fairphone.com> References: <20260403-milos-ipa-v1-0-01e9e4e03d3e@fairphone.com> In-Reply-To: <20260403-milos-ipa-v1-0-01e9e4e03d3e@fairphone.com> To: Alex Elder , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775234639; l=15389; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=jUo7g6I6p1JHRet0ueHk1c8pIkO2J9jMZW92HH837/g=; b=FFV557m6AuzXzr7rZcZPUpu6eFseOqmjavF2MzNSYrIvBbIFl1EDhWxwMFEJ8Yf1rL0hk93Or hCbkN2iIGXDCmgefKfNZH9TcWhFG0l4wH++5hpdN2yWYR6hKMI3S6Ko X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the configuration data required for IPA v5.2, which is used in the Qualcomm Milos SoC. Signed-off-by: Luca Weiss --- drivers/net/ipa/Makefile | 2 +- drivers/net/ipa/data/ipa_data-v5.2.c | 452 +++++++++++++++++++++++++++++++= ++++ drivers/net/ipa/gsi_reg.c | 1 + drivers/net/ipa/ipa_data.h | 1 + drivers/net/ipa/ipa_main.c | 4 + drivers/net/ipa/ipa_reg.c | 1 + drivers/net/ipa/ipa_sysfs.c | 2 + drivers/net/ipa/ipa_version.h | 2 + 8 files changed, 464 insertions(+), 1 deletion(-) diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile index d3abb38633e0..e148ec3c1a10 100644 --- a/drivers/net/ipa/Makefile +++ b/drivers/net/ipa/Makefile @@ -7,7 +7,7 @@ IPA_REG_VERSIONS :=3D 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5 # Some IPA versions can reuse another set of GSI register definitions. GSI_REG_VERSIONS :=3D 3.1 3.5.1 4.0 4.5 4.9 4.11 5.0 =20 -IPA_DATA_VERSIONS :=3D 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5 +IPA_DATA_VERSIONS :=3D 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.2 5.5 =20 obj-$(CONFIG_QCOM_IPA) +=3D ipa.o =20 diff --git a/drivers/net/ipa/data/ipa_data-v5.2.c b/drivers/net/ipa/data/ip= a_data-v5.2.c new file mode 100644 index 000000000000..c56c4f1836ae --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v5.2.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023-2024 Linaro Ltd. + * Copyright (c) 2026, Luca Weiss + */ + +#include +#include + +#include "../ipa_data.h" +#include "../ipa_endpoint.h" +#include "../ipa_mem.h" +#include "../ipa_version.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.2= */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS =3D 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS =3D 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, + IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS, +}; + +/* Resource groups used for an SoC having IPA v5.2 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL =3D 0, + IPA_RSRC_GROUP_SRC_DL, + IPA_RSRC_GROUP_SRC_URLLC, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL =3D 0, + IPA_RSRC_GROUP_DST_DL, + IPA_RSRC_GROUP_DST_UNUSED_1, + IPA_RSRC_GROUP_DST_DRB_IP, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v5.2 */ +static const struct ipa_qsb_data ipa_qsb_data[] =3D { + [IPA_QSB_MASTER_DDR] =3D { + .max_writes =3D 13, + .max_reads =3D 13, + .max_reads_beats =3D 0, + }, +}; + +/* Endpoint configuration data for an SoC having IPA v5.2 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] =3D { + [IPA_ENDPOINT_AP_COMMAND_TX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 6, + .endpoint_id =3D 9, + .toward_ipa =3D true, + .channel =3D { + .tre_count =3D 256, + .event_count =3D 256, + .tlv_count =3D 20, + }, + .endpoint =3D { + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_SRC_UL, + .dma_mode =3D true, + .dma_endpoint =3D IPA_ENDPOINT_AP_LAN_RX, + .tx =3D { + .seq_type =3D IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 7, + .endpoint_id =3D 11, + .toward_ipa =3D false, + .channel =3D { + .tre_count =3D 256, + .event_count =3D 256, + .tlv_count =3D 9, + }, + .endpoint =3D { + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_DST_UL, + .aggregation =3D true, + .status_enable =3D true, + .rx =3D { + .buffer_size =3D 8192, + .pad_align =3D ilog2(sizeof(u32)), + .aggr_time_limit =3D 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 5, + .endpoint_id =3D 2, + .toward_ipa =3D true, + .channel =3D { + .tre_count =3D 512, + .event_count =3D 512, + .tlv_count =3D 25, + }, + .endpoint =3D { + .filter_support =3D true, + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_SRC_UL, + .checksum =3D true, + .qmap =3D true, + .status_enable =3D true, + .tx =3D { + .seq_type =3D IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint =3D + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] =3D { + .ee_id =3D GSI_EE_AP, + .channel_id =3D 9, + .endpoint_id =3D 18, + .toward_ipa =3D false, + .channel =3D { + .tre_count =3D 256, + .event_count =3D 256, + .tlv_count =3D 9, + }, + .endpoint =3D { + .config =3D { + .resource_group =3D IPA_RSRC_GROUP_DST_DL, + .checksum =3D true, + .qmap =3D true, + .aggregation =3D true, + .rx =3D { + .buffer_size =3D 8192, + .aggr_time_limit =3D 500, + .aggr_close_eof =3D true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] =3D { + .ee_id =3D GSI_EE_MODEM, + .channel_id =3D 0, + .endpoint_id =3D 7, + .toward_ipa =3D true, + .endpoint =3D { + .filter_support =3D true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] =3D { + .ee_id =3D GSI_EE_MODEM, + .channel_id =3D 7, + .endpoint_id =3D 16, + .toward_ipa =3D false, + }, + [IPA_ENDPOINT_MODEM_DL_NLO_TX] =3D { + .ee_id =3D GSI_EE_MODEM, + .channel_id =3D 2, + .endpoint_id =3D 10, + .toward_ipa =3D true, + .endpoint =3D { + .filter_support =3D true, + }, + }, +}; + +/* Source resource configuration data for an SoC having IPA v5.2 */ +static const struct ipa_resource ipa_resource_src[] =3D { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 1, .max =3D 7, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] =3D { + .min =3D 1, .max =3D 7, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 0, .max =3D 5, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 8, .max =3D 8, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] =3D { + .min =3D 8, .max =3D 8, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 8, .max =3D 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 10, .max =3D 10, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] =3D { + .min =3D 12, .max =3D 12, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 12, .max =3D 12, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 0, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] =3D { + .min =3D 0, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 0, .max =3D 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] =3D { + .limits[IPA_RSRC_GROUP_SRC_UL] =3D { + .min =3D 15, .max =3D 15, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] =3D { + .min =3D 15, .max =3D 15, + }, + .limits[IPA_RSRC_GROUP_SRC_URLLC] =3D { + .min =3D 12, .max =3D 12, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v5.2 */ +static const struct ipa_resource ipa_resource_dst[] =3D { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] =3D { + .limits[IPA_RSRC_GROUP_DST_UL] =3D { + .min =3D 3, .max =3D 3, + }, + .limits[IPA_RSRC_GROUP_DST_DL] =3D { + .min =3D 3, .max =3D 3, + }, + .limits[IPA_RSRC_GROUP_DST_DRB_IP] =3D { + .min =3D 23, .max =3D 23, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] =3D { + .limits[IPA_RSRC_GROUP_DST_UL] =3D { + .min =3D 1, .max =3D 2, + }, + .limits[IPA_RSRC_GROUP_DST_DL] =3D { + .min =3D 1, .max =3D 2, + }, + }, + [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] =3D { + .limits[IPA_RSRC_GROUP_DST_UL] =3D { + .min =3D 1, .max =3D 63, + }, + .limits[IPA_RSRC_GROUP_DST_DL] =3D { + .min =3D 1, .max =3D 63, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v5.2 */ +static const struct ipa_resource_data ipa_resource_data =3D { + .rsrc_group_dst_count =3D IPA_RSRC_GROUP_DST_COUNT, + .rsrc_group_src_count =3D IPA_RSRC_GROUP_SRC_COUNT, + .resource_src_count =3D ARRAY_SIZE(ipa_resource_src), + .resource_src =3D ipa_resource_src, + .resource_dst_count =3D ARRAY_SIZE(ipa_resource_dst), + .resource_dst =3D ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v5.2 */ +static const struct ipa_mem ipa_mem_local_data[] =3D { + { + .id =3D IPA_MEM_UC_SHARED, + .offset =3D 0x0000, + .size =3D 0x0080, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_UC_INFO, + .offset =3D 0x0080, + .size =3D 0x0200, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_V4_FILTER_HASHED, + .offset =3D 0x0288, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V4_FILTER, + .offset =3D 0x0308, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_FILTER_HASHED, + .offset =3D 0x0388, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_FILTER, + .offset =3D 0x0408, + .size =3D 0x0078, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V4_ROUTE_HASHED, + .offset =3D 0x0488, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V4_ROUTE, + .offset =3D 0x0528, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_ROUTE_HASHED, + .offset =3D 0x05c8, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_V6_ROUTE, + .offset =3D 0x0668, + .size =3D 0x0098, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_MODEM_HEADER, + .offset =3D 0x0708, + .size =3D 0x0240, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_AP_HEADER, + .offset =3D 0x0948, + .size =3D 0x01e0, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_MODEM_PROC_CTX, + .offset =3D 0x0b40, + .size =3D 0x0b20, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_AP_PROC_CTX, + .offset =3D 0x1660, + .size =3D 0x0200, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_QUOTA_MODEM, + .offset =3D 0x1868, + .size =3D 0x0060, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_STATS_QUOTA_AP, + .offset =3D 0x18c8, + .size =3D 0x0048, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_TETHERING, + .offset =3D 0x1910, + .size =3D 0x03c0, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_FILTER_ROUTE, + .offset =3D 0x1cd0, + .size =3D 0x0ba0, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_STATS_DROP, + .offset =3D 0x2870, + .size =3D 0x0020, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_MODEM, + .offset =3D 0x2898, + .size =3D 0x0d48, + .canary_count =3D 2, + }, + { + .id =3D IPA_MEM_NAT_TABLE, + .offset =3D 0x35e0, + .size =3D 0x0900, + .canary_count =3D 0, + }, + { + .id =3D IPA_MEM_PDN_CONFIG, + .offset =3D 0x3ee8, + .size =3D 0x0100, + .canary_count =3D 2, + }, +}; + +/* Memory configuration data for an SoC having IPA v5.2 */ +static const struct ipa_mem_data ipa_mem_data =3D { + .local_count =3D ARRAY_SIZE(ipa_mem_local_data), + .local =3D ipa_mem_local_data, + .smem_size =3D 0x0000b000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] =3D { + { + .name =3D "memory", + .peak_bandwidth =3D 1300000, /* 1.3 GBps */ + .average_bandwidth =3D 600000, /* 600 MBps */ + }, + /* Average rate is unused for the next interconnect */ + { + .name =3D "config", + .peak_bandwidth =3D 76800, /* 76.8 MBps */ + .average_bandwidth =3D 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v5.2 */ +static const struct ipa_power_data ipa_power_data =3D { + .core_clock_rate =3D 120 * 1000 * 1000, /* Hz */ + .interconnect_count =3D ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data =3D ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v5.2. */ +const struct ipa_data ipa_data_v5_2 =3D { + .version =3D IPA_VERSION_5_2, + .qsb_count =3D ARRAY_SIZE(ipa_qsb_data), + .qsb_data =3D ipa_qsb_data, + .modem_route_count =3D 11, + .endpoint_count =3D ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data =3D ipa_gsi_endpoint_data, + .resource_data =3D &ipa_resource_data, + .mem_data =3D &ipa_mem_data, + .power_data =3D &ipa_power_data, +}; diff --git a/drivers/net/ipa/gsi_reg.c b/drivers/net/ipa/gsi_reg.c index 825598661188..e13cf835a013 100644 --- a/drivers/net/ipa/gsi_reg.c +++ b/drivers/net/ipa/gsi_reg.c @@ -110,6 +110,7 @@ static const struct regs *gsi_regs(struct gsi *gsi) return &gsi_regs_v4_11; =20 case IPA_VERSION_5_0: + case IPA_VERSION_5_2: case IPA_VERSION_5_5: return &gsi_regs_v5_0; =20 diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index f3bdc64cef05..3eb9dc2ce339 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -253,6 +253,7 @@ extern const struct ipa_data ipa_data_v4_7; extern const struct ipa_data ipa_data_v4_9; extern const struct ipa_data ipa_data_v4_11; extern const struct ipa_data ipa_data_v5_0; +extern const struct ipa_data ipa_data_v5_2; extern const struct ipa_data ipa_data_v5_5; =20 #endif /* _IPA_DATA_H_ */ diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index edead9c48d1f..8e2b4bf7b14e 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -669,6 +669,10 @@ static const struct of_device_id ipa_match[] =3D { .compatible =3D "qcom,sdx65-ipa", .data =3D &ipa_data_v5_0, }, + { + .compatible =3D "qcom,milos-ipa", + .data =3D &ipa_data_v5_2, + }, { .compatible =3D "qcom,sm8550-ipa", .data =3D &ipa_data_v5_5, diff --git a/drivers/net/ipa/ipa_reg.c b/drivers/net/ipa/ipa_reg.c index c574f798fdc9..30bd69f4c147 100644 --- a/drivers/net/ipa/ipa_reg.c +++ b/drivers/net/ipa/ipa_reg.c @@ -125,6 +125,7 @@ static const struct regs *ipa_regs(enum ipa_version ver= sion) case IPA_VERSION_4_11: return &ipa_regs_v4_11; case IPA_VERSION_5_0: + case IPA_VERSION_5_2: return &ipa_regs_v5_0; case IPA_VERSION_5_5: return &ipa_regs_v5_5; diff --git a/drivers/net/ipa/ipa_sysfs.c b/drivers/net/ipa/ipa_sysfs.c index a53e9e6f6cdf..8b805a9d49e6 100644 --- a/drivers/net/ipa/ipa_sysfs.c +++ b/drivers/net/ipa/ipa_sysfs.c @@ -39,6 +39,8 @@ static const char *ipa_version_string(struct ipa *ipa) return "5.0"; case IPA_VERSION_5_1: return "5.1"; + case IPA_VERSION_5_2: + return "5.2"; case IPA_VERSION_5_5: return "5.5"; default: diff --git a/drivers/net/ipa/ipa_version.h b/drivers/net/ipa/ipa_version.h index 38c47f51a50c..c157c72a5bad 100644 --- a/drivers/net/ipa/ipa_version.h +++ b/drivers/net/ipa/ipa_version.h @@ -23,6 +23,7 @@ * @IPA_VERSION_4_11: IPA version 4.11/GSI version 2.11 (2.1.1) * @IPA_VERSION_5_0: IPA version 5.0/GSI version 3.0 * @IPA_VERSION_5_1: IPA version 5.1/GSI version 3.0 + * @IPA_VERSION_5_2: IPA version 5.2/GSI version 5.2 * @IPA_VERSION_5_5: IPA version 5.5/GSI version 5.5 * @IPA_VERSION_COUNT: Number of defined IPA versions * @@ -43,6 +44,7 @@ enum ipa_version { IPA_VERSION_4_11, IPA_VERSION_5_0, IPA_VERSION_5_1, + IPA_VERSION_5_2, IPA_VERSION_5_5, IPA_VERSION_COUNT, /* Last; not a version */ }; --=20 2.53.0