From nobody Sun Jun 14 14:30:11 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CD65384252; Fri, 3 Apr 2026 10:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775213455; cv=none; b=E7A1JPaRxRuTx9cLLMyiG0R0QUyYeAOTGRyPFfiVlcisJnln4rXclJBygKgIHlVSyxjQbocU1mqTeY6IGnWc4jk1wi1lKTak7R9Ocss8BWnRbpaF7ru5gSaPiqR4n1RnKLTAp21ID1LEM3hcBnqidqCSV9lfRO5aSCwAbHtsGLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775213455; c=relaxed/simple; bh=AiH/SG3mloiWc2yGy2juFYW+0HI26Ye9sN7thg3x+6U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pG7FluPfAnL3EzCo7L2L9VhmAEHs+e534Xu9/ZMWXVOj/U5BX3R3/aVzzAIwu2piQuthCWBy9RNW/tRoszNnVG6EDCIxsA3KJAq/LCjusWQ8d7fTIA92rMFqENGTBCxETj9LA1V3m+ihA5/5MTtU/FeTJ5JL+xfHD/ZK2h833yA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=H7dWNaq4; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="H7dWNaq4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1775213452; x=1806749452; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=AiH/SG3mloiWc2yGy2juFYW+0HI26Ye9sN7thg3x+6U=; b=H7dWNaq47aAE/tzRBANP2xLsXPw1aUjhJCxeiOuRV1PdcGL6p2TlhkzX /16nVTOGOv/Y9RB0/0D4RZjLJmO1f6mAK0A6VGBlUzdTWZiFPPq6LmWdj MOk0abWheQfnaY8glDpjIxxciR8KOhagpo6J38D+HgM6+1s3NWD+Nrivl S5vhBkD0xVCO+kIRbI55Yf3YspG28VVECBpT8s4m+dA19muv1ZbdeTWgI QkUHeyjMarDcvq6CxDgsN1iIWDgw29KyzmPEMD9SnGjsG5rjuLIAoHnFl dFS944itS8Mwyi48If8U13NyXvUIeqacz/QycOMZ2493jVcS6IYCIbIvT Q==; X-CSE-ConnectionGUID: sRw3xtFbQm2lIneyrptZQg== X-CSE-MsgGUID: H8r/TftiSQmvnxzAJjvtng== X-IronPort-AV: E=Sophos;i="6.23,157,1770620400"; d="scan'208";a="63451604" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2026 03:50:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Fri, 3 Apr 2026 03:50:22 -0700 Received: from [127.0.1.1] (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 3 Apr 2026 03:50:20 -0700 From: Ariana Lazar Date: Fri, 3 Apr 2026 13:50:13 +0300 Subject: [PATCH 1/2] dt-bindings: iio: dac: add support for Microchip MCP48FEB02 to MCP47FEB02 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260403-mcp47feb02-fix2-v1-1-da60c773550e@microchip.com> References: <20260403-mcp47feb02-fix2-v1-0-da60c773550e@microchip.com> In-Reply-To: <20260403-mcp47feb02-fix2-v1-0-da60c773550e@microchip.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Jonathan Cameron , Conor Dooley , , , , Ariana Lazar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775213414; l=20442; i=ariana.lazar@microchip.com; s=20250825; h=from:subject:message-id; bh=AiH/SG3mloiWc2yGy2juFYW+0HI26Ye9sN7thg3x+6U=; b=WoR9MkKYZkjfBEgh2Sx+tk1Vb97C+DHLbjZKZqI8gS4guuOnyckx//YrREQs2igRyNRWP9U+r 4nsA+aj2A+VDdEoiot5BYmoOtgxb+uVTzjm2u3RXXRLlqLl83XtmIly X-Developer-Key: i=ariana.lazar@microchip.com; a=ed25519; pk=jmvf1fSxcnzZmXfITM3L94IwutM+wqA1POQHiYyD6Dk= This is the device tree schema for iio driver for Microchip MCP48FxBy1/2/4/8 series of buffered voltage output Digital-to-Analog Converters with nonvolatile or volatile memory on top of MCP47FEB02. The families support up to 8 output channels and have 8-bit, 10-bit or 12-bit resolution. The I2C (MCP47F(E/V)BXX) and SPI (MCP48F(E/V)BXX) DAC families were merged into the same dt-binding file. Fixes: 4ba12d304175 ("dt-bindings: iio: dac: adding support for Microchip M= CP47FEB02") Signed-off-by: Ariana Lazar Link: https://lore.kernel.org/all/20260216-shiny-itunes-00a31d1f4db7@spud/ --- .../bindings/iio/dac/microchip,mcp47feb02.yaml | 291 +++++++++++++++--= ---- MAINTAINERS | 1 - 2 files changed, 217 insertions(+), 75 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02= .yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml index d2466aa6bda2106a8b695347a0edf38462294d03..544755cb6334c311f38d156dcf4= b4e6170c6e62d 100644 --- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml @@ -4,90 +4,151 @@ $id: http://devicetree.org/schemas/iio/dac/microchip,mcp47feb02.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Microchip MCP47F(E/V)B(0/1/2)(1/2/4/8) DAC with I2C Interface Famil= ies +title: Microchip MCP4(7/8)F(E/V)B(0/1/2)(1/2/4/8) DAC with I2C/SPI Interfa= ce Families =20 maintainers: - Ariana Lazar =20 description: | - Datasheet for MCP47FEB01, MCP47FEB11, MCP47FEB21, MCP47FEB02, MCP47FEB12, - MCP47FEB22 can be found here: - https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/Product= Documents/DataSheets/20005375A.pdf - Datasheet for MCP47FVB01, MCP47FVB11, MCP47FVB21, MCP47FVB02, MCP47FVB12, - MCP47FVB22 can be found here: - https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/Product= Documents/DataSheets/20005405A.pdf - Datasheet for MCP47FEB04, MCP47FEB14, MCP47FEB24, MCP47FEB08, MCP47FEB18, - MCP47FEB28, MCP47FVB04, MCP47FVB14, MCP47FVB24, MCP47FVB08, MCP47FVB18, - MCP47FVB28 can be found here: - https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Produc= tDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf - - +------------+--------------+-------------+-------------+------------+ - | Device | Resolution | Channels | Vref number | Memory | - |------------|--------------|-------------|-------------|------------| - | MCP47FEB01 | 8-bit | 1 | 1 | EEPROM | - | MCP47FEB11 | 10-bit | 1 | 1 | EEPROM | - | MCP47FEB21 | 12-bit | 1 | 1 | EEPROM | - |------------|--------------|-------------|-------------|------------| - | MCP47FEB02 | 8-bit | 2 | 1 | EEPROM | - | MCP47FEB12 | 10-bit | 2 | 1 | EEPROM | - | MCP47FEB22 | 12-bit | 2 | 1 | EEPROM | - |------------|--------------|-------------|-------------|------------| - | MCP47FVB01 | 8-bit | 1 | 1 | RAM | - | MCP47FVB11 | 10-bit | 1 | 1 | RAM | - | MCP47FVB21 | 12-bit | 1 | 1 | RAM | - |------------|--------------|-------------|-------------|------------| - | MCP47FVB02 | 8-bit | 2 | 1 | RAM | - | MCP47FVB12 | 10-bit | 2 | 1 | RAM | - | MCP47FVB22 | 12-bit | 2 | 1 | RAM | - |------------|--------------|-------------|-------------|------------| - | MCP47FVB04 | 8-bit | 4 | 2 | RAM | - | MCP47FVB14 | 10-bit | 4 | 2 | RAM | - | MCP47FVB24 | 12-bit | 4 | 2 | RAM | - |------------|--------------|-------------|-------------|------------| - | MCP47FVB08 | 8-bit | 8 | 2 | RAM | - | MCP47FVB18 | 10-bit | 8 | 2 | RAM | - | MCP47FVB28 | 12-bit | 8 | 2 | RAM | - |------------|--------------|-------------|-------------|------------| - | MCP47FEB04 | 8-bit | 4 | 2 | EEPROM | - | MCP47FEB14 | 10-bit | 4 | 2 | EEPROM | - | MCP47FEB24 | 12-bit | 4 | 2 | EEPROM | - |------------|--------------|-------------|-------------|------------| - | MCP47FEB08 | 8-bit | 8 | 2 | EEPROM | - | MCP47FEB18 | 10-bit | 8 | 2 | EEPROM | - | MCP47FEB28 | 12-bit | 8 | 2 | EEPROM | - +------------+--------------+-------------+-------------+------------+ + Datasheets for MCP47F(E/V)B(0/1/2)(1/2/4/8) DAC with I2C Interface Famil= ies: + Datasheet for MCP47FEB01, MCP47FEB11, MCP47FEB21, MCP47FEB02, MCP47FEB1= 2, + MCP47FEB22 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/Produc= tDocuments/DataSheets/20005375A.pdf + Datasheet for MCP47FVB01, MCP47FVB11, MCP47FVB21, MCP47FVB02, MCP47FVB1= 2, + MCP47FVB22 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/Produc= tDocuments/DataSheets/20005405A.pdf + Datasheet for MCP47FEB04, MCP47FEB14, MCP47FEB24, MCP47FEB08, MCP47FEB1= 8, + MCP47FEB28, MCP47FVB04, MCP47FVB14, MCP47FVB24, MCP47FVB08, MCP47FVB18, + MCP47FVB28 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Produ= ctDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf + Datasheets for MCP48F(E/V)B(0/1/2)(1/2/4/8) DAC with SPI Interface Fami= lies: + Datasheet for MCP48FEB01, MCP48FEB02, MCP48FEB11, MCP48FEB12, MCP48FEB2= 1, + MCP48FEB22 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/Produc= tDocuments/DataSheets/20005429B.pdf + Datasheet for MCP48FVB01, MCP48FVB02, MCP48FVB11, MCP48FVB12, MCP48FVB2= 1, + MCP48FVB22 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/Produc= tDocuments/DataSheets/20005466A.pdf + Datasheet for MCP48FEB04, MCP48FEB14, MCP48FEB24, MCP48FEB08, MCP48FEB1= 8, + MCP48FEB28, MCP48FVB04, MCP48FVB14, MCP48FVB24, MCP48FVB08, MCP48FVB18, + MCP48FVB28 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Produ= ctDocuments/DataSheets/MCP48FXBX4-8-Family-Data-Sheet-DS20006362A.pdf + + +------------+--------------+-------------+-------------+------------+--= ----------+ + | Device | Resolution | Channels | Vref number | Memory | I= nterface | + |------------|--------------|-------------|-------------|------------|--= ----------| + | MCP47FEB01 | | 1 | 1 | EEPROM | = I2C | + | MCP47FEB02 | | 2 | 1 | EEPROM | = I2C | + | MCP47FEB04 | | 4 | 2 | EEPROM | = I2C | + | MCP47FEB08 | 8-bit | 8 | 2 | EEPROM | = I2C | + | MCP48FEB01 | | 1 | 1 | EEPROM | = SPI | + | MCP48FEB02 | | 2 | 1 | EEPROM | = SPI | + | MCP48FEB04 | | 4 | 2 | EEPROM | = SPI | + | MCP48FEB08 | | 8 | 2 | EEPROM | = SPI | + |------------|--------------|-------------|-------------|------------|--= ----------| + | MCP47FEB11 | | 1 | 1 | EEPROM | = I2C | + | MCP47FEB12 | | 2 | 1 | EEPROM | = I2C | + | MCP47FEB14 | | 4 | 2 | EEPROM | = I2C | + | MCP47FEB18 | 10-bit | 8 | 2 | EEPROM | = I2C | + | MCP48FEB11 | | 1 | 1 | EEPROM | = SPI | + | MCP48FEB12 | | 2 | 1 | EEPROM | = SPI | + | MCP48FEB14 | | 4 | 2 | EEPROM | = SPI | + | MCP48FEB18 | | 8 | 2 | EEPROM | = SPI | + |------------|--------------|-------------|-------------|------------|--= ----------| + | MCP47FEB21 | | 1 | 1 | EEPROM | = I2C | + | MCP47FEB22 | | 2 | 1 | EEPROM | = I2C | + | MCP47FEB24 | | 4 | 2 | EEPROM | = I2C | + | MCP47FEB28 | 12-bit | 8 | 2 | EEPROM | = I2C | + | MCP48FEB21 | | 1 | 1 | EEPROM | = SPI | + | MCP48FEB22 | | 2 | 1 | EEPROM | = SPI | + | MCP48FEB24 | | 4 | 2 | EEPROM | = SPI | + | MCP48FEB28 | | 8 | 2 | EEPROM | = SPI | + |------------|--------------|-------------|-------------|------------|--= ----------| + | MCP47FVB01 | | 1 | 1 | RAM | = I2C | + | MCP47FVB02 | | 2 | 1 | RAM | = I2C | + | MCP47FVB04 | | 4 | 2 | RAM | = I2C | + | MCP47FVB08 | 8-bit | 8 | 2 | RAM | = I2C | + | MCP48FVB01 | | 1 | 1 | RAM | = SPI | + | MCP48FVB02 | | 2 | 1 | RAM | = SPI | + | MCP48FVB04 | | 4 | 2 | RAM | = SPI | + | MCP48FVB08 | | 8 | 2 | RAM | = SPI | + |------------|--------------|-------------|-------------|------------|--= ----------| + | MCP47FVB11 | | 1 | 1 | RAM | = I2C | + | MCP47FVB12 | | 2 | 1 | RAM | = I2C | + | MCP47FVB14 | | 4 | 2 | RAM | = I2C | + | MCP47FVB18 | 10-bit | 8 | 2 | RAM | = I2C | + | MCP48FVB11 | | 1 | 1 | RAM | = SPI | + | MCP48FVB12 | | 2 | 1 | RAM | = SPI | + | MCP48FVB14 | | 4 | 2 | RAM | = SPI | + | MCP48FVB18 | | 8 | 2 | RAM | = SPI | + |------------|--------------|-------------|-------------|------------|--= ----------| + | MCP47FVB21 | | 1 | 1 | RAM | = I2C | + | MCP47FVB22 | | 2 | 1 | RAM | = I2C | + | MCP47FVB24 | | 4 | 2 | RAM | = I2C | + | MCP47FVB28 | 12-bit | 8 | 2 | RAM | = I2C | + | MCP48FVB21 | | 1 | 1 | RAM | = SPI | + | MCP48FVB22 | | 2 | 1 | RAM | = SPI | + | MCP48FVB24 | | 4 | 2 | RAM | = SPI | + | MCP48FVB28 | | 8 | 2 | RAM | = SPI | + +------------+--------------+-------------+-------------+------------+--= ----------+ =20 properties: compatible: enum: - microchip,mcp47feb01 - - microchip,mcp47feb11 - - microchip,mcp47feb21 - microchip,mcp47feb02 + - microchip,mcp47feb04 + - microchip,mcp47feb08 + - microchip,mcp47feb11 - microchip,mcp47feb12 + - microchip,mcp47feb14 + - microchip,mcp47feb18 + - microchip,mcp47feb21 - microchip,mcp47feb22 + - microchip,mcp47feb24 + - microchip,mcp47feb28 - microchip,mcp47fvb01 - - microchip,mcp47fvb11 - - microchip,mcp47fvb21 - microchip,mcp47fvb02 - - microchip,mcp47fvb12 - - microchip,mcp47fvb22 - microchip,mcp47fvb04 - - microchip,mcp47fvb14 - - microchip,mcp47fvb24 - microchip,mcp47fvb08 + - microchip,mcp47fvb11 + - microchip,mcp47fvb12 + - microchip,mcp47fvb14 - microchip,mcp47fvb18 + - microchip,mcp47fvb21 + - microchip,mcp47fvb22 + - microchip,mcp47fvb24 - microchip,mcp47fvb28 - - microchip,mcp47feb04 - - microchip,mcp47feb14 - - microchip,mcp47feb24 - - microchip,mcp47feb08 - - microchip,mcp47feb18 - - microchip,mcp47feb28 + - microchip,mcp48feb01 + - microchip,mcp48feb02 + - microchip,mcp48feb04 + - microchip,mcp48feb08 + - microchip,mcp48feb11 + - microchip,mcp48feb12 + - microchip,mcp48feb14 + - microchip,mcp48feb18 + - microchip,mcp48feb21 + - microchip,mcp48feb22 + - microchip,mcp48feb24 + - microchip,mcp48feb28 + - microchip,mcp48fvb01 + - microchip,mcp48fvb02 + - microchip,mcp48fvb04 + - microchip,mcp48fvb08 + - microchip,mcp48fvb11 + - microchip,mcp48fvb12 + - microchip,mcp48fvb14 + - microchip,mcp48fvb18 + - microchip,mcp48fvb21 + - microchip,mcp48fvb22 + - microchip,mcp48fvb24 + - microchip,mcp48fvb28 =20 reg: maxItems: 1 =20 + spi-max-frequency: + maximum: 10000000 + "#address-cells": const: 1 =20 @@ -111,7 +172,7 @@ properties: - for single-channel device: Vout0; - for dual-channel device: Vout0, Vout1; - for quad-channel device: Vout0, Vout2; - - for octal-channel device: Vout0, Vout2, Vout6, Vout8; + - for octal-channel device: Vout0, Vout2, Vout4, Vout6; =20 vref1-supply: description: | @@ -141,7 +202,7 @@ properties: description: Enable buffering of the external Vref/Vref0 pin in cases where the external reference voltage does not have sufficient current capabili= ty in - order not to drop it=E2=80=99s voltage when connected to the interna= l resistor + order not to drop its voltage when connected to the internal resistor ladder circuit. =20 microchip,vref1-buffered: @@ -149,7 +210,7 @@ properties: description: Enable buffering of the external Vref1 pin in cases where the extern= al reference voltage does not have sufficient current capability in ord= er not - to drop it=E2=80=99s voltage when connected to the internal resistor= ladder + to drop its voltage when connected to the internal resistor ladder circuit. =20 patternProperties: @@ -161,8 +222,7 @@ patternProperties: properties: reg: description: The channel number. - minItems: 1 - maxItems: 8 + maxItems: 1 =20 label: description: Unique name to identify which channel this is. @@ -178,6 +238,13 @@ required: - vdd-supply =20 allOf: + - if: + properties: + compatible: + contains: + pattern: "mcp48" + then: + $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -189,6 +256,12 @@ allOf: - microchip,mcp47fvb01 - microchip,mcp47fvb11 - microchip,mcp47fvb21 + - microchip,mcp48feb01 + - microchip,mcp48feb11 + - microchip,mcp48feb21 + - microchip,mcp48fvb01 + - microchip,mcp48fvb11 + - microchip,mcp48fvb21 then: properties: lat1-gpios: false @@ -211,6 +284,12 @@ allOf: - microchip,mcp47fvb02 - microchip,mcp47fvb12 - microchip,mcp47fvb22 + - microchip,mcp48feb02 + - microchip,mcp48feb12 + - microchip,mcp48feb22 + - microchip,mcp48fvb02 + - microchip,mcp48fvb12 + - microchip,mcp48fvb22 then: properties: lat1-gpios: false @@ -227,12 +306,18 @@ allOf: compatible: contains: enum: - - microchip,mcp47fvb04 - - microchip,mcp47fvb14 - - microchip,mcp47fvb24 - microchip,mcp47feb04 - microchip,mcp47feb14 - microchip,mcp47feb24 + - microchip,mcp47fvb04 + - microchip,mcp47fvb14 + - microchip,mcp47fvb24 + - microchip,mcp48feb04 + - microchip,mcp48feb14 + - microchip,mcp48feb24 + - microchip,mcp48fvb04 + - microchip,mcp48fvb14 + - microchip,mcp48fvb24 then: patternProperties: "^channel@[0-3]$": @@ -245,12 +330,12 @@ allOf: compatible: contains: enum: - - microchip,mcp47fvb08 - - microchip,mcp47fvb18 - - microchip,mcp47fvb28 - microchip,mcp47feb08 - microchip,mcp47feb18 - microchip,mcp47feb28 + - microchip,mcp48fvb08 + - microchip,mcp48fvb18 + - microchip,mcp48fvb28 then: patternProperties: "^channel@[0-7]$": @@ -272,7 +357,40 @@ allOf: properties: microchip,vref1-buffered: false =20 -additionalProperties: false + - if: + properties: + compatible: + contains: + enum: + - microchip,mcp47feb01 + - microchip,mcp47feb02 + - microchip,mcp47feb04 + - microchip,mcp47feb08 + - microchip,mcp47feb11 + - microchip,mcp47feb12 + - microchip,mcp47feb14 + - microchip,mcp47feb18 + - microchip,mcp47feb21 + - microchip,mcp47feb22 + - microchip,mcp47feb24 + - microchip,mcp47feb28 + - microchip,mcp47fvb01 + - microchip,mcp47fvb02 + - microchip,mcp47fvb04 + - microchip,mcp47fvb08 + - microchip,mcp47fvb11 + - microchip,mcp47fvb12 + - microchip,mcp47fvb14 + - microchip,mcp47fvb18 + - microchip,mcp47fvb21 + - microchip,mcp47fvb22 + - microchip,mcp47fvb24 + - microchip,mcp47fvb28 + then: + properties: + spi-max-frequency: false + +unevaluatedProperties: false =20 examples: - | @@ -280,7 +398,7 @@ examples: =20 #address-cells =3D <1>; #size-cells =3D <0>; - dac@0 { + dac@60 { compatible =3D "microchip,mcp47feb02"; reg =3D <0>; vdd-supply =3D <&vdac_vdd>; @@ -299,4 +417,29 @@ examples: }; }; }; + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dac@0 { + compatible =3D "microchip,mcp48feb02"; + reg =3D <0>; + vdd-supply =3D <&vdac_vdd>; + vref-supply =3D <&vref_reg>; + spi-max-frequency =3D <10000000>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + label =3D "Adjustable_voltage_ch0"; + }; + + channel@1 { + reg =3D <0x1>; + label =3D "Adjustable_voltage_ch1"; + }; + }; + }; ... diff --git a/MAINTAINERS b/MAINTAINERS index d664add6d40891fb4a94dba34c58d401df81d657..5997cf04b0732beaf69ac78cb76= 2c42c56e4fcd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15850,7 +15850,6 @@ M: Ariana Lazar L: linux-iio@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml -F: drivers/iio/dac/mcp47feb02.c =20 MCP4821 DAC DRIVER M: Anshul Dalal --=20 2.43.0 From nobody Sun Jun 14 14:30:11 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04D3833F8C1; Fri, 3 Apr 2026 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dac: mcp47feb02: add MCP48FEB02 SPI driver to MCP47FEB02 I2C driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260403-mcp47feb02-fix2-v1-2-da60c773550e@microchip.com> References: <20260403-mcp47feb02-fix2-v1-0-da60c773550e@microchip.com> In-Reply-To: <20260403-mcp47feb02-fix2-v1-0-da60c773550e@microchip.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Jonathan Cameron , Conor Dooley , , , , Ariana Lazar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775213414; l=52331; i=ariana.lazar@microchip.com; s=20250825; h=from:subject:message-id; bh=Z4sCw/tXCwUCpxM3lMTl5uhv1+oiMgAILF99F59ctuM=; b=rtaXT3zbbZBtdXvrYp3jellaIDmenTLX70ZdXUbyB+c1YfbKdRugEqWvFM1YrZb+Hv1Pp6iW/ WkY3eYVZ6OQBiufuIyPVDfr+WT28D7BzhpBmkaQDp5FXOkJ3P1a38Y3 X-Developer-Key: i=ariana.lazar@microchip.com; a=ed25519; pk=jmvf1fSxcnzZmXfITM3L94IwutM+wqA1POQHiYyD6Dk= This is the iio driver for Microchip MCP48FxBy1/2/4/8 series of buffered voltage output Digital-to-Analog Converters with nonvolatile or volatile memory on top of MCP47FEB02. The families support up to 8 output channels and have 8-bit, 10-bit or 12-bit resolution. The MCP47FEB02 driver was split into three modules: mcp47feb02-core.c, mcp47feb02-i2c.c and mcp47feb02-spi.c in order to support both DAC families - I2C (MCP47F(E/V)BXX) and SPI (MCP48F(E/V)BXX). Fixes: bf394cc80369 ("iio: dac: adding support for Microchip MCP47FEB02") Signed-off-by: Ariana Lazar Link: https://lore.kernel.org/all/aY4yaVP2TQFRI1E4@smile.fi.intel.com/ --- MAINTAINERS | 4 + drivers/iio/dac/Kconfig | 29 +- drivers/iio/dac/Makefile | 3 + drivers/iio/dac/mcp47feb02-core.c | 845 ++++++++++++++++++++++++++++++++++= ++++ drivers/iio/dac/mcp47feb02-i2c.c | 145 +++++++ drivers/iio/dac/mcp47feb02-spi.c | 145 +++++++ drivers/iio/dac/mcp47feb02.h | 158 +++++++ 7 files changed, 1328 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5997cf04b0732beaf69ac78cb762c42c56e4fcd6..af747c5449681807d3d74014dc1= 1dffea5acc012 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15850,6 +15850,10 @@ M: Ariana Lazar L: linux-iio@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml +F: drivers/iio/dac/mcp47feb02-core.c +F: drivers/iio/dac/mcp47feb02-i2c.c +F: drivers/iio/dac/mcp47feb02-spi.c +F: drivers/iio/dac/mcp47feb02.h =20 MCP4821 DAC DRIVER M: Anshul Dalal diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index cd4870b654153e91c3c44860be43d231ee3b5519..5bec52552d263532ffe357666a6= 4a1c6bb968d85 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -539,8 +539,12 @@ config MCP4728 will be called mcp4728. =20 config MCP47FEB02 + tristate + +config MCP47FEB02_I2C tristate "MCP47F(E/V)B01/02/04/08/11/12/14/18/21/22/24/28 DAC driver" depends on I2C + select MCP47FEB02 help Say yes here if you want to build the driver for the Microchip: - 8-bit DAC: @@ -556,7 +560,30 @@ config MCP47FEB02 (DAC) with I2C interface. =20 To compile this driver as a module, choose M here: the module - will be called mcp47feb02. + will be called mcp47feb02_i2c and you will also get + mcp47feb02_core for the core module. + +config MCP47FEB02_SPI + tristate "MCP48F(E/V)B01/02/04/08/11/12/14/18/21/22/24/28 DAC driver" + depends on SPI + select MCP47FEB02 + help + Say yes here if you want to build the driver for the Microchip: + - 8-bit DAC: + MCP48FEB01, MCP48FEB02, MCP48FEB04, MCP48FEB08, + MCP48FVB01, MCP48FVB02, MCP48FVB04, MCP48FVB08 + - 10-bit DAC: + MCP48FEB11, MCP48FEB12, MCP48FEB14, MCP48FEB18, + MCP48FVB11, MCP48FVB12, MCP48FVB14, MCP48FVB18 + - 12-bit DAC: + MCP48FEB21, MCP48FEB22, MCP48FEB24, MCP48FEB28, + MCP48FVB21, MCP48FVB22, MCP48FVB24, MCP48FVB28 + having 1 to 8 channels, 8/10/12-bit digital-to-analog converter + (DAC) with SPI interface. + + To compile this driver as a module, choose M here: the module + will be called mcp47feb02_spi and you will also get + mcp47feb02_core for the core module. =20 config MCP4821 tristate "MCP4801/02/11/12/21/22 DAC driver" diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 2a80bbf4e80ad557da79ed916027cedff286984b..d2a2279b15499e1b43ed0e3e1f1= 80b5b1ff72785 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -54,6 +54,9 @@ obj-$(CONFIG_MAX5821) +=3D max5821.o obj-$(CONFIG_MCP4725) +=3D mcp4725.o obj-$(CONFIG_MCP4728) +=3D mcp4728.o obj-$(CONFIG_MCP47FEB02) +=3D mcp47feb02.o +mcp47feb02-objs :=3D mcp47feb02-core.o +obj-$(CONFIG_MCP47FEB02_I2C) +=3D mcp47feb02-i2c.o +obj-$(CONFIG_MCP47FEB02_SPI) +=3D mcp47feb02-spi.o obj-$(CONFIG_MCP4821) +=3D mcp4821.o obj-$(CONFIG_MCP4922) +=3D mcp4922.o obj-$(CONFIG_STM32_DAC_CORE) +=3D stm32-dac-core.o diff --git a/drivers/iio/dac/mcp47feb02-core.c b/drivers/iio/dac/mcp47feb02= -core.c new file mode 100644 index 0000000000000000000000000000000000000000..728da45c27beb3f523f5ae7b63e= ae57ab18c6492 --- /dev/null +++ b/drivers/iio/dac/mcp47feb02-core.c @@ -0,0 +1,845 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * IIO driver for MCP47FEB02 Multi-Channel DAC with I2C or SPI interface + * + * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries + * + * Author: Ariana Lazar + * + * Datasheet links for devices with I2C interface: + * [MCP47FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005375A.pdf + * [MCP47FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005405A.pdf + * [MCP47FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documen= ts/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf + * + * Datasheet links for devices with SPI interface: + * [MCP48FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005429B.pdf + * [MCP48FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005466A.pdf + * [MCP48FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documen= ts/MSLD/ProductDocuments/DataSheets/MCP48FXBX4-8-Family-Data-Sheet-DS200063= 62A.pdf + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mcp47feb02.h" + +const char * const mcp47feb02_powerdown_modes[] =3D { + "1kohm_to_gnd", + "100kohm_to_gnd", + "open_circuit", +}; + +static const struct regmap_range mcp47feb02_readable_ranges[] =3D { + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), +}; + +static const struct regmap_range mcp47feb02_writable_ranges[] =3D { + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), +}; + +static const struct regmap_range mcp47feb02_volatile_ranges[] =3D { + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), +}; + +static const struct regmap_access_table mcp47feb02_readable_table =3D { + .yes_ranges =3D mcp47feb02_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp47feb02_readable_ranges), +}; + +static const struct regmap_access_table mcp47feb02_writable_table =3D { + .yes_ranges =3D mcp47feb02_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp47feb02_writable_ranges), +}; + +static const struct regmap_access_table mcp47feb02_volatile_table =3D { + .yes_ranges =3D mcp47feb02_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp47feb02_volatile_ranges), +}; + +const struct regmap_config mcp47feb02_regmap_config =3D { + .name =3D "mcp47feb02_regmap", + .reg_bits =3D 8, + .val_bits =3D 16, + .rd_table =3D &mcp47feb02_readable_table, + .wr_table =3D &mcp47feb02_writable_table, + .volatile_table =3D &mcp47feb02_volatile_table, + .max_register =3D MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR, + .read_flag_mask =3D READFLAG_MASK, + .cache_type =3D REGCACHE_MAPLE, + .val_format_endian =3D REGMAP_ENDIAN_BIG, +}; +EXPORT_SYMBOL_NS_GPL(mcp47feb02_regmap_config, "IIO_MCP47FEB02"); + +/* For devices that doesn't have nonvolatile memory */ +static const struct regmap_range mcp47fvb02_readable_ranges[] =3D { + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), +}; + +static const struct regmap_range mcp47fvb02_writable_ranges[] =3D { + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), +}; + +static const struct regmap_range mcp47fvb02_volatile_ranges[] =3D { + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_RE= G_ADDR), +}; + +static const struct regmap_access_table mcp47fvb02_readable_table =3D { + .yes_ranges =3D mcp47fvb02_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp47fvb02_readable_ranges), +}; + +static const struct regmap_access_table mcp47fvb02_writable_table =3D { + .yes_ranges =3D mcp47fvb02_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp47fvb02_writable_ranges), +}; + +static const struct regmap_access_table mcp47fvb02_volatile_table =3D { + .yes_ranges =3D mcp47fvb02_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp47fvb02_volatile_ranges), +}; + +const struct regmap_config mcp47fvb02_regmap_config =3D { + .name =3D "mcp47fvb02_regmap", + .reg_bits =3D 8, + .val_bits =3D 16, + .rd_table =3D &mcp47fvb02_readable_table, + .wr_table =3D &mcp47fvb02_writable_table, + .volatile_table =3D &mcp47fvb02_volatile_table, + .max_register =3D MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR, + .read_flag_mask =3D READFLAG_MASK, + .cache_type =3D REGCACHE_MAPLE, + .val_format_endian =3D REGMAP_ENDIAN_BIG, +}; +EXPORT_SYMBOL_NS_GPL(mcp47fvb02_regmap_config, "IIO_MCP47FEB02"); + +static int mcp47feb02_write_to_eeprom(struct mcp47feb02_data *data, unsign= ed int reg, + unsigned int val) +{ + unsigned int eewa_val; + int ret; + + ret =3D regmap_read_poll_timeout(data->regmap, MCP47FEB02_GAIN_CTRL_STATU= S_REG_ADDR, + eewa_val, + !(eewa_val & MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK), + 1 * USEC_PER_MSEC, 5 * USEC_PER_MSEC); + if (ret) + return ret; + + return regmap_write(data->regmap, reg, val); +} + +static ssize_t store_eeprom_store(struct device *dev, struct device_attrib= ute *attr, + const char *buf, size_t len) +{ + struct mcp47feb02_data *data =3D iio_priv(dev_to_iio_dev(dev)); + unsigned int i, val, val1, eewa_val; + bool state; + int ret; + + ret =3D kstrtobool(buf, &state); + if (ret) + return ret; + + if (!state) + return 0; + + /* + * Wait until the currently occurring EEPROM Write Cycle is completed. + * Only serial commands to the volatile memory are allowed. + */ + guard(mutex)(&data->lock); + + /* + * Verify DAC Wiper and DAC Configuration are unlocked. If both are disab= led, + * writing to EEPROM is available. + */ + ret =3D regmap_read(data->regmap, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR, &= val); + if (ret) + return ret; + + if (val) { + dev_err(dev, "DAC Wiper and DAC Configuration are not unlocked\n"); + return -EINVAL; + } + + for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) { + ret =3D mcp47feb02_write_to_eeprom(data, NV_REG_ADDR(i), + data->chdata[i].dac_data); + if (ret) + return ret; + } + + ret =3D regmap_read(data->regmap, MCP47FEB02_VREF_REG_ADDR, &val); + if (ret) + return ret; + + ret =3D mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_VREF_REG_ADDR, val= ); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, &val); + if (ret) + return ret; + + ret =3D mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_POWER_DOWN_REG_ADD= R, val); + if (ret) + return ret; + + ret =3D regmap_read_poll_timeout(data->regmap, MCP47FEB02_GAIN_CTRL_STATU= S_REG_ADDR, eewa_val, + !(eewa_val & MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK), + USEC_PER_MSEC, USEC_PER_MSEC * 5); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_A= DDR, &val); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, &= val1); + if (ret) + return ret; + + ret =3D mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAV= E_REG_ADDR, + (val1 & MCP47FEB02_GAIN_BITS_MASK) | + (val & MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK)); + if (ret) + return ret; + + return len; +} +static IIO_DEVICE_ATTR_WO(store_eeprom, 0); + +static struct attribute *mcp47feb02_attributes[] =3D { + &iio_dev_attr_store_eeprom.dev_attr.attr, + NULL +}; + +static const struct attribute_group mcp47feb02_attribute_group =3D { + .attrs =3D mcp47feb02_attributes, +}; + +static int mcp47feb02_suspend(struct device *dev) +{ + struct mcp47feb02_data *data =3D iio_priv(dev_get_drvdata(dev)); + int ret; + u8 ch; + + guard(mutex)(&data->lock); + + for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) { + u8 pd_mode; + + data->chdata[ch].powerdown =3D true; + pd_mode =3D data->chdata[ch].powerdown_mode + 1; + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, + DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, pd_mode)); + if (ret) + return ret; + + ret =3D regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_da= ta); + if (ret) + return ret; + } + + return 0; +} + +static int mcp47feb02_resume(struct device *dev) +{ + struct mcp47feb02_data *data =3D iio_priv(dev_get_drvdata(dev)); + u8 ch; + + guard(mutex)(&data->lock); + + for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) { + int ret; + + data->chdata[ch].powerdown =3D false; + + ret =3D regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_da= ta); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_VREF_REG_ADDR, + DAC_CTRL_MASK(ch), + DAC_CTRL_VAL(ch, data->chdata[ch].ref_mode)); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG= _ADDR, + DAC_GAIN_MASK(ch), + DAC_GAIN_VAL(ch, data->chdata[ch].use_2x_gain)); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, + DAC_CTRL_MASK(ch), + DAC_CTRL_VAL(ch, MCP47FEB02_NORMAL_OPERATION)); + if (ret) + return ret; + } + + return 0; +} + +static int mcp47feb02_get_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + + return data->chdata[chan->address].powerdown_mode; +} + +static int mcp47feb02_set_powerdown_mode(struct iio_dev *indio_dev, const = struct iio_chan_spec *ch, + unsigned int mode) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + + data->chdata[ch->address].powerdown_mode =3D mode; + + return 0; +} + +static ssize_t mcp47feb02_read_powerdown(struct iio_dev *indio_dev, uintpt= r_t private, + const struct iio_chan_spec *ch, char *buf) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + + /* Print if channel is in a power-down mode or not */ + return sysfs_emit(buf, "%d\n", data->chdata[ch->address].powerdown); +} + +static ssize_t mcp47feb02_write_powerdown(struct iio_dev *indio_dev, uintp= tr_t private, + const struct iio_chan_spec *ch, const char *buf, + size_t len) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + u32 reg =3D ch->address; + u8 tmp_pd_mode; + bool state; + int ret; + + guard(mutex)(&data->lock); + + ret =3D kstrtobool(buf, &state); + if (ret) + return ret; + + /* + * Set the channel to the specified power-down mode. Exiting power-down m= ode + * requires writing normal operation mode (0) to the channel-specific reg= ister bits. + */ + tmp_pd_mode =3D state ? (data->chdata[reg].powerdown_mode + 1) : MCP47FEB= 02_NORMAL_OPERATION; + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, + DAC_CTRL_MASK(reg), DAC_CTRL_VAL(reg, tmp_pd_mode)); + if (ret) + return ret; + + data->chdata[reg].powerdown =3D state; + + return len; +} + +EXPORT_SIMPLE_DEV_PM_OPS(mcp47feb02_pm_ops, mcp47feb02_suspend, mcp47feb02= _resume); + +static const struct iio_enum mcp47febxx_powerdown_mode_enum =3D { + .items =3D mcp47feb02_powerdown_modes, + .num_items =3D ARRAY_SIZE(mcp47feb02_powerdown_modes), + .get =3D mcp47feb02_get_powerdown_mode, + .set =3D mcp47feb02_set_powerdown_mode, +}; + +static const struct iio_chan_spec_ext_info mcp47feb02_ext_info[] =3D { + { + .name =3D "powerdown", + .read =3D mcp47feb02_read_powerdown, + .write =3D mcp47feb02_write_powerdown, + .shared =3D IIO_SEPARATE, + }, + IIO_ENUM("powerdown_mode", IIO_SEPARATE, &mcp47febxx_powerdown_mode_enum), + IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &mcp47febxx_powe= rdown_mode_enum), + { } +}; + +static const struct iio_chan_spec mcp47febxx_ch_template =3D { + .type =3D IIO_VOLTAGE, + .output =3D 1, + .indexed =3D 1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE), + .ext_info =3D mcp47feb02_ext_info, +}; + +static void mcp47feb02_init_scale(struct mcp47feb02_data *data, enum mcp47= feb02_scale scale, + int vref_uV, int scale_avail[]) +{ + u32 tmp; + + /* + * Avoid expensive 64-bit division. + */ + tmp =3D (vref_uV * (MILLI / 8)) >> (data->chip_features->resolution - 3); + scale_avail[scale * 2] =3D tmp / MICRO; + scale_avail[scale * 2 + 1] =3D tmp % MICRO; +} + +static int mcp47feb02_init_scales_avail(struct mcp47feb02_data *data, int = vdd_uV, + int vref_uV, int vref1_uV) +{ + int tmp_vref; + + mcp47feb02_init_scale(data, MCP47FEB02_SCALE_VDD, vdd_uV, data->scale_0); + + tmp_vref =3D data->use_vref ? vref_uV : MCP47FEB02_INTERNAL_BAND_GAP_uV; + mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X1, tmp_vref, data->sca= le_0); + mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X2, tmp_vref * 2, data-= >scale_0); + + if (data->phys_channels >=3D 4) { + mcp47feb02_init_scale(data, MCP47FEB02_SCALE_VDD, vdd_uV, data->scale_1); + tmp_vref =3D data->use_vref1 ? vref1_uV : MCP47FEB02_INTERNAL_BAND_GAP_u= V; + + mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X1, + tmp_vref, data->scale_1); + mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X2, + tmp_vref * 2, data->scale_1); + } + + return 0; +} + +static int mcp47feb02_read_avail(struct iio_dev *indio_dev, struct iio_cha= n_spec const *ch, + const int **vals, int *type, int *length, long info) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SCALE: + switch (ch->type) { + case IIO_VOLTAGE: + *vals =3D data->chdata[ch->address].scale_avail; + *length =3D 2 * MCP47FEB02_MAX_SCALES_CH; + *type =3D IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static void mcp47feb02_get_scale(int ch, struct mcp47feb02_data *data, int= *val, int *val2) +{ + enum mcp47feb02_scale current_scale; + int *scale; + + if (data->chdata[ch].ref_mode =3D=3D MCP47FEB02_VREF_VDD) + current_scale =3D MCP47FEB02_SCALE_VDD; + else if (data->chdata[ch].use_2x_gain) + current_scale =3D MCP47FEB02_SCALE_GAIN_X2; + else + current_scale =3D MCP47FEB02_SCALE_GAIN_X1; + + scale =3D data->chdata[ch].scale_avail; + *val =3D scale[current_scale * 2]; + *val2 =3D scale[current_scale * 2 + 1]; +} + +static int mcp47feb02_check_scale(struct mcp47feb02_data *data, int val, i= nt val2, int scale[]) +{ + unsigned int i; + + for (i =3D 0; i < MCP47FEB02_MAX_SCALES_CH; i++) { + if (scale[i * 2] =3D=3D val && scale[i * 2 + 1] =3D=3D val2) + return i; + } + + return -EINVAL; +} + +static int mcp47feb02_ch_scale(struct mcp47feb02_data *data, int ch, int s= cale) +{ + int tmp_val, ret; + + if (scale =3D=3D MCP47FEB02_SCALE_VDD) { + tmp_val =3D MCP47FEB02_VREF_VDD; + } else if (data->phys_channels >=3D 4 && (ch % 2)) { + if (data->use_vref1) { + if (data->vref1_buffered) + tmp_val =3D MCP47FEB02_EXTERNAL_VREF_BUFFERED; + else + tmp_val =3D MCP47FEB02_EXTERNAL_VREF_UNBUFFERED; + } else { + tmp_val =3D MCP47FEB02_INTERNAL_BAND_GAP; + } + } else if (data->use_vref) { + if (data->vref_buffered) + tmp_val =3D MCP47FEB02_EXTERNAL_VREF_BUFFERED; + else + tmp_val =3D MCP47FEB02_EXTERNAL_VREF_UNBUFFERED; + } else { + tmp_val =3D MCP47FEB02_INTERNAL_BAND_GAP; + } + + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_VREF_REG_ADDR, + DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, tmp_val)); + if (ret) + return ret; + + data->chdata[ch].ref_mode =3D tmp_val; + + return 0; +} + +/* + * Setting the scale in order to choose between VDD and (Vref or Band Gap)= from the user + * space. The VREF pin is either an input or an output, therefore the user= cannot + * simultaneously connect an external voltage reference to the pin and sel= ect the + * internal Band Gap. + * When the DAC=E2=80=99s voltage reference is configured as the VREF pin,= the pin is an input. + * When the DAC=E2=80=99s voltage reference is configured as the internal = Band Gap, + * the VREF pin is an output. + * If Vref/Vref1 voltage is not available, then the internal Band Gap will= be used + * to calculate the values for the scale. + */ +static int mcp47feb02_set_scale(struct mcp47feb02_data *data, int ch, int = scale) +{ + unsigned int tmp_val; + int ret; + + ret =3D mcp47feb02_ch_scale(data, ch, scale); + if (ret) + return ret; + + if (scale =3D=3D MCP47FEB02_SCALE_GAIN_X2) + tmp_val =3D MCP47FEB02_GAIN_BIT_X2; + else + tmp_val =3D MCP47FEB02_GAIN_BIT_X1; + + ret =3D regmap_update_bits(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_= ADDR, + DAC_GAIN_MASK(ch), DAC_GAIN_VAL(ch, tmp_val)); + if (ret) + return ret; + + data->chdata[ch].use_2x_gain =3D tmp_val; + + return 0; +} + +static int mcp47feb02_read_raw(struct iio_dev *indio_dev, struct iio_chan_= spec const *ch, + int *val, int *val2, long mask) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_read(data->regmap, REG_ADDR(ch->address), val); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + mcp47feb02_get_scale(ch->address, data, val, val2); + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int mcp47feb02_write_raw(struct iio_dev *indio_dev, struct iio_chan= _spec const *ch, + int val, int val2, long mask) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + int ret; + + guard(mutex)(&data->lock); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_write(data->regmap, REG_ADDR(ch->address), val); + if (ret) + return ret; + + data->chdata[ch->address].dac_data =3D val; + return 0; + case IIO_CHAN_INFO_SCALE: + ret =3D mcp47feb02_check_scale(data, val, val2, + data->chdata[ch->address].scale_avail); + if (ret < 0) + return ret; + + return mcp47feb02_set_scale(data, ch->address, ret); + default: + return -EINVAL; + } +} + +static int mcp47feb02_read_label(struct iio_dev *indio_dev, struct iio_cha= n_spec const *ch, + char *label) +{ + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + + return sysfs_emit(label, "%s\n", data->labels[ch->address]); +} + +static const struct iio_info mcp47feb02_info =3D { + .read_raw =3D mcp47feb02_read_raw, + .write_raw =3D mcp47feb02_write_raw, + .read_label =3D mcp47feb02_read_label, + .read_avail =3D &mcp47feb02_read_avail, + .attrs =3D &mcp47feb02_attribute_group, +}; + +static const struct iio_info mcp47fvb02_info =3D { + .read_raw =3D mcp47feb02_read_raw, + .write_raw =3D mcp47feb02_write_raw, + .read_label =3D mcp47feb02_read_label, + .read_avail =3D &mcp47feb02_read_avail, +}; + +static int mcp47feb02_parse_fw(struct iio_dev *indio_dev, + const struct mcp47feb02_features *chip_features) +{ + struct iio_chan_spec chanspec =3D mcp47febxx_ch_template; + struct mcp47feb02_data *data =3D iio_priv(indio_dev); + struct device *dev =3D regmap_get_device(data->regmap); + struct iio_chan_spec *channels; + u32 num_channels; + u8 chan_idx; + + num_channels =3D device_get_child_node_count(dev); + if (num_channels > chip_features->phys_channels) + return dev_err_probe(dev, -EINVAL, "More channels than the chip supports= \n"); + + if (num_channels =3D=3D 0) + return dev_err_probe(dev, -EINVAL, "No channel specified in the devicetr= ee\n"); + + channels =3D devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNE= L); + if (!channels) + return -ENOMEM; + + chan_idx =3D 0; + device_for_each_child_node_scoped(dev, child) { + u32 reg; + int ret; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return dev_err_probe(dev, ret, "Invalid channel number\n"); + + if (reg >=3D chip_features->phys_channels) + return dev_err_probe(dev, -EINVAL, + "The index of the channels does not match the chip\n"); + + __set_bit(reg, &data->active_channels_mask); + + ret =3D fwnode_property_read_string(child, "label", &data->labels[reg]); + if (ret) + dev_dbg(dev, "%pfw: invalid label\n", child); + + chanspec.address =3D reg; + chanspec.channel =3D reg; + channels[chan_idx] =3D chanspec; + chan_idx++; + } + + indio_dev->num_channels =3D num_channels; + indio_dev->channels =3D channels; + indio_dev->modes =3D INDIO_DIRECT_MODE; + data->phys_channels =3D chip_features->phys_channels; + + data->vref_buffered =3D device_property_read_bool(dev, "microchip,vref-bu= ffered"); + + if (chip_features->have_ext_vref1) + data->vref1_buffered =3D device_property_read_bool(dev, "microchip,vref1= -buffered"); + + return 0; +} + +static int mcp47feb02_init_ctrl_regs(struct mcp47feb02_data *data) +{ + unsigned int i, vref_ch, gain_ch, pd_ch; + int ret; + + ret =3D regmap_read(data->regmap, MCP47FEB02_VREF_REG_ADDR, &vref_ch); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, &= gain_ch); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, &pd_ch); + if (ret) + return ret; + + gain_ch =3D gain_ch & MCP47FEB02_GAIN_BITS_MASK; + for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) { + struct device *dev =3D regmap_get_device(data->regmap); + unsigned int pd_tmp; + + data->chdata[i].ref_mode =3D (vref_ch >> (2 * i)) & MCP47FEB02_DAC_CTRL_= MASK; + data->chdata[i].use_2x_gain =3D (gain_ch >> i) & MCP47FEB02_GAIN_BIT_MA= SK; + + /* + * Inform the user that the current voltage reference read from the vola= tile + * register of the chip is different from the one specified in the devic= e tree. + * Considering that the user cannot have an external voltage reference c= onnected + * to the pin and select the internal Band Gap at the same time, in orde= r to avoid + * miscofiguring the reference voltage, the volatile register will not b= e written. + * In order to overwrite the setting from volatile register with the one= from the + * device tree, the user needs to write the chosen scale. + */ + switch (data->chdata[i].ref_mode) { + case MCP47FEB02_INTERNAL_BAND_GAP: + if (data->phys_channels >=3D 4 && (i % 2) && data->use_vref1) { + dev_dbg(dev, + "ch[%u]: was configured to use internal band gap\n", i); + dev_dbg(dev, "ch[%u]: reference voltage set to VREF1\n", i); + break; + } + if (data->use_vref && ((data->phys_channels >=3D 4 && !(i % 2)) || + data->phys_channels < 4)) { + dev_dbg(dev, + "ch[%u]: was configured to use internal band gap\n", i); + dev_dbg(dev, "ch[%u]: reference voltage set to vref\n", i); + break; + } + break; + case MCP47FEB02_EXTERNAL_VREF_UNBUFFERED: + case MCP47FEB02_EXTERNAL_VREF_BUFFERED: + if (!data->use_vref1 && data->phys_channels >=3D 4 && (i % 2)) { + dev_dbg(dev, "ch[%u]: was configured to use vref1\n", i); + dev_dbg(dev, + "ch[%u]: reference voltage set to internal band gap\n", i); + break; + } + if (!data->use_vref && ((data->phys_channels >=3D 4 && !(i % 2)) || + data->phys_channels < 4)) { + dev_dbg(dev, "ch[%u]: was configured to use vref\n", i); + dev_dbg(dev, + "ch[%u]: reference voltage set to internal band gap\n", i); + break; + } + break; + } + + pd_tmp =3D (pd_ch >> (2 * i)) & MCP47FEB02_DAC_CTRL_MASK; + data->chdata[i].powerdown_mode =3D pd_tmp ? (pd_tmp - 1) : pd_tmp; + data->chdata[i].powerdown =3D !!(data->chdata[i].powerdown_mode); + } + + return 0; +} + +static int mcp47feb02_init_ch_scales(struct mcp47feb02_data *data, int vdd= _uV, + int vref_uV, int vref1_uV) +{ + struct device *dev =3D regmap_get_device(data->regmap); + unsigned int i; + int ret; + + ret =3D mcp47feb02_init_scales_avail(data, vdd_uV, vref_uV, vref1_uV); + if (ret) + return dev_err_probe(dev, ret, "Failed to init scales\n"); + + for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) { + if (data->phys_channels >=3D 4 && (i % 2)) + data->chdata[i].scale_avail =3D data->scale_1; + else + data->chdata[i].scale_avail =3D data->scale_0; + } + + return 0; +} + +int mcp47feb02_common_probe(const struct mcp47feb02_features *chip_feature= s, struct regmap *regmap) +{ + struct device *dev =3D regmap_get_device(regmap); + int vref1_uV, vref_uV, vdd_uV; + struct mcp47feb02_data *data; + struct iio_dev *indio_dev; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data =3D iio_priv(indio_dev); + data->chip_features =3D chip_features; + data->regmap =3D regmap; + + indio_dev->info =3D chip_features->have_eeprom ? &mcp47feb02_info : &mcp4= 7fvb02_info; + indio_dev->name =3D chip_features->name; + + ret =3D devm_mutex_init(dev, &data->lock); + if (ret) + return ret; + + ret =3D mcp47feb02_parse_fw(indio_dev, chip_features); + if (ret) + return dev_err_probe(dev, ret, "Error parsing firmware data\n"); + + ret =3D devm_regulator_get_enable_read_voltage(dev, "vdd"); + if (ret < 0) + return ret; + + vdd_uV =3D ret; + + ret =3D devm_regulator_get_enable_read_voltage(dev, "vref"); + if (ret > 0) { + vref_uV =3D ret; + data->use_vref =3D true; + } else { + vref_uV =3D 0; + dev_dbg(dev, "Using internal band gap as voltage reference.\n"); + dev_dbg(dev, "Vref is unavailable.\n"); + } + + if (chip_features->have_ext_vref1) { + ret =3D devm_regulator_get_enable_read_voltage(dev, "vref1"); + if (ret > 0) { + vref1_uV =3D ret; + data->use_vref1 =3D true; + } else { + vref1_uV =3D 0; + dev_dbg(dev, "Using internal band gap as voltage reference 1.\n"); + dev_dbg(dev, "Vref1 is unavailable.\n"); + } + } + + ret =3D mcp47feb02_init_ctrl_regs(data); + if (ret) + return dev_err_probe(dev, ret, "Error initialising vref register\n"); + + ret =3D mcp47feb02_init_ch_scales(data, vdd_uV, vref_uV, vref1_uV); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} +EXPORT_SYMBOL_NS(mcp47feb02_common_probe, "IIO_MCP47FEB02"); + +MODULE_AUTHOR("Ariana Lazar "); +MODULE_DESCRIPTION("IIO driver for MCP47FXBX4/8 and MCP48FXBX4/8 DAC with = I2C or SPI interface"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/dac/mcp47feb02-i2c.c b/drivers/iio/dac/mcp47feb02-= i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..78e4e380d42c9686625e749ba2f= 0965a3fb4fff7 --- /dev/null +++ b/drivers/iio/dac/mcp47feb02-i2c.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * IIO driver for MCP47FEB02 Multi-Channel DAC with I2C interface + * + * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries + * + * Author: Ariana Lazar + * + * Datasheet links for devices with I2C interface: + * [MCP47FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005375A.pdf + * [MCP47FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005405A.pdf + * [MCP47FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documen= ts/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mcp47feb02.h" + +MCP47FEB02_CHIP_INFO(mcp47feb01, 1, 8, false, true); +MCP47FEB02_CHIP_INFO(mcp47feb02, 2, 8, false, true); +MCP47FEB02_CHIP_INFO(mcp47feb04, 4, 8, true, true); +MCP47FEB02_CHIP_INFO(mcp47feb08, 8, 8, true, true); +MCP47FEB02_CHIP_INFO(mcp47feb11, 1, 10, false, true); +MCP47FEB02_CHIP_INFO(mcp47feb12, 2, 10, false, true); +MCP47FEB02_CHIP_INFO(mcp47feb14, 4, 10, true, true); +MCP47FEB02_CHIP_INFO(mcp47feb18, 8, 10, true, true); +MCP47FEB02_CHIP_INFO(mcp47feb21, 1, 12, false, true); +MCP47FEB02_CHIP_INFO(mcp47feb22, 2, 12, false, true); +MCP47FEB02_CHIP_INFO(mcp47feb24, 4, 12, true, true); +MCP47FEB02_CHIP_INFO(mcp47feb28, 8, 12, true, true); + +/* Parts without EEPROM memory */ +MCP47FEB02_CHIP_INFO(mcp47fvb01, 1, 8, false, false); +MCP47FEB02_CHIP_INFO(mcp47fvb02, 2, 8, false, false); +MCP47FEB02_CHIP_INFO(mcp47fvb04, 4, 8, true, false); +MCP47FEB02_CHIP_INFO(mcp47fvb08, 8, 8, true, false); +MCP47FEB02_CHIP_INFO(mcp47fvb11, 1, 10, false, false); +MCP47FEB02_CHIP_INFO(mcp47fvb12, 2, 10, false, false); +MCP47FEB02_CHIP_INFO(mcp47fvb14, 4, 10, true, false); +MCP47FEB02_CHIP_INFO(mcp47fvb18, 8, 10, true, false); +MCP47FEB02_CHIP_INFO(mcp47fvb21, 1, 12, false, false); +MCP47FEB02_CHIP_INFO(mcp47fvb22, 2, 12, false, false); +MCP47FEB02_CHIP_INFO(mcp47fvb24, 4, 12, true, false); +MCP47FEB02_CHIP_INFO(mcp47fvb28, 8, 12, true, false); + +static int mcp47feb02_i2c_probe(struct i2c_client *client) +{ + const struct mcp47feb02_features *chip_features; + struct device *dev =3D &client->dev; + struct regmap *regmap; + + chip_features =3D i2c_get_match_data(client); + if (!chip_features) + return -EINVAL; + + if (chip_features->have_eeprom) + regmap =3D devm_regmap_init_i2c(client, &mcp47feb02_regmap_config); + else + regmap =3D devm_regmap_init_i2c(client, &mcp47fvb02_regmap_config); + + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Error initializing I2C regma= p\n"); + + return mcp47feb02_common_probe(chip_features, regmap); +} + +static const struct i2c_device_id mcp47feb02_i2c_id[] =3D { + { "mcp47feb01", (kernel_ulong_t)&mcp47feb01_chip_features }, + { "mcp47feb02", (kernel_ulong_t)&mcp47feb02_chip_features }, + { "mcp47feb04", (kernel_ulong_t)&mcp47feb04_chip_features }, + { "mcp47feb08", (kernel_ulong_t)&mcp47feb08_chip_features }, + { "mcp47feb11", (kernel_ulong_t)&mcp47feb11_chip_features }, + { "mcp47feb12", (kernel_ulong_t)&mcp47feb12_chip_features }, + { "mcp47feb14", (kernel_ulong_t)&mcp47feb14_chip_features }, + { "mcp47feb18", (kernel_ulong_t)&mcp47feb18_chip_features }, + { "mcp47feb21", (kernel_ulong_t)&mcp47feb21_chip_features }, + { "mcp47feb22", (kernel_ulong_t)&mcp47feb22_chip_features }, + { "mcp47feb24", (kernel_ulong_t)&mcp47feb24_chip_features }, + { "mcp47feb28", (kernel_ulong_t)&mcp47feb28_chip_features }, + { "mcp47fvb01", (kernel_ulong_t)&mcp47fvb01_chip_features }, + { "mcp47fvb02", (kernel_ulong_t)&mcp47fvb02_chip_features }, + { "mcp47fvb04", (kernel_ulong_t)&mcp47fvb04_chip_features }, + { "mcp47fvb08", (kernel_ulong_t)&mcp47fvb08_chip_features }, + { "mcp47fvb11", (kernel_ulong_t)&mcp47fvb11_chip_features }, + { "mcp47fvb12", (kernel_ulong_t)&mcp47fvb12_chip_features }, + { "mcp47fvb14", (kernel_ulong_t)&mcp47fvb14_chip_features }, + { "mcp47fvb18", (kernel_ulong_t)&mcp47fvb18_chip_features }, + { "mcp47fvb21", (kernel_ulong_t)&mcp47fvb21_chip_features }, + { "mcp47fvb22", (kernel_ulong_t)&mcp47fvb22_chip_features }, + { "mcp47fvb24", (kernel_ulong_t)&mcp47fvb24_chip_features }, + { "mcp47fvb28", (kernel_ulong_t)&mcp47fvb28_chip_features }, + { } +}; +MODULE_DEVICE_TABLE(i2c, mcp47feb02_i2c_id); + +static const struct of_device_id mcp47feb02_of_i2c_match[] =3D { + { .compatible =3D "microchip,mcp47feb01", .data =3D &mcp47feb01_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb02", .data =3D &mcp47feb02_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb04", .data =3D &mcp47feb04_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb08", .data =3D &mcp47feb08_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb11", .data =3D &mcp47feb11_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb12", .data =3D &mcp47feb12_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb14", .data =3D &mcp47feb14_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb18", .data =3D &mcp47feb18_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb21", .data =3D &mcp47feb21_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb22", .data =3D &mcp47feb22_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb24", .data =3D &mcp47feb24_chip_feat= ures }, + { .compatible =3D "microchip,mcp47feb28", .data =3D &mcp47feb28_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb01", .data =3D &mcp47fvb01_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb02", .data =3D &mcp47fvb02_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb04", .data =3D &mcp47fvb04_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb08", .data =3D &mcp47fvb08_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb11", .data =3D &mcp47fvb11_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb12", .data =3D &mcp47fvb12_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb14", .data =3D &mcp47fvb14_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb18", .data =3D &mcp47fvb18_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb21", .data =3D &mcp47fvb21_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb22", .data =3D &mcp47fvb22_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb24", .data =3D &mcp47fvb24_chip_feat= ures }, + { .compatible =3D "microchip,mcp47fvb28", .data =3D &mcp47fvb28_chip_feat= ures }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp47feb02_of_i2c_match); + +static struct i2c_driver mcp47feb02_i2c_driver =3D { + .driver =3D { + .name =3D "mcp47feb02", + .of_match_table =3D mcp47feb02_of_i2c_match, + .pm =3D pm_sleep_ptr(&mcp47feb02_pm_ops), + }, + .probe =3D mcp47feb02_i2c_probe, + .id_table =3D mcp47feb02_i2c_id, +}; +module_i2c_driver(mcp47feb02_i2c_driver); + +MODULE_AUTHOR("Ariana Lazar "); +MODULE_DESCRIPTION("IIO driver for MCP47FEB02 Multi-Channel DAC with I2C i= nterface"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_MCP47FEB02"); diff --git a/drivers/iio/dac/mcp47feb02-spi.c b/drivers/iio/dac/mcp47feb02-= spi.c new file mode 100644 index 0000000000000000000000000000000000000000..82e99388ac75860d534d0f2cc05= dcc6628d96f6b --- /dev/null +++ b/drivers/iio/dac/mcp47feb02-spi.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * IIO driver for MCP48FEB02 Multi-Channel DAC with SPI interface + * + * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries + * + * Author: Ariana Lazar + * + * Datasheet links for devices with SPI interface: + * [MCP48FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005429B.pdf + * [MCP48FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005466A.pdf + * [MCP48FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documen= ts/MSLD/ProductDocuments/DataSheets/MCP48FXBX4-8-Family-Data-Sheet-DS200063= 62A.pdf + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mcp47feb02.h" + +MCP47FEB02_CHIP_INFO(mcp48feb01, 1, 8, false, true); +MCP47FEB02_CHIP_INFO(mcp48feb02, 2, 8, false, true); +MCP47FEB02_CHIP_INFO(mcp48feb04, 4, 8, true, true); +MCP47FEB02_CHIP_INFO(mcp48feb08, 8, 8, true, true); +MCP47FEB02_CHIP_INFO(mcp48feb11, 1, 10, false, true); +MCP47FEB02_CHIP_INFO(mcp48feb12, 2, 10, false, true); +MCP47FEB02_CHIP_INFO(mcp48feb14, 4, 10, true, true); +MCP47FEB02_CHIP_INFO(mcp48feb18, 8, 10, true, true); +MCP47FEB02_CHIP_INFO(mcp48feb21, 1, 12, false, true); +MCP47FEB02_CHIP_INFO(mcp48feb22, 2, 12, false, true); +MCP47FEB02_CHIP_INFO(mcp48feb24, 4, 12, true, true); +MCP47FEB02_CHIP_INFO(mcp48feb28, 8, 12, true, true); + +/* Parts without EEPROM memory */ +MCP47FEB02_CHIP_INFO(mcp48fvb01, 1, 8, false, false); +MCP47FEB02_CHIP_INFO(mcp48fvb02, 2, 8, false, false); +MCP47FEB02_CHIP_INFO(mcp48fvb04, 4, 8, true, false); +MCP47FEB02_CHIP_INFO(mcp48fvb08, 8, 8, true, false); +MCP47FEB02_CHIP_INFO(mcp48fvb11, 1, 10, false, false); +MCP47FEB02_CHIP_INFO(mcp48fvb12, 2, 10, false, false); +MCP47FEB02_CHIP_INFO(mcp48fvb14, 4, 10, true, false); +MCP47FEB02_CHIP_INFO(mcp48fvb18, 8, 10, true, false); +MCP47FEB02_CHIP_INFO(mcp48fvb21, 1, 12, false, false); +MCP47FEB02_CHIP_INFO(mcp48fvb22, 2, 12, false, false); +MCP47FEB02_CHIP_INFO(mcp48fvb24, 4, 12, true, false); +MCP47FEB02_CHIP_INFO(mcp48fvb28, 8, 12, true, false); + +static int mcp47feb02_spi_probe(struct spi_device *spi) +{ + const struct mcp47feb02_features *chip_features; + struct device *dev =3D &spi->dev; + struct regmap *regmap; + + chip_features =3D spi_get_device_match_data(spi); + if (!chip_features) + return -EINVAL; + + if (chip_features->have_eeprom) + regmap =3D devm_regmap_init_spi(spi, &mcp47feb02_regmap_config); + else + regmap =3D devm_regmap_init_spi(spi, &mcp47fvb02_regmap_config); + + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Error initializing SPI regma= p\n"); + + return mcp47feb02_common_probe(chip_features, regmap); +} + +static const struct spi_device_id mcp47feb02_spi_id[] =3D { + { "mcp48feb01", (kernel_ulong_t)&mcp48feb01_chip_features }, + { "mcp48feb02", (kernel_ulong_t)&mcp48feb02_chip_features }, + { "mcp48feb04", (kernel_ulong_t)&mcp48feb04_chip_features }, + { "mcp48feb08", (kernel_ulong_t)&mcp48feb08_chip_features }, + { "mcp48feb11", (kernel_ulong_t)&mcp48feb11_chip_features }, + { "mcp48feb12", (kernel_ulong_t)&mcp48feb12_chip_features }, + { "mcp48feb14", (kernel_ulong_t)&mcp48feb14_chip_features }, + { "mcp48feb18", (kernel_ulong_t)&mcp48feb18_chip_features }, + { "mcp48feb21", (kernel_ulong_t)&mcp48feb21_chip_features }, + { "mcp48feb22", (kernel_ulong_t)&mcp48feb22_chip_features }, + { "mcp48feb24", (kernel_ulong_t)&mcp48feb24_chip_features }, + { "mcp48feb28", (kernel_ulong_t)&mcp48feb28_chip_features }, + { "mcp48fvb01", (kernel_ulong_t)&mcp48fvb01_chip_features }, + { "mcp48fvb02", (kernel_ulong_t)&mcp48fvb02_chip_features }, + { "mcp48fvb04", (kernel_ulong_t)&mcp48fvb04_chip_features }, + { "mcp48fvb08", (kernel_ulong_t)&mcp48fvb08_chip_features }, + { "mcp48fvb11", (kernel_ulong_t)&mcp48fvb11_chip_features }, + { "mcp48fvb12", (kernel_ulong_t)&mcp48fvb12_chip_features }, + { "mcp48fvb14", (kernel_ulong_t)&mcp48fvb14_chip_features }, + { "mcp48fvb18", (kernel_ulong_t)&mcp48fvb18_chip_features }, + { "mcp48fvb21", (kernel_ulong_t)&mcp48fvb21_chip_features }, + { "mcp48fvb22", (kernel_ulong_t)&mcp48fvb22_chip_features }, + { "mcp48fvb24", (kernel_ulong_t)&mcp48fvb24_chip_features }, + { "mcp48fvb28", (kernel_ulong_t)&mcp48fvb28_chip_features }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp47feb02_spi_id); + +static const struct of_device_id mcp47feb02_of_spi_match[] =3D { + { .compatible =3D "microchip,mcp48feb01", .data =3D &mcp48feb01_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb02", .data =3D &mcp48feb02_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb04", .data =3D &mcp48feb04_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb08", .data =3D &mcp48feb08_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb11", .data =3D &mcp48feb11_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb12", .data =3D &mcp48feb12_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb14", .data =3D &mcp48feb14_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb18", .data =3D &mcp48feb18_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb21", .data =3D &mcp48feb21_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb22", .data =3D &mcp48feb22_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb24", .data =3D &mcp48feb24_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb28", .data =3D &mcp48feb28_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb01", .data =3D &mcp48fvb01_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb02", .data =3D &mcp48fvb02_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb04", .data =3D &mcp48fvb04_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb08", .data =3D &mcp48fvb08_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb11", .data =3D &mcp48fvb11_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb12", .data =3D &mcp48fvb12_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb14", .data =3D &mcp48fvb14_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb18", .data =3D &mcp48fvb18_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb21", .data =3D &mcp48fvb21_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb22", .data =3D &mcp48fvb22_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb24", .data =3D &mcp48fvb24_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb28", .data =3D &mcp48fvb28_chip_feat= ures }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp47feb02_of_spi_match); + +static struct spi_driver mcp47feb02_spi_driver =3D { + .driver =3D { + .name =3D "mcp47feb02", + .of_match_table =3D mcp47feb02_of_spi_match, + .pm =3D pm_sleep_ptr(&mcp47feb02_pm_ops), + }, + .probe =3D mcp47feb02_spi_probe, + .id_table =3D mcp47feb02_spi_id, +}; +module_spi_driver(mcp47feb02_spi_driver); + +MODULE_AUTHOR("Ariana Lazar "); +MODULE_DESCRIPTION("IIO driver for MCP48FEB02 Multi-Channel DAC with SPI i= nterface"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_MCP47FEB02"); diff --git a/drivers/iio/dac/mcp47feb02.h b/drivers/iio/dac/mcp47feb02.h new file mode 100644 index 0000000000000000000000000000000000000000..41de47166019ef23a89e531d7b0= 326273b14d175 --- /dev/null +++ b/drivers/iio/dac/mcp47feb02.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * IIO driver for MCP47FEB02 Multi-Channel DAC with I2C or SPI interface + * + * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries + * + * Author: Ariana Lazar + */ +#ifndef _MCP47FEB02_H_ +#define _MCP47FEB02_H_ + +#include +#include +#include +#include +#include + +/* Register addresses must be left shifted with 3 positions in order to ap= pend command mask */ +#define MCP47FEB02_DAC0_REG_ADDR 0x00 +#define MCP47FEB02_VREF_REG_ADDR 0x40 +#define MCP47FEB02_POWER_DOWN_REG_ADDR 0x48 +#define MCP47FEB02_DAC_CTRL_MASK GENMASK(1, 0) + +#define MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR 0x50 +#define MCP47FEB02_GAIN_BIT_MASK BIT(0) +#define MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK BIT(6) +#define MCP47FEB02_GAIN_BITS_MASK GENMASK(15, 8) + +#define MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR 0x58 + +#define MCP47FEB02_NV_DAC0_REG_ADDR 0x80 +#define MCP47FEB02_NV_VREF_REG_ADDR 0xC0 +#define MCP47FEB02_NV_POWER_DOWN_REG_ADDR 0xC8 +#define MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR 0xD0 +#define MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK GENMASK(7, 0) + +/* Voltage reference, Power-Down control register and DAC Wiperlock status= register fields */ +#define DAC_CTRL_MASK(ch) (GENMASK(1, 0) << (2 * (ch))) +#define DAC_CTRL_VAL(ch, val) ((val) << (2 * (ch))) + +/* Gain Control and I2C Slave Address Reguster fields */ +#define DAC_GAIN_MASK(ch) BIT(8 + (ch)) +#define DAC_GAIN_VAL(ch, val) ((val) * BIT(8 + (ch))) + +#define REG_ADDR(reg) ((reg) << 3) +#define NV_REG_ADDR(reg) ((NV_DAC_ADDR_OFFSET + (reg)) << 3) +#define READFLAG_MASK GENMASK(2, 1) + +#define MCP47FEB02_MAX_CH 8 +#define MCP47FEB02_MAX_SCALES_CH 3 +#define MCP47FEB02_DAC_WIPER_UNLOCKED 0 +#define MCP47FEB02_NORMAL_OPERATION 0 +#define MCP47FEB02_INTERNAL_BAND_GAP_uV 2440000 +#define NV_DAC_ADDR_OFFSET 0x10 + +/** + * struct mcp47feb02_features - chip specific data + * @name: device name + * @phys_channels: number of hardware channels + * @resolution: DAC resolution + * @have_ext_vref1: does the hardware have an the second external voltage = reference? + * @have_eeprom: does the hardware have an internal eeprom? + */ +struct mcp47feb02_features { + const char *name; + unsigned int phys_channels; + unsigned int resolution; + bool have_ext_vref1; + bool have_eeprom; +}; + +/* Macro used for generating chip features structures */ +#define MCP47FEB02_CHIP_INFO(_name, _channels, _res, _vref1, _eeprom) \ +static const struct mcp47feb02_features _name##_chip_features =3D { \ + .name =3D #_name, \ + .phys_channels =3D _channels, \ + .resolution =3D _res, \ + .have_ext_vref1 =3D _vref1, \ + .have_eeprom =3D _eeprom, \ +} + +enum mcp47feb02_vref_mode { + MCP47FEB02_VREF_VDD =3D 0, + MCP47FEB02_INTERNAL_BAND_GAP =3D 1, + MCP47FEB02_EXTERNAL_VREF_UNBUFFERED =3D 2, + MCP47FEB02_EXTERNAL_VREF_BUFFERED =3D 3, +}; + +enum mcp47feb02_scale { + MCP47FEB02_SCALE_VDD =3D 0, + MCP47FEB02_SCALE_GAIN_X1 =3D 1, + MCP47FEB02_SCALE_GAIN_X2 =3D 2, +}; + +enum mcp47feb02_gain_bit_mode { + MCP47FEB02_GAIN_BIT_X1 =3D 0, + MCP47FEB02_GAIN_BIT_X2 =3D 1, +}; + +/** + * struct mcp47feb02_channel_data - channel configuration + * @scale_avail: scales available for the channel based on current configu= ration + * @dac_data: DAC value + * @ref_mode: chosen voltage for reference + * @powerdown_mode: selected power-down mode + * @use_2x_gain: output driver gain control + * @powerdown: is false if the channel is in normal operation mode + */ +struct mcp47feb02_channel_data { + int *scale_avail; + u16 dac_data; + u8 ref_mode; + u8 powerdown_mode; + bool use_2x_gain; + bool powerdown; +}; + +/** + * struct mcp47feb02_data - chip configuration + * @chdata: options configured for each channel on the device + * @lock: prevents concurrent reads/writes to driver's state members + * @chip_features: pointer to features struct + * @scale_1: scales set on channels that are based on Vref1 + * @scale_0: scales set on channels that are based on Vref/Vref0 + * @active_channels_mask: enabled channels + * @regmap: regmap for directly accessing device register + * @labels: table with channels labels + * @phys_channels: physical channels on the device + * @vref1_buffered: Vref1 buffer is enabled + * @vref_buffered: Vref/Vref0 buffer is enabled + * @use_vref1: vref1-supply is defined + * @use_vref: vref-supply is defined + */ +struct mcp47feb02_data { + struct mcp47feb02_channel_data chdata[MCP47FEB02_MAX_CH]; + struct mutex lock; /* prevents concurrent reads/writes to driver's state = members */ + const struct mcp47feb02_features *chip_features; + int scale_1[2 * MCP47FEB02_MAX_SCALES_CH]; + int scale_0[2 * MCP47FEB02_MAX_SCALES_CH]; + unsigned long active_channels_mask; + struct regmap *regmap; + const char *labels[MCP47FEB02_MAX_CH]; + u16 phys_channels; + bool vref1_buffered; + bool vref_buffered; + bool use_vref1; + bool use_vref; +}; + +extern const struct regmap_config mcp47feb02_regmap_config; +extern const struct regmap_config mcp47fvb02_regmap_config; + +/* Properties shared by I2C and SPI families */ +int mcp47feb02_common_probe(const struct mcp47feb02_features *chip_feature= s, struct regmap *regmap); + +extern const struct dev_pm_ops mcp47feb02_pm_ops; + +#endif /* _MCP47FEB02_H_ */ --=20 2.43.0