From nobody Sat Apr 4 00:23:43 2026 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C93F362157 for ; Thu, 2 Apr 2026 18:36:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775155010; cv=none; b=li1XyylZ+BfJuHck0fa3ElI+rQ/C5in4KVexz66mOiT6Y3dVcwy5jNpeKwRYdnEfnXfN4mlV7aft0PF6+O7JFGRuSmjQxZ/ry+y7dl2O5lwN5V6MpFw89HG2SvsNDqx2/AwWiJLYo1jPv7nGmUhkmORYqe7V82zeyu6DzkGN3Dc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775155010; c=relaxed/simple; bh=Gl8cAlYokbfIAz8kiSzuCSqX0nTBtFhY6khwWvSjqtE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N/ohseYPNJtZPMVGu3TFY+f5dvpNemSXQ1xZK7nm2dA+a7Z+068kpxohsvf5HHL0lLQu3dCm+Nl5ltd93ID4tzRRYcS1MhxqOvjqdCrtdjQrHT0C1B3YPMVtRSD0NfoEV0Ythg5rD/iAP8CPO64buUmAfRz0M7p3uomN1hxl1u4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id D6D561F80041 for ; Thu, 2 Apr 2026 18:36:46 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 3BDE1B40132; Thu, 2 Apr 2026 18:36:46 +0000 (UTC) X-Spam-Level: * Received: from shepard (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id F1C86B40128; Thu, 2 Apr 2026 18:33:52 +0000 (UTC) From: Paul Kocialkowski To: dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Marek Vasut , Stefan Agner , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Lucas Stach , =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= , Marco Felsch , Liu Ying , Paul Kocialkowski Subject: [PATCH v2 2/2] drm: lcdif: Wait for vblank before disabling DMA Date: Thu, 2 Apr 2026 20:33:51 +0200 Message-ID: <20260402183351.3281123-3-paulk@sys-base.io> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260402183351.3281123-1-paulk@sys-base.io> References: <20260402183351.3281123-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is necessary to wait for the full frame to finish streaming through the DMA engine before we can safely disable it by removing the DISP_PARA_DISP_ON bit. Disabling it in-flight can leave the hardware confused and unable to resume streaming for the next frame. This causes the FIFO underrun and empty status bits to be set and a single solid color to be shown on the display, coming from one of the pixels of the previous frame. The issue occurs sporadically when a new mode is set, which triggers the crtc disable and enable paths. Setting the shadow load bit and waiting for it to be cleared by the DMA engine allows waiting for completion. The NXP BSP driver addresses this issue with a hardcoded 25 ms sleep. Fixes: 9db35bb349a0 ("drm: lcdif: Add support for i.MX8MP LCDIF variant") Signed-off-by: Paul Kocialkowski Co-developed-by: Lucas Stach --- drivers/gpu/drm/mxsfb/lcdif_kms.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c b/drivers/gpu/drm/mxsfb/lcdi= f_kms.c index a00c4f6d63f4..0d04a0028671 100644 --- a/drivers/gpu/drm/mxsfb/lcdif_kms.c +++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c @@ -375,14 +375,23 @@ static void lcdif_disable_controller(struct lcdif_drm= _private *lcdif) int ret; =20 reg =3D readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); + /* Disable the layer for DMA. */ reg &=3D ~CTRLDESCL0_5_EN; + /* + * It is necessary to wait for the full frame to finish streaming + * through the DMA engine before we can safely disable it by removing + * the DISP_PARA_DISP_ON bit. Disabling it in-flight can leave the + * hardware confused and unable to resume streaming for the next frame. + */ + reg |=3D CTRLDESCL0_5_SHADOW_LOAD_EN; writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); =20 + /* Wait for the frame to finish or timeout after 50 ms. */ ret =3D readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5, - reg, !(reg & CTRLDESCL0_5_EN), - 0, 36000); /* Wait ~2 frame times max */ + reg, !(reg & CTRLDESCL0_5_SHADOW_LOAD_EN), + 200, 50000); if (ret) - drm_err(lcdif->drm, "Failed to disable controller!\n"); + drm_err(lcdif->drm, "Timed out waiting for final vblank!\n"); =20 reg =3D readl(lcdif->base + LCDC_V8_DISP_PARA); reg &=3D ~DISP_PARA_DISP_ON; --=20 2.53.0