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The EIO GPIO block exposes only bank 0 and bank 1 to multiplexed I/O pins, providing a fixed total of 52 GPIO lines (2 banks =C3=97 26 pins). Enforce this hardware constraint by requiring exactly 52 entries in gpio-line-names for the EIO variant. Signed-off-by: Shubhrajyoti Datta --- .../devicetree/bindings/gpio/gpio-zynq.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Docume= ntation/devicetree/bindings/gpio/gpio-zynq.yaml index 5e2496379a3c..b8dd279753a5 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -16,6 +16,7 @@ properties: - xlnx,zynqmp-gpio-1.0 - xlnx,versal-gpio-1.0 - xlnx,pmc-gpio-1.0 + - xlnx,eio-gpio-1.0 =20 reg: maxItems: 1 @@ -30,7 +31,7 @@ properties: =20 gpio-line-names: description: strings describing the names of each gpio line - minItems: 58 + minItems: 52 maxItems: 174 =20 interrupt-controller: true @@ -89,6 +90,17 @@ allOf: minItems: 116 maxItems: 116 =20 + - if: + properties: + compatible: + enum: + - xlnx,eio-gpio-1.0 + then: + properties: + gpio-line-names: + minItems: 52 + maxItems: 52 + required: - compatible - reg --=20 2.34.1 From nobody Sun Jun 21 16:15:13 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012012.outbound.protection.outlook.com [40.107.200.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 596F03F211C; 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charset="utf-8" Add support for the EIO GPIO controller found on xa2ve3288 silicon. The EIO GPIO block provides access to multiplexed I/O pins exposed through the EIO interface. Only bank 0 and bank 1 are connected to external MIO pins, with 26 GPIOs per bank (52 GPIOs total). This change extends the Zynq GPIO driver to support the EIO GPIO variant. Signed-off-by: Shubhrajyoti Datta --- drivers/gpio/gpio-zynq.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index 571e366624d2..8118ae3412c2 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -25,6 +25,7 @@ #define VERSAL_GPIO_MAX_BANK 4 #define PMC_GPIO_MAX_BANK 5 #define VERSAL_UNUSED_BANKS 2 +#define EIO_GPIO_MAX_BANK 2 =20 #define ZYNQ_GPIO_BANK0_NGPIO 32 #define ZYNQ_GPIO_BANK1_NGPIO 22 @@ -818,6 +819,16 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = =3D { RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, zynq_gpio_runtime_resume, NULL) }; =20 +static const struct zynq_platform_data eio_gpio_def =3D { + .label =3D "eio_gpio", + .ngpio =3D 52, + .max_bank =3D EIO_GPIO_MAX_BANK, + .bank_min[0] =3D 0, + .bank_max[0] =3D 25, /* 0 to 25 are connected to MIOs (26 pins) */ + .bank_min[1] =3D 26, + .bank_max[1] =3D 51, /* Bank 1 are connected to MIOs (26 pins) */ +}; + static const struct zynq_platform_data versal_gpio_def =3D { .label =3D "versal_gpio", .quirks =3D GPIO_QUIRK_VERSAL, @@ -882,6 +893,7 @@ static const struct of_device_id zynq_gpio_of_match[] = =3D { { .compatible =3D "xlnx,zynqmp-gpio-1.0", .data =3D &zynqmp_gpio_def }, { .compatible =3D "xlnx,versal-gpio-1.0", .data =3D &versal_gpio_def }, { .compatible =3D "xlnx,pmc-gpio-1.0", .data =3D &pmc_gpio_def }, + { .compatible =3D "xlnx,eio-gpio-1.0", .data =3D &eio_gpio_def }, { /* end of table */ } }; MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); --=20 2.34.1