From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 87F0A3F210D; Thu, 2 Apr 2026 16:32:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147551; cv=none; b=f4EkDJQvjAHTFZVJKi4j62oGk1JjkDj25GwEHpsZqQGq9Yv3RVmdaQNSogL0n2DVNDBdeezG8kcmqJmG8bDrIX+liR58jgqKMSFOFfPVvB6MHqZ7Q0C8P/4LqYsYkHypBJhMCPxq7ninPyiF1E+TSNQxuUGw/jLa1AfwoygRcAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147551; c=relaxed/simple; bh=FqfhaaGORDtC0Sg2I4bOKsTv/3W4jMWHDL/jX1f+hs4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IvUvFX1JuEIPWmQG7cBHk/8RNc7OnyfBP2jnb7tCwuRnxX5Z+hKUC8oFfLea6uSa0gWETBcbifUn/1ssdgm0fphEXvrSMFzT4gh0wjOlFFcuFLQ1SSEw75yJ0468FIvyy2bza8lI+Sow9HBYzj80EfWRXLyHgcGSwj7UuTAuH9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: MZK23wQsS1SKIZPPmwTHWA== X-CSE-MsgGUID: /zlyM/o/TBmFwZ9L+vzFRw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Apr 2026 01:32:28 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.38]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9965540083E2; Fri, 3 Apr 2026 01:32:24 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 1/8] dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family Date: Thu, 2 Apr 2026 18:31:19 +0200 Message-ID: <20260402163126.12135-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/V2H, RZ/V2N, and RZ/G3E support external audio clock inputs (AUDIO_CLKA, AUDIO_CLKB, AUDIO_CLKC) that can be used by the Audio Clock Generator (ADG) to derive internal audio clocks. These clocks are optional and their frequencies are set by the board. Update the bindings to allow these optional clocks for all RZ/V2H family SoCs. Signed-off-by: John Madieu --- Changes: v3: No changes v2: Remove maxItems as it not needed with items lists. .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml= b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index f261445bf341..d9cf62f5224e 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -26,16 +26,24 @@ properties: maxItems: 1 =20 clocks: + minItems: 3 items: - description: AUDIO_EXTAL clock input - description: RTXIN clock input - description: QEXTAL clock input + - description: AUDIO_CLKA clock input + - description: AUDIO_CLKB clock input + - description: AUDIO_CLKC clock input =20 clock-names: + minItems: 3 items: - const: audio_extal - const: rtxin - const: qextal + - const: audio_clka + - const: audio_clkb + - const: audio_clkc =20 '#clock-cells': description: | --=20 2.25.1 From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF67E3F1658; Thu, 2 Apr 2026 16:32:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147556; cv=none; b=HmxQM9QrGWD6QndaK5ciIUGWZIoDtp/XfEyACO/3WyoVPdviMYhtbVBN74dVPYKmlNmORQDyqStHtUj6Bi3SulFsz0padfREG5pR8ms1VgKyt4wf4csWS0SOtWF6YLyiLMtTO6av3AHp+7tX16XBVUCSD/i0p2ia3RGYEFZV3wk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147556; c=relaxed/simple; bh=htY4R93hUQvqMTXVC9Z8Fx0GPcaYzhokDYmPN4X0WMc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZFep07e3cis7F5Df1YhnSWCpZvw1/PJqF2ATNNXecWlcPvC5e8d9q4aPLRQBXuVrXSxE9+gzj6tFm3gXFnDRNZ4qqEA6siSRqxZa0ObKgJXLyBGIBpnrCZgQ9S3oQCVprWx6J5wcehjrsEbEcGG1nbBpTE1qEU4AsqBq8HgvS3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: Crn6D5xmQh6e+cfVCKTxWg== X-CSE-MsgGUID: Juo0+x9UT6ylVpn8fFqUTw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Apr 2026 01:32:33 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.38]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0BD7D40083E2; Fri, 3 Apr 2026 01:32:28 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 2/8] clk: renesas: r9a09g047: Add audio clock and reset support Date: Thu, 2 Apr 2026 18:31:20 +0200 Message-ID: <20260402163126.12135-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock and reset entries for audio-related modules on the RZ/G3E SoC. Target modules are: - SSIU (Serial Sound Interface Unit) with SSI ch0-ch9 - SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1, CTU/MIX ch0-ch1 - ADMAC (Audio DMA Controller) - ADG (Audio Clock Generator) with divider input clocks and audio master clock outputs While at it, reorder plldty_div16 to group it with other plldty fixed dividers. Signed-off-by: John Madieu --- Changes: v3: No changes v2: No changes drivers/clk/renesas/r9a09g047-cpg.c | 129 +++++++++++++++++++++++++++- 1 file changed, 128 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a0= 9g047-cpg.c index e59ac4a05a7f..2d7e58f155f6 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -22,6 +22,9 @@ enum clk_ids { CLK_AUDIO_EXTAL, CLK_RTXIN, CLK_QEXTAL, + CLK_AUDIO_CLKA, + CLK_AUDIO_CLKB, + CLK_AUDIO_CLKC, =20 /* PLL Clocks */ CLK_PLLCM33, @@ -34,6 +37,8 @@ enum clk_ids { /* Internal Core Clocks */ CLK_PLLCM33_DIV3, CLK_PLLCM33_DIV4, + CLK_PLLCM33_DIV4_DDIV2, + CLK_PLLCM33_DIV4_DDIV2_DIV2, CLK_PLLCM33_DIV5, CLK_PLLCM33_DIV16, CLK_PLLCM33_GEAR, @@ -41,15 +46,19 @@ enum clk_ids { CLK_SMUX2_XSPI_CLK1, CLK_PLLCM33_XSPI, CLK_PLLCLN_DIV2, + CLK_PLLCLN_DIV4, CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, CLK_PLLCLN_DIV20, + CLK_PLLCLN_DIV32, CLK_PLLCLN_DIV64, CLK_PLLCLN_DIV256, CLK_PLLCLN_DIV1024, CLK_PLLDTY_ACPU, CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV2, + CLK_PLLDTY_DIV4, CLK_PLLDTY_DIV8, CLK_PLLDTY_RCPU, CLK_PLLDTY_RCPU_DIV4, @@ -64,6 +73,7 @@ enum clk_ids { CLK_PLLDTY_DIV16, CLK_PLLVDO_CRU0, CLK_PLLVDO_GPU, + CLK_CDIV5_MAINOSC, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -120,6 +130,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] = __initconst =3D { DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), DEF_INPUT("rtxin", CLK_RTXIN), DEF_INPUT("qextal", CLK_QEXTAL), + DEF_INPUT("audio_clka", CLK_AUDIO_CLKA), + DEF_INPUT("audio_clkb", CLK_AUDIO_CLKB), + DEF_INPUT("audio_clkc", CLK_AUDIO_CLKC), =20 /* PLL Clocks */ DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), @@ -135,6 +148,11 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), =20 + DEF_DDIV(".pllcm33_div4_ddiv2", CLK_PLLCM33_DIV4_DDIV2, CLK_PLLCM33_DIV4, + CDDIV0_DIVCTL1, dtable_2_64), + DEF_FIXED(".pllcm33_div4_ddiv2_div2", CLK_PLLCM33_DIV4_DDIV2_DIV2, + CLK_PLLCM33_DIV4_DDIV2, 1, 2), + DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVC= TL1, dtable_2_64), =20 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xs= pi_clk0), @@ -142,9 +160,11 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_= DIVCTL3, dtable_2_16), DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), + DEF_FIXED(".pllcln_div4", CLK_PLLCLN_DIV4, CLK_PLLCLN, 1, 4), DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), + DEF_FIXED(".pllcln_div32", CLK_PLLCLN_DIV32, CLK_PLLCLN, 1, 32), DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64), DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256), DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024), @@ -152,7 +172,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[]= __initconst =3D { DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, = 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), + DEF_FIXED(".plldty_div2", CLK_PLLDTY_DIV2, CLK_PLLDTY, 1, 2), + DEF_FIXED(".plldty_div4", CLK_PLLDTY_DIV4, CLK_PLLDTY, 1, 4), DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), + DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), =20 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_F= IX, 1, 2), @@ -164,9 +187,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] = __initconst =3D { DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_= gbe0_rxclk), DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), - DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, = 4), + DEF_FIXED(".cdiv5_mainosc", CLK_CDIV5_MAINOSC, CLK_QEXTAL, 1, 5), =20 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dta= ble_2_4), DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtabl= e_2_64), @@ -460,6 +483,96 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[]= __initconst =3D { BUS_MSTOP(3, BIT(4))), DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, BUS_MSTOP(2, BIT(15))), + DEF_MOD("ssif_clk", CLK_PLLCLN_DIV8, 15, 5, 7, 21, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("scu_clk", CLK_PLLCLN_DIV8, 15, 6, 7, 22, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("scu_clkx2", CLK_PLLCLN_DIV4, 15, 7, 7, 23, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("admac_clk", CLK_PLLCLN_DIV8, 15, 8, 7, 24, + BUS_MSTOP(2, BIT(5))), + DEF_MOD("adg_clks1", CLK_PLLCLN_DIV8, 15, 9, 7, 25, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_clk_200m", CLK_PLLCLN_DIV8, 15, 10, 7, 26, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_audio_clka", CLK_AUDIO_CLKA, 15, 11, 7, 27, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_audio_clkb", CLK_AUDIO_CLKB, 15, 12, 7, 28, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_audio_clkc", CLK_AUDIO_CLKC, 15, 13, 7, 29, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi0_clk", CLK_PLLCLN_DIV8, 22, 0, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi1_clk", CLK_PLLCLN_DIV8, 22, 1, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi2_clk", CLK_PLLCLN_DIV8, 22, 2, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi3_clk", CLK_PLLCLN_DIV8, 22, 3, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi4_clk", CLK_PLLCLN_DIV8, 22, 4, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi5_clk", CLK_PLLCLN_DIV8, 22, 5, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi6_clk", CLK_PLLCLN_DIV8, 22, 6, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi7_clk", CLK_PLLCLN_DIV8, 22, 7, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi8_clk", CLK_PLLCLN_DIV8, 22, 8, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("adg_ssi9_clk", CLK_PLLCLN_DIV8, 22, 9, -1, -1, + BUS_MSTOP(2, BIT(2))), + DEF_MOD("dvc0_clk", CLK_PLLCLN_DIV8, 23, 0, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("dvc1_clk", CLK_PLLCLN_DIV8, 23, 1, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("ctu0_mix0_clk", CLK_PLLCLN_DIV8, 23, 2, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("ctu1_mix1_clk", CLK_PLLCLN_DIV8, 23, 3, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src0_clk", CLK_PLLCLN_DIV8, 23, 4, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src1_clk", CLK_PLLCLN_DIV8, 23, 5, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src2_clk", CLK_PLLCLN_DIV8, 23, 6, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src3_clk", CLK_PLLCLN_DIV8, 23, 7, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src4_clk", CLK_PLLCLN_DIV8, 23, 8, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src5_clk", CLK_PLLCLN_DIV8, 23, 9, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src6_clk", CLK_PLLCLN_DIV8, 23, 10, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src7_clk", CLK_PLLCLN_DIV8, 23, 11, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src8_clk", CLK_PLLCLN_DIV8, 23, 12, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("src9_clk", CLK_PLLCLN_DIV8, 23, 13, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("scu_supply_clk", CLK_PLLCLN_DIV8, 23, 14, -1, -1, + BUS_MSTOP(2, BIT(0) | BIT(1))), + DEF_MOD("ssif_supply_clk", CLK_PLLCLN_DIV8, 24, 0, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi0_clk", CLK_PLLCLN_DIV8, 24, 1, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi1_clk", CLK_PLLCLN_DIV8, 24, 2, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi2_clk", CLK_PLLCLN_DIV8, 24, 3, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi3_clk", CLK_PLLCLN_DIV8, 24, 4, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi4_clk", CLK_PLLCLN_DIV8, 24, 5, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi5_clk", CLK_PLLCLN_DIV8, 24, 6, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi6_clk", CLK_PLLCLN_DIV8, 24, 7, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi7_clk", CLK_PLLCLN_DIV8, 24, 8, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi8_clk", CLK_PLLCLN_DIV8, 24, 9, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), + DEF_MOD("ssi9_clk", CLK_PLLCLN_DIV8, 24, 10, -1, -1, + BUS_MSTOP(2, BIT(3) | BIT(4))), }; =20 static const struct rzv2h_reset r9a09g047_resets[] __initconst =3D { @@ -538,6 +651,20 @@ static const struct rzv2h_reset r9a09g047_resets[] __i= nitconst =3D { DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */ DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */ + DEF_RST(14, 1, 6, 18), /* SSIF_0_ASYNC_RESET_SSI */ + DEF_RST(14, 2, 6, 19), /* SSIF_0_SYNC_RESET_SSI0 */ + DEF_RST(14, 3, 6, 20), /* SSIF_0_SYNC_RESET_SSI1 */ + DEF_RST(14, 4, 6, 21), /* SSIF_0_SYNC_RESET_SSI2 */ + DEF_RST(14, 5, 6, 22), /* SSIF_0_SYNC_RESET_SSI3 */ + DEF_RST(14, 6, 6, 23), /* SSIF_0_SYNC_RESET_SSI4 */ + DEF_RST(14, 7, 6, 24), /* SSIF_0_SYNC_RESET_SSI5 */ + DEF_RST(14, 8, 6, 25), /* SSIF_0_SYNC_RESET_SSI6 */ + DEF_RST(14, 9, 6, 26), /* SSIF_0_SYNC_RESET_SSI7 */ + DEF_RST(14, 10, 6, 27), /* SSIF_0_SYNC_RESET_SSI8 */ + DEF_RST(14, 11, 6, 28), /* SSIF_0_SYNC_RESET_SSI9 */ + DEF_RST(14, 12, 6, 29), /* SCU_RESET_SRU */ + DEF_RST(14, 13, 6, 30), /* ADMAC_ARESETN */ + DEF_RST(14, 14, 6, 31), /* ADG_RST_RESET_ADG */ DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; =20 --=20 2.25.1 From nobody Sun Jun 21 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 35GrQuCsQDeF3i1l+cRztw== X-CSE-MsgGUID: FJnIy14eSa+XNGhA9KjrOQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Apr 2026 01:32:37 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.38]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9477A40083E2; Fri, 3 Apr 2026 01:32:33 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 3/8] arm64: dts: renesas: rzv2h: Add audio clock inputs Date: Thu, 2 Apr 2026 18:31:21 +0200 Message-ID: <20260402163126.12135-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Model external audio clock inputs as CPG input clocks for RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG) to derive internal audio clocks from these external sources. The clock frequencies are board-specific and must be overridden in the board DTS files. Signed-off-by: John Madieu --- Changes: v3: No changes v2: No changes arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 27 ++++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 27 ++++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 27 ++++++++++++++++++++-- 3 files changed, 75 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index 95a4e30a064d..1ff48c8f98e1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -14,6 +14,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -270,8 +291,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g047-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index 40525470194e..d2ac78006f15 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -32,6 +32,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -293,8 +314,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g056-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 9581af58024e..e15b47dc93d4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -14,6 +14,27 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + audio_clka: audio-clka { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkb: audio-clkb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + audio_clkc: audio-clkc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + audio_extal_clk: audio-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -275,8 +296,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible =3D "renesas,r9a09g057-cpg"; reg =3D <0 0x10420000 0 0x10000>; - clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names =3D "audio_extal", "rtxin", "qextal"; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>; + clock-names =3D "audio_extal", "rtxin", "qextal", + "audio_clka", "audio_clkb", "audio_clkc"; #clock-cells =3D <2>; #reset-cells =3D <1>; #power-domain-cells =3D <0>; --=20 2.25.1 From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2BEEA3F1673; Thu, 2 Apr 2026 16:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147565; cv=none; b=QEgCo/pYiiRaCxWUdyIKuKKVNvL8qurKnEtNFnFCrAx0qicj9V1NeXe6loS+DCZFXRsIIcHIVcBRVVyM5MshSpbf8VwrQ/J4f007eWGS4kFvWzVqXs0REHO8MekkDYw710wJKc6BWuj2hPrN8sAQdQIs61pvodo0RVNfwEXPKyg= ARC-Message-Signature: i=1; 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Fri, 3 Apr 2026 01:32:38 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 4/8] arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support Date: Thu, 2 Apr 2026 18:31:22 +0200 Message-ID: <20260402163126.12135-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the rzg3e_sound node for the RZ/G3E SoC with all sub-components: - SSI (Serial Sound Interface) units 0-9 - SSIU (Serial Sound Interface Unit) units 0-27 - SRC (Sample Rate Converter) units 0-9 - CTU (Channel Transfer Unit) units 0-7 - DVC (Digital Volume Control) units 0-1 - MIX (Mixer) units 0-1 Wire up all 5 DMA controllers (dmac0-dmac4) for each audio sub-node with repeated channel names, so that the DMA core can pick the first available controller. Signed-off-by: John Madieu --- Changes: v3: Typo fix in commit description v2: - Remove 2-cells specifier on audio DMA assignment - Do not update DMAC #dma-cells anymore=20 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 502 +++++++++++++++++++++ 1 file changed, 502 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index 1ff48c8f98e1..b1e567d71c26 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -918,6 +918,508 @@ rsci9: serial@12803000 { status =3D "disabled"; }; =20 + snd_rzg3e: sound@13c00000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells =3D <0>; <&snd_rzg3e>; + * Multi DAI : #sound-dai-cells =3D <1>; <&snd_rzg3e N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells =3D <0>; <&snd_rzg3e>; + * clkout0/1/2/3: #clock-cells =3D <1>; <&snd_rzg3e N>; + */ + compatible =3D "renesas,r9a09g047-sound"; + reg =3D <0 0x13c00000 0 0x10000>, /* SCU */ + <0 0x13c20000 0 0x10000>, /* ADG */ + <0 0x13c30000 0 0x1000>, /* SSIU */ + <0 0x13c31000 0 0x1F000>, /* SSI */ + <0 0x13c50000 0 0x10000>; /* Audio DMAC peri peri */ + reg-names =3D "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks =3D <&cpg CPG_MOD 245>, + <&cpg CPG_MOD 394>, + <&cpg CPG_MOD 393>, + <&cpg CPG_MOD 392>, + <&cpg CPG_MOD 391>, + <&cpg CPG_MOD 390>, + <&cpg CPG_MOD 389>, + <&cpg CPG_MOD 388>, + <&cpg CPG_MOD 387>, + <&cpg CPG_MOD 386>, + <&cpg CPG_MOD 385>, + <&cpg CPG_MOD 381>, + <&cpg CPG_MOD 380>, + <&cpg CPG_MOD 379>, + <&cpg CPG_MOD 378>, + <&cpg CPG_MOD 377>, + <&cpg CPG_MOD 376>, + <&cpg CPG_MOD 375>, + <&cpg CPG_MOD 374>, + <&cpg CPG_MOD 373>, + <&cpg CPG_MOD 372>, + <&cpg CPG_MOD 371>, + <&cpg CPG_MOD 370>, + <&cpg CPG_MOD 371>, + <&cpg CPG_MOD 370>, + <&cpg CPG_MOD 368>, + <&cpg CPG_MOD 369>, + <&cpg CPG_MOD 251>, + <&cpg CPG_MOD 252>, + <&cpg CPG_MOD 253>, + <&cpg CPG_MOD 250>, + <&cpg CPG_MOD 384>, + <&cpg CPG_MOD 246>, + <&cpg CPG_MOD 247>, + <&cpg CPG_MOD 382>, + <&cpg CPG_MOD 361>, + <&cpg CPG_MOD 360>, + <&cpg CPG_MOD 359>, + <&cpg CPG_MOD 358>, + <&cpg CPG_MOD 357>, + <&cpg CPG_MOD 356>, + <&cpg CPG_MOD 355>, + <&cpg CPG_MOD 354>, + <&cpg CPG_MOD 353>, + <&cpg CPG_MOD 352>, + <&cpg CPG_MOD 248>, + <&cpg CPG_MOD 249>; + clock-names =3D "ssi-all", + "ssi.9", "ssi.8", + "ssi.7", "ssi.6", + "ssi.5", "ssi.4", + "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", + "src.7", "src.6", + "src.5", "src.4", + "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", + "clk_c", "clk_i", + "ssif_supply", + "scu", "scu_x2", + "scu_supply", + "adg.ssi.9", "adg.ssi.8", + "adg.ssi.7", "adg.ssi.6", + "adg.ssi.5", "adg.ssi.4", + "adg.ssi.3", "adg.ssi.2", + "adg.ssi.1", "adg.ssi.0", + "audmapp", "adg"; + power-domains =3D <&cpg>; + resets =3D <&cpg 225>, + <&cpg 235>, + <&cpg 234>, + <&cpg 233>, + <&cpg 232>, + <&cpg 231>, + <&cpg 230>, + <&cpg 229>, + <&cpg 228>, + <&cpg 227>, + <&cpg 226>, + <&cpg 236>, + <&cpg 238>, + <&cpg 237>; + reset-names =3D "ssi-all", + "ssi.9", "ssi.8", + "ssi.7", "ssi.6", + "ssi.5", "ssi.4", + "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "scu", "adg", + "audmapp"; + status =3D "disabled"; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas =3D <&dmac0 0x1db3>, <&dmac1 0x1db3>, + <&dmac2 0x1db3>, <&dmac3 0x1db3>, + <&dmac4 0x1db3>; + dma-names =3D "tx", "tx", "tx", "tx", "tx"; + }; + dvc1: dvc-1 { + dmas =3D <&dmac0 0x1db4>, <&dmac1 0x1db4>, + <&dmac2 0x1db4>, <&dmac3 0x1db4>, + <&dmac4 0x1db4>; + dma-names =3D "tx", "tx", "tx", "tx", "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts =3D ; + dmas =3D <&dmac0 0x1d9f>, <&dmac0 0x1da9>, + <&dmac1 0x1d9f>, <&dmac1 0x1da9>, + <&dmac2 0x1d9f>, <&dmac2 0x1da9>, + <&dmac3 0x1d9f>, <&dmac3 0x1da9>, + <&dmac4 0x1d9f>, <&dmac4 0x1da9>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src1: src-1 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da0>, <&dmac0 0x1daa>, + <&dmac1 0x1da0>, <&dmac1 0x1daa>, + <&dmac2 0x1da0>, <&dmac2 0x1daa>, + <&dmac3 0x1da0>, <&dmac3 0x1daa>, + <&dmac4 0x1da0>, <&dmac4 0x1daa>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src2: src-2 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da1>, <&dmac0 0x1dab>, + <&dmac1 0x1da1>, <&dmac1 0x1dab>, + <&dmac2 0x1da1>, <&dmac2 0x1dab>, + <&dmac3 0x1da1>, <&dmac3 0x1dab>, + <&dmac4 0x1da1>, <&dmac4 0x1dab>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src3: src-3 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da2>, <&dmac0 0x1dac>, + <&dmac1 0x1da2>, <&dmac1 0x1dac>, + <&dmac2 0x1da2>, <&dmac2 0x1dac>, + <&dmac3 0x1da2>, <&dmac3 0x1dac>, + <&dmac4 0x1da2>, <&dmac4 0x1dac>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src4: src-4 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da3>, <&dmac0 0x1dad>, + <&dmac1 0x1da3>, <&dmac1 0x1dad>, + <&dmac2 0x1da3>, <&dmac2 0x1dad>, + <&dmac3 0x1da3>, <&dmac3 0x1dad>, + <&dmac4 0x1da3>, <&dmac4 0x1dad>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src5: src-5 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da4>, <&dmac0 0x1dae>, + <&dmac1 0x1da4>, <&dmac1 0x1dae>, + <&dmac2 0x1da4>, <&dmac2 0x1dae>, + <&dmac3 0x1da4>, <&dmac3 0x1dae>, + <&dmac4 0x1da4>, <&dmac4 0x1dae>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src6: src-6 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da5>, <&dmac0 0x1daf>, + <&dmac1 0x1da5>, <&dmac1 0x1daf>, + <&dmac2 0x1da5>, <&dmac2 0x1daf>, + <&dmac3 0x1da5>, <&dmac3 0x1daf>, + <&dmac4 0x1da5>, <&dmac4 0x1daf>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src7: src-7 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da6>, <&dmac0 0x1db0>, + <&dmac1 0x1da6>, <&dmac1 0x1db0>, + <&dmac2 0x1da6>, <&dmac2 0x1db0>, + <&dmac3 0x1da6>, <&dmac3 0x1db0>, + <&dmac4 0x1da6>, <&dmac4 0x1db0>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src8: src-8 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da7>, <&dmac0 0x1db1>, + <&dmac1 0x1da7>, <&dmac1 0x1db1>, + <&dmac2 0x1da7>, <&dmac2 0x1db1>, + <&dmac3 0x1da7>, <&dmac3 0x1db1>, + <&dmac4 0x1da7>, <&dmac4 0x1db1>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + src9: src-9 { + interrupts =3D ; + dmas =3D <&dmac0 0x1da8>, <&dmac0 0x1db2>, + <&dmac1 0x1da8>, <&dmac1 0x1db2>, + <&dmac2 0x1da8>, <&dmac2 0x1db2>, + <&dmac3 0x1da8>, <&dmac3 0x1db2>, + <&dmac4 0x1da8>, <&dmac4 0x1db2>; + dma-names =3D "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "= tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts =3D ; + }; + ssi1: ssi-1 { + interrupts =3D ; + }; + ssi2: ssi-2 { + interrupts =3D ; + }; + ssi3: ssi-3 { + interrupts =3D ; + }; + ssi4: ssi-4 { + interrupts =3D ; + }; + ssi5: ssi-5 { + interrupts =3D ; + }; + ssi6: ssi-6 { + interrupts =3D ; + }; + ssi7: ssi-7 { + interrupts =3D ; + }; + ssi8: ssi-8 { + interrupts =3D ; + }; + ssi9: ssi-9 { + interrupts =3D ; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas =3D <&dmac0 0x1d61>, <&dmac0 0x1d62>, + <&dmac1 0x1d61>, <&dmac1 0x1d62>, + <&dmac2 0x1d61>, <&dmac2 0x1d62>, + <&dmac3 0x1d61>, <&dmac3 0x1d62>, + <&dmac4 0x1d61>, <&dmac4 0x1d62>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu01: ssiu-1 { + dmas =3D <&dmac0 0x1d63>, <&dmac0 0x1d64>, + <&dmac1 0x1d63>, <&dmac1 0x1d64>, + <&dmac2 0x1d63>, <&dmac2 0x1d64>, + <&dmac3 0x1d63>, <&dmac3 0x1d64>, + <&dmac4 0x1d63>, <&dmac4 0x1d64>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu02: ssiu-2 { + dmas =3D <&dmac0 0x1d65>, <&dmac0 0x1d66>, + <&dmac1 0x1d65>, <&dmac1 0x1d66>, + <&dmac2 0x1d65>, <&dmac2 0x1d66>, + <&dmac3 0x1d65>, <&dmac3 0x1d66>, + <&dmac4 0x1d65>, <&dmac4 0x1d66>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu03: ssiu-3 { + dmas =3D <&dmac0 0x1d67>, <&dmac0 0x1d68>, + <&dmac1 0x1d67>, <&dmac1 0x1d68>, + <&dmac2 0x1d67>, <&dmac2 0x1d68>, + <&dmac3 0x1d67>, <&dmac3 0x1d68>, + <&dmac4 0x1d67>, <&dmac4 0x1d68>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu10: ssiu-4 { + dmas =3D <&dmac0 0x1d69>, <&dmac0 0x1d6a>, + <&dmac1 0x1d69>, <&dmac1 0x1d6a>, + <&dmac2 0x1d69>, <&dmac2 0x1d6a>, + <&dmac3 0x1d69>, <&dmac3 0x1d6a>, + <&dmac4 0x1d69>, <&dmac4 0x1d6a>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu11: ssiu-5 { + dmas =3D <&dmac0 0x1d6b>, <&dmac0 0x1d6c>, + <&dmac1 0x1d6b>, <&dmac1 0x1d6c>, + <&dmac2 0x1d6b>, <&dmac2 0x1d6c>, + <&dmac3 0x1d6b>, <&dmac3 0x1d6c>, + <&dmac4 0x1d6b>, <&dmac4 0x1d6c>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu12: ssiu-6 { + dmas =3D <&dmac0 0x1d6d>, <&dmac0 0x1d6e>, + <&dmac1 0x1d6d>, <&dmac1 0x1d6e>, + <&dmac2 0x1d6d>, <&dmac2 0x1d6e>, + <&dmac3 0x1d6d>, <&dmac3 0x1d6e>, + <&dmac4 0x1d6d>, <&dmac4 0x1d6e>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu13: ssiu-7 { + dmas =3D <&dmac0 0x1d6f>, <&dmac0 0x1d70>, + <&dmac1 0x1d6f>, <&dmac1 0x1d70>, + <&dmac2 0x1d6f>, <&dmac2 0x1d70>, + <&dmac3 0x1d6f>, <&dmac3 0x1d70>, + <&dmac4 0x1d6f>, <&dmac4 0x1d70>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu20: ssiu-8 { + dmas =3D <&dmac0 0x1d71>, <&dmac0 0x1d72>, + <&dmac1 0x1d71>, <&dmac1 0x1d72>, + <&dmac2 0x1d71>, <&dmac2 0x1d72>, + <&dmac3 0x1d71>, <&dmac3 0x1d72>, + <&dmac4 0x1d71>, <&dmac4 0x1d72>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu21: ssiu-9 { + dmas =3D <&dmac0 0x1d73>, <&dmac0 0x1d74>, + <&dmac1 0x1d73>, <&dmac1 0x1d74>, + <&dmac2 0x1d73>, <&dmac2 0x1d74>, + <&dmac3 0x1d73>, <&dmac3 0x1d74>, + <&dmac4 0x1d73>, <&dmac4 0x1d74>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu22: ssiu-10 { + dmas =3D <&dmac0 0x1d75>, <&dmac0 0x1d76>, + <&dmac1 0x1d75>, <&dmac1 0x1d76>, + <&dmac2 0x1d75>, <&dmac2 0x1d76>, + <&dmac3 0x1d75>, <&dmac3 0x1d76>, + <&dmac4 0x1d75>, <&dmac4 0x1d76>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu23: ssiu-11 { + dmas =3D <&dmac0 0x1d77>, <&dmac0 0x1d78>, + <&dmac1 0x1d77>, <&dmac1 0x1d78>, + <&dmac2 0x1d77>, <&dmac2 0x1d78>, + <&dmac3 0x1d77>, <&dmac3 0x1d78>, + <&dmac4 0x1d77>, <&dmac4 0x1d78>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu30: ssiu-12 { + dmas =3D <&dmac0 0x1d79>, <&dmac0 0x1d7a>, + <&dmac1 0x1d79>, <&dmac1 0x1d7a>, + <&dmac2 0x1d79>, <&dmac2 0x1d7a>, + <&dmac3 0x1d79>, <&dmac3 0x1d7a>, + <&dmac4 0x1d79>, <&dmac4 0x1d7a>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu31: ssiu-13 { + dmas =3D <&dmac0 0x1d7b>, <&dmac0 0x1d7c>, + <&dmac1 0x1d7b>, <&dmac1 0x1d7c>, + <&dmac2 0x1d7b>, <&dmac2 0x1d7c>, + <&dmac3 0x1d7b>, <&dmac3 0x1d7c>, + <&dmac4 0x1d7b>, <&dmac4 0x1d7c>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu32: ssiu-14 { + dmas =3D <&dmac0 0x1d7d>, <&dmac0 0x1d7e>, + <&dmac1 0x1d7d>, <&dmac1 0x1d7e>, + <&dmac2 0x1d7d>, <&dmac2 0x1d7e>, + <&dmac3 0x1d7d>, <&dmac3 0x1d7e>, + <&dmac4 0x1d7d>, <&dmac4 0x1d7e>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu33: ssiu-15 { + dmas =3D <&dmac0 0x1d7f>, <&dmac0 0x1d80>, + <&dmac1 0x1d7f>, <&dmac1 0x1d80>, + <&dmac2 0x1d7f>, <&dmac2 0x1d80>, + <&dmac3 0x1d7f>, <&dmac3 0x1d80>, + <&dmac4 0x1d7f>, <&dmac4 0x1d80>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu40: ssiu-16 { + dmas =3D <&dmac0 0x1d81>, <&dmac0 0x1d82>, + <&dmac1 0x1d81>, <&dmac1 0x1d82>, + <&dmac2 0x1d81>, <&dmac2 0x1d82>, + <&dmac3 0x1d81>, <&dmac3 0x1d82>, + <&dmac4 0x1d81>, <&dmac4 0x1d82>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu41: ssiu-17 { + dmas =3D <&dmac0 0x1d83>, <&dmac0 0x1d84>, + <&dmac1 0x1d83>, <&dmac1 0x1d84>, + <&dmac2 0x1d83>, <&dmac2 0x1d84>, + <&dmac3 0x1d83>, <&dmac3 0x1d84>, + <&dmac4 0x1d83>, <&dmac4 0x1d84>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu42: ssiu-18 { + dmas =3D <&dmac0 0x1d85>, <&dmac0 0x1d86>, + <&dmac1 0x1d85>, <&dmac1 0x1d86>, + <&dmac2 0x1d85>, <&dmac2 0x1d86>, + <&dmac3 0x1d85>, <&dmac3 0x1d86>, + <&dmac4 0x1d85>, <&dmac4 0x1d86>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu43: ssiu-19 { + dmas =3D <&dmac0 0x1d87>, <&dmac0 0x1d88>, + <&dmac1 0x1d87>, <&dmac1 0x1d88>, + <&dmac2 0x1d87>, <&dmac2 0x1d88>, + <&dmac3 0x1d87>, <&dmac3 0x1d88>, + <&dmac4 0x1d87>, <&dmac4 0x1d88>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu50: ssiu-20 { + dmas =3D <&dmac0 0x1d89>, <&dmac0 0x1d8a>, + <&dmac1 0x1d89>, <&dmac1 0x1d8a>, + <&dmac2 0x1d89>, <&dmac2 0x1d8a>, + <&dmac3 0x1d89>, <&dmac3 0x1d8a>, + <&dmac4 0x1d89>, <&dmac4 0x1d8a>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu60: ssiu-21 { + dmas =3D <&dmac0 0x1d8b>, <&dmac0 0x1d8c>, + <&dmac1 0x1d8b>, <&dmac1 0x1d8c>, + <&dmac2 0x1d8b>, <&dmac2 0x1d8c>, + <&dmac3 0x1d8b>, <&dmac3 0x1d8c>, + <&dmac4 0x1d8b>, <&dmac4 0x1d8c>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu70: ssiu-22 { + dmas =3D <&dmac0 0x1d8d>, <&dmac0 0x1d8e>, + <&dmac1 0x1d8d>, <&dmac1 0x1d8e>, + <&dmac2 0x1d8d>, <&dmac2 0x1d8e>, + <&dmac3 0x1d8d>, <&dmac3 0x1d8e>, + <&dmac4 0x1d8d>, <&dmac4 0x1d8e>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu80: ssiu-23 { + dmas =3D <&dmac0 0x1d8f>, <&dmac0 0x1d90>, + <&dmac1 0x1d8f>, <&dmac1 0x1d90>, + <&dmac2 0x1d8f>, <&dmac2 0x1d90>, + <&dmac3 0x1d8f>, <&dmac3 0x1d90>, + <&dmac4 0x1d8f>, <&dmac4 0x1d90>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu90: ssiu-24 { + dmas =3D <&dmac0 0x1d91>, <&dmac0 0x1d92>, + <&dmac1 0x1d91>, <&dmac1 0x1d92>, + <&dmac2 0x1d91>, <&dmac2 0x1d92>, + <&dmac3 0x1d91>, <&dmac3 0x1d92>, + <&dmac4 0x1d91>, <&dmac4 0x1d92>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu91: ssiu-25 { + dmas =3D <&dmac0 0x1d93>, <&dmac0 0x1d94>, + <&dmac1 0x1d93>, <&dmac1 0x1d94>, + <&dmac2 0x1d93>, <&dmac2 0x1d94>, + <&dmac3 0x1d93>, <&dmac3 0x1d94>, + <&dmac4 0x1d93>, <&dmac4 0x1d94>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu92: ssiu-26 { + dmas =3D <&dmac0 0x1d95>, <&dmac0 0x1d96>, + <&dmac1 0x1d95>, <&dmac1 0x1d96>, + <&dmac2 0x1d95>, <&dmac2 0x1d96>, + <&dmac3 0x1d95>, <&dmac3 0x1d96>, + <&dmac4 0x1d95>, <&dmac4 0x1d96>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + ssiu93: ssiu-27 { + dmas =3D <&dmac0 0x1d97>, <&dmac0 0x1d98>, + <&dmac1 0x1d97>, <&dmac1 0x1d98>, + <&dmac2 0x1d97>, <&dmac2 0x1d98>, + <&dmac3 0x1d97>, <&dmac3 0x1d98>, + <&dmac4 0x1d97>, <&dmac4 0x1d98>; + dma-names =3D "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "= rx"; + }; + }; + }; + wdt1: watchdog@14400000 { compatible =3D "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg =3D <0 0x14400000 0 0x400>; --=20 2.25.1 From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C8C973F210D; Thu, 2 Apr 2026 16:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147569; cv=none; b=r3iJDINT70a7GepfwXm52ym4+VlVya6zaWV/Ach6tPShoaJrrMYuevqUpnZSle3mdOV9yVf1u7Xir/nMxF4uYTmfILfTdYVhKuv02BOYVVR95Fkzy09NC5+fgCQqUwvjeaLV64NBxaicivwNIKbyV8c2Ahs3oky8vLeQ9a9f8qk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147569; c=relaxed/simple; bh=ufQMTqHmHKAyAaEq0yNSPDr1z4Qa3trGoEdPMrHKtfo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kScK5BOfUpDyevxUFaOibdi+L9jPj7OmR3EmaNGemXuCLyhKtvd1A3waxjJ9+lnuxjIkT6eZNCsWCJzzZ+ZD1RcAE3OW3ssSP2biJeLR2MJyLDWBTYr54QSLRFL8s41GQbIsYi3xPtq1hXAPcODdWzsxVoiDtQO9Ld4f2iMKidA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: sE2rvK1dQyqvJPFX2YOkNQ== X-CSE-MsgGUID: ZyNl5g2YSMaBt9vkVWJT6w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Apr 2026 01:32:47 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.38]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 08B2A40083E2; Fri, 3 Apr 2026 01:32:42 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 5/8] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator Date: Thu, 2 Apr 2026 18:31:23 +0200 Message-ID: <20260402163126.12135-6-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Renesas 5P35023 (Versa3) programmable clock generator on the I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the audio subsystem. The Versa3 provides the following audio-related clock outputs: - Output 0: 24MHz (reference) - Output 1: 12.288MHz (audio, 48kHz family) - Output 2: 11.2896MHz (audio, 44.1kHz family) - Output 3: 12.288MHz (audio) These clocks are required for the audio codec found on the RZ/G3E SMARC EVK. Signed-off-by: John Madieu --- Changes: v3: No changes v2: No changes .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index d978619155d2..89428c804efb 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -77,6 +77,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others { regulator-always-on; }; =20 + x2: x2-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + /* 32.768kHz crystal */ x3: x3-clock { compatible =3D "fixed-clock"; @@ -130,6 +136,20 @@ raa215300: pmic@12 { =20 interrupts-extended =3D <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING= >; }; + + versa3: clock-generator@68 { + compatible =3D "renesas,5p35023"; + reg =3D <0x68>; + #clock-cells =3D <1>; + clocks =3D <&x2>; + + assigned-clocks =3D <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates =3D <24000000>, <12288000>, + <11289600>, <12288000>, + <25000000>, <25000000>; + }; }; =20 &i3c { --=20 2.25.1 From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 94B5E3F1665; Thu, 2 Apr 2026 16:32:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147574; cv=none; b=DknPQd6KW582JmPOZZfLM2K2NeZJwJQPCJa0cU3jSy6Z1tmD9G+Kqo9NHYWcSYQru1JpyI1NdQSmPOEs73q4fBVjkCnmVT3C+SIlsEQiD7XRY3vDq59ZSqImXtp2jNXpYPRIBfz+Fk8zhrPUhxPj7qRlcSlEtXjBk2pqDhNdEos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147574; c=relaxed/simple; bh=fE1StIyC+9RQx4VOXzJYI+ix8JGlW3+LFC2fh9goOSY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uwIKGn/kEEJsVabm3KOhcC6bC4QrW9Vc59wyaTG9tqjNtPEvHqQy0bBU9gYnEC0ejikha4k9mvMoN1RIH/aq50ok7b04fYgPDh7conGIJIN1TqSN1v/UZZ6Yu2efoP1vKg8221k6M+Y8lgwAS0NDY54sF2+asah7Dz9YaJ7yEbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: FIPvZWcwRFaz3ffn2JynIA== X-CSE-MsgGUID: WmBLw7Q7QyG36IQClNFzqA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Apr 2026 01:32:51 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.38]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9D50F4009A30; Fri, 3 Apr 2026 01:32:47 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 6/8] arm64: dts: renesas: rzg3e-smarc-som: Add I2C1 support Date: Thu, 2 Apr 2026 18:31:24 +0200 Message-ID: <20260402163126.12135-7-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add and enable I2C1 controller support with pin configuration. The I2C1 bus is routed to the carrier board and used for peripherals such as the audio codec. Signed-off-by: John Madieu --- Changes: v3: No changes v2: No changes arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 89428c804efb..493f6783d583 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -32,6 +32,7 @@ / { aliases { ethernet0 =3D ð0; ethernet1 =3D ð1; + i2c1 =3D &i2c1; i2c2 =3D &i2c2; mmc0 =3D &sdhi0; mmc2 =3D &sdhi2; @@ -118,6 +119,12 @@ &gpu { mali-supply =3D <®_vdd0p8v_others>; }; =20 +&i2c1 { + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &i2c2 { pinctrl-0 =3D <&i2c2_pins>; pinctrl-names =3D "default"; @@ -255,6 +262,11 @@ ctrl { }; }; =20 + i2c1_pins: i2c1 { + pinmux =3D , /* SCL1 */ + ; /* SDA1 */ + }; + i2c2_pins: i2c { pinmux =3D , /* SCL2 */ ; /* SDA2 */ --=20 2.25.1 From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B66243F1655; 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charset="utf-8" Add pinmux definitions for SSI3/SSI4 audio interface on RZ/G3E SMARC SoM: - sound_clk_pins: AUDIO_CLKB and AUDIO_CLKC clock outputs - sound_pins: SSI3_SCK, SSI3_WS, SSI3_SDATA (playback) and SSI4_SDATA (capture) Signed-off-by: John Madieu --- Changes: v3: No changes v2: No changes arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index 493f6783d583..f4532a06cc31 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -353,6 +353,18 @@ sd2-pwen { }; }; =20 + sound_clk_pins: sound_clk { + pinmux =3D , /* AUDIO_CLKB */ + ; /* AUDIO_CLKC */ + }; + + sound_pins: sound { + pinmux =3D , /* SSI3_SCK */ + , /* SSI3_WS */ + , /* SSI3_SDATA */ + ; /* SSI4_SDATA */ + }; + xspi_pins: xspi0 { pinmux =3D , /* XSPI0_IO0 */ , /* XSPI0_IO1 */ --=20 2.25.1 From nobody Sun Jun 21 16:15:13 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5026E3F54B7; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: gKzI0NIYTzWKjtHzPkgDcw== X-CSE-MsgGUID: orBfnzr0SiqkbGM4lon7zQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Apr 2026 01:33:01 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.38]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1BE7F40083E2; Fri, 3 Apr 2026 01:32:56 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Madieu Subject: [PATCh v3 8/8] arm64: dts: renesas: r9a09g047e57-smarc: add DA7212 audio codec support Date: Thu, 2 Apr 2026 18:31:26 +0200 Message-ID: <20260402163126.12135-9-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> References: <20260402163126.12135-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E SMARC board has a DA7212 audio codec connected via I2C1 for sound input/output using SSI3/SSI4 where: - The codec receives its master clock from the Versa3 clock generator present on the SoM - SSI4 shares clock pins with SSI3 to provide a separate data line for full-duplex audio capture. Enable audio support on RZ/G3E SMARC2 EVK boards with a DA7212 audio codec. Signed-off-by: John Madieu --- Changes: v3: No changes v2: No changes .../boot/dts/renesas/r9a09g047e57-smarc.dts | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g047e57-smarc.dts index 6372f582a7c4..7defd342294a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -32,6 +32,37 @@ #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" =20 +/* + * SSI-DA7212 + * + * These commands are required when Playback/Capture + * + * amixer -q cset name=3D'Aux Switch' on + * amixer -q cset name=3D'Mixin Left Aux Left Switch' on + * amixer -q cset name=3D'Mixin Right Aux Right Switch' on + * amixer -q cset name=3D'ADC Switch' on + * amixer -q cset name=3D'Mixout Right Mixin Right Switch' off + * amixer -q cset name=3D'Mixout Left Mixin Left Switch' off + * amixer -q cset name=3D'Headphone Volume' 70% + * amixer -q cset name=3D'Headphone Switch' on + * amixer -q cset name=3D'Mixout Left DAC Left Switch' on + * amixer -q cset name=3D'Mixout Right DAC Right Switch' on + * amixer -q cset name=3D'DAC Left Source MUX' 'DAI Input Left' + * amixer -q cset name=3D'DAC Right Source MUX' 'DAI Input Right' + * amixer -q sset 'Mic 1 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mic 2 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mixin Left Mic 1' on + * amixer -q sset 'Mixin Right Mic 2' on + * amixer -q sset 'Mic 1' 90% on + * amixer -q sset 'Mic 2' 90% on + * amixer -q sset 'Lineout' 80% on + * amixer -q set "Headphone" 100% on + * + * When Capture chained with DVC, use this command to amplify sound + * amixer set 'DVC In',0 80% + * For playback, use: amixer set 'DVC Out',0 80% + */ + / { model =3D "Renesas SMARC EVK version 2 based on r9a09g047e57"; compatible =3D "renesas,smarc2-evk", "renesas,rzg3e-smarcm", @@ -55,6 +86,22 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { gpios-states =3D <0>; states =3D <3300000 0>, <1800000 1>; }; + + sound_card: sound { + compatible =3D "audio-graph-card"; + + label =3D "snd-rzg3e"; + + dais =3D <&rsnd_port0>; /* DA7212 */ + }; +}; + +&audio_clkb { + clock-frequency =3D <11289600>; +}; + +&audio_clkc { + clock-frequency =3D <12288000>; }; =20 &canfd { @@ -99,6 +146,37 @@ &i2c0 { pinctrl-names =3D "default"; }; =20 +&i2c1 { + da7212: codec@1a { + compatible =3D "dlg,da7212"; + #sound-dai-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x1a>; + + clocks =3D <&versa3 1>; + clock-names =3D "mclk"; + + dlg,micbias1-lvl =3D <2500>; + dlg,micbias2-lvl =3D <2500>; + dlg,dmic-data-sel =3D "lrise_rfall"; + dlg,dmic-samplephase =3D "between_clkedge"; + dlg,dmic-clkrate =3D <3000000>; + + VDDA-supply =3D <®_1p8v>; + VDDSP-supply =3D <®_3p3v>; + VDDMIC-supply =3D <®_3p3v>; + VDDIO-supply =3D <®_1p8v>; + + port { + da7212_endpoint: endpoint { + remote-endpoint =3D <&rsnd_endpoint0>; + mclk-fs =3D <256>; + }; + }; + }; +}; + &keys { pinctrl-0 =3D <&nmi_pins>; pinctrl-names =3D "default"; @@ -280,6 +358,42 @@ &sdhi1 { vqmmc-supply =3D <&vqmmc_sd1_pvdd>; }; =20 +&snd_rzg3e { + pinctrl-0 =3D <&sound_clk_pins &sound_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + /* audio_clkout */ + #clock-cells =3D <0>; + clock-frequency =3D <11289600>; + + /* Multi DAI */ + #sound-dai-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + rsnd_port0: port@0 { + reg =3D <0>; + rsnd_endpoint0: endpoint { + remote-endpoint =3D <&da7212_endpoint>; + + dai-format =3D "i2s"; + bitclock-master =3D <&rsnd_endpoint0>; + frame-master =3D <&rsnd_endpoint0>; + + playback =3D <&ssi3>, <&src1>, <&dvc1>; + capture =3D <&ssi4>, <&src0>, <&dvc0>; + }; + }; + }; +}; + +&ssi4 { + shared-pin; +}; + &usb3_phy { status =3D "okay"; }; --=20 2.25.1