From nobody Mon Apr 6 23:25:40 2026 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC61B3DBD78 for ; Thu, 2 Apr 2026 11:27:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775129277; cv=none; b=IlEUisNGOjdVXaMcfeDMrtu0S3Lw5VNnDn19EGmt2tXP3sQjqEb/c+Qo2lwoEIYSuLxqygVUcp416uEeb3T7gC0pcXL/7vA2heryw3Fh7cLHZ4REWSjtLFu5QY1T9PkxhD9MPwZymB4TzC1C/yw4ynF3K0ucvQ0w1oWW95pDZNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775129277; c=relaxed/simple; bh=T9p3aJZIONmt1w+3RcK0dmLMQc6A1J6Nl8YM/mmzfgE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lPimwFUZXUMz/082aB/YoH1YTmFKIZ2+CqvCmOw/jI90Hu+RFGfh/Bzprr1xqyQL00ZW7c/d1Y1QURUbNxRVn3WjUPwEpnkt4ZJxOLw06VjqeWYsKU6DNIRA7b/4d8yaTko4nEc3KnUn2iJycoJWrtfEJH854D3xFBdOU29QWyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=NE/Uu0Mx; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="NE/Uu0Mx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; s=k1; bh=1zF6qO9ByDLCq7YhJcjUTAse1EQmfYIR8iItHXNCU64=; b=NE/Uu0 Mx2lgu/jlREkdSTjh4lRtEsuxdQwwbDKFkIX0fwQn1fZL6SG/BhdBwdLkSNFktAg flKC4e0S9cz6wO/CWhruNt8eEqMRx19WN3q/MCZXki44PUw1TzR6hafCr4LHAvWC oV4VB/0HShIXkKjEzVHp+p6xTabFRsFTZ9k1FW5tgdC5X73jQgmrwXimsDDzchXg JWHZQZ6stQanYZEyJXGeSQhbe9VBpaLmQJ0Q+jkhzc4Stnmr8kbIoH5WQxb/ptCa zE9s/7aOJSda1VgA0P+bylPcLpBSKozqeyLoV/lvaIj9zroKw6zali9+NtjpTuKt voL1AgW+rZYRwwRw== Received: (qmail 2479138 invoked from network); 2 Apr 2026 13:27:40 +0200 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 2 Apr 2026 13:27:40 +0200 X-UD-Smtp-Session: l3s3148p1@sBv9fHhOxlpUhsJN From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: Krzysztof Kozlowski , Marek Vasut , linux-kernel@vger.kernel.org, Wolfram Sang , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Rob Herring , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH v4 1/3] dt-bindings: soc: renesas: Document MFIS IP core Date: Thu, 2 Apr 2026 13:27:05 +0200 Message-ID: <20260402112709.13002-2-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260402112709.13002-1-wsa+renesas@sang-engineering.com> References: <20260402112709.13002-1-wsa+renesas@sang-engineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the Renesas Multifunctional Interface (MFIS) as found on the Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW Spinlock/Product Register/Error Injection/Error Detection and the likes. Family-compatible values are not introduced here because MFIS is usually very different per SoC. Signed-off-by: Wolfram Sang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- Changes since v3: * dropped superfluous constraints (Thanks, Geert!) * added tags from Krzysztof and Geert (Thanks!) .../soc/renesas/renesas,r8a78000-mfis.yaml | 187 ++++++++++++++++++ .../dt-bindings/soc/renesas,r8a78000-mfis.h | 28 +++ 2 files changed, 215 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r= 8a78000-mfis.yaml create mode 100644 include/dt-bindings/soc/renesas,r8a78000-mfis.h diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000= -mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000= -mfis.yaml new file mode 100644 index 000000000000..eef8c0a59e9c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.y= aml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MFIS (Multifunctional Interface) controller + +maintainers: + - Wolfram Sang + +description: + The Renesas Multifunctional Interface (MFIS) provides various functional= ity + like mailboxes, hardware spinlocks, product identification, error inject= ion, + error detection and such. Parts of it can be used for communication betw= een + different CPU cores. Those cores can be in various domains like AP, RT, = or + SCP. Often multiple domain-specific MFIS instances exist in one SoC. + +properties: + compatible: + enum: + - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR) + - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR) + + reg: + maxItems: 2 + + reg-names: + items: + - const: common + - const: mboxes + + interrupts: + minItems: 32 + maxItems: 128 + description: + The interrupts raised by the remote doorbells. + + interrupt-names: + minItems: 32 + maxItems: 128 + description: + An interrupt name is constructed with the prefix 'ch'. Then, the + channel number as specified in the documentation of the SoC. Finally, + the letter 'i' if the interrupt is raised by the IICR register. Or '= e' + if it is raised by the EICR register. + + "#hwlock-cells": + const: 1 + + "#mbox-cells": + const: 2 + description: + The first cell is the channel number as specified in the documentati= on + of the SoC. The second cell may specify flags as described in the fi= le + . + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis + then: + properties: + interrupts: + minItems: 128 + interrupt-names: + minItems: 128 + items: + pattern: "^ch[0-9]+[ie]$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis-scp + then: + properties: + interrupts: + maxItems: 32 + interrupt-names: + maxItems: 32 + items: + pattern: "^ch[0-9]+i$" + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#hwlock-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + system-controller@189e0000 { + compatible =3D "renesas,r8a78000-mfis"; + reg =3D <0x189e0000 0x1000>, <0x18800000 0x40000>; + reg-names =3D "common", "mboxes"; + interrupts =3D , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + interrupt-names =3D "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e"= , "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", = "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e"= , "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch= 14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch= 18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch= 22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch= 26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch= 30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch= 34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch= 38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch= 42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch= 46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch= 50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch= 54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch= 58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch= 62e", "ch63i", "ch63e"; + #hwlock-cells =3D <1>; + #mbox-cells =3D <2>; + }; diff --git a/include/dt-bindings/soc/renesas,r8a78000-mfis.h b/include/dt-b= indings/soc/renesas,r8a78000-mfis.h new file mode 100644 index 000000000000..52e17fea1a03 --- /dev/null +++ b/include/dt-bindings/soc/renesas,r8a78000-mfis.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H +#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H + +/* + * Constants for the second mbox-cell of the Renesas MFIS IP core. To be t= reated + * as bit flags which can be ORed. + */ + +/* + * MFIS HW design before r8a78001 requires a channel to be marked as either + * TX or RX. + */ +#define MFIS_CHANNEL_TX (0 << 0) +#define MFIS_CHANNEL_RX (1 << 0) + +/* + * MFIS variants before r8a78001 work with pairs of IICR and EICR register= s. + * Usually, it is specified in the datasheets which of the two a specific = core + * should use. Then, it does not need extra description in DT. For plain M= FIS + * of r8a78000, this is selectable, though. According to the system design= and + * the firmware in use, these channels need to be marked. This is not need= ed + * with other versions of the MFIS, not even with MFIS-SCP of r8a78000. + */ +#define MFIS_CHANNEL_IICR (0 << 1) +#define MFIS_CHANNEL_EICR (1 << 1) + +#endif --=20 2.51.0 From nobody Mon Apr 6 23:25:40 2026 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DEB93A4F27 for ; Thu, 2 Apr 2026 11:27:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775129278; cv=none; b=hFxjxh6R6fEAWIM1DxQpgm2blKJ2nZvDO9+nTfWaR0O3IhEdpPMEGFZlvZ+7Y6XzDEgAhysepPds2QUgODQ4Bb0V1hOSQmIhdfxcg4K6vo0FzwK6Mv/pTNv4Pbyxz7RsOo604ViVl6NKIbPJtt14svepu5EsPK2gGa0QisfDVBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775129278; c=relaxed/simple; bh=0c46ZuEPBNO+/W1uWG3bnq/cdwDNO4WbeQsqV2PRHwA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nHUyfEf6Ij9D3vAuEwmtXGCoQ45AqceLbw0RhdE4gPjH2WklW2eQQkEB9tqaLHR36nhxk534eg8tmKF3R3S9t0KNMHRmoh1FINH3Ea8F/FUnZ7s6z7o5YU40CYj0TdNDzuMQo9b+oN7CM6kPkqOv9Zwv26cePIevoIdUYGsqsHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=lV/APieO; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="lV/APieO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; s=k1; bh=6jbsIGjGvxMUHttwN4fWdHOUnHxcTAMlQq5tKtNQ16M=; b=lV/APi eO7TshUZXS9oeQeM9N3seatbF9IMX1pizfkdEqzRBv/MUlV8yF3cctT/iGvRLHrG 30NBqRsakgoKPtrvt/J0JaEhF3KEOs52d1Q2ch0bkdshhR5mziYQwxhp3wk1s1v/ ZukY8F4pnbeYFSmf4MURBkqn5sBIjkwsnFP983wHX+jG5CsdrFQ7rNGqnn/wcw1D Uh3/05mz7IDumrjfcQeYS5cjIAfcJEPYrFuhRGrVnWXQMlPhAV81vUXCZkmN5p2h QYgbcT+WgXRhHzlfM2WlQe8BHkTPHs/HB4Yko4E8uo9BpthpU799OZb0AnLxy6/J 4VptFrkp9P+fXvSg== Received: (qmail 2479197 invoked from network); 2 Apr 2026 13:27:42 +0200 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 2 Apr 2026 13:27:42 +0200 X-UD-Smtp-Session: l3s3148p1@YFgXfXhOuN9UhsJN From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: Krzysztof Kozlowski , Marek Vasut , linux-kernel@vger.kernel.org, Wolfram Sang , Kuninori Morimoto , Jassi Brar , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 2/3] soc: renesas: Add Renesas R-Car MFIS driver Date: Thu, 2 Apr 2026 13:27:06 +0200 Message-ID: <20260402112709.13002-3-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260402112709.13002-1-wsa+renesas@sang-engineering.com> References: <20260402112709.13002-1-wsa+renesas@sang-engineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas R-Car MFIS offers multiple features but most importantly mailboxes and hwspinlocks. Because they share a common register space and a common register unprotection mechanism, a single driver was chosen to handle all dependencies. (MFD and auxiliary bus have been tried as well, but they failed because of circular dependencies.) In this first step, the driver implements common register access and a mailbox controller. hwspinlock support will be added incrementally, once the subsystem allows out-of-directory drivers. Signed-off-by: Kuninori Morimoto Signed-off-by: Wolfram Sang Acked-by: Jassi Brar Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven --- Changes since v3: * use more 'unsigned int' instead of 'int' * re-ordered declarations to be more xmas-tree like (don't want to go farther than this) * added tags from Geert (Thanks!) drivers/soc/renesas/Kconfig | 9 + drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/rcar-mfis.c | 344 ++++++++++++++++++++++++++++++++ 3 files changed, 354 insertions(+) create mode 100644 drivers/soc/renesas/rcar-mfis.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 26bed0fdceb0..2ab150d04bb1 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -465,6 +465,15 @@ config ARCH_R9A07G043 =20 endif # RISCV =20 +config RCAR_MFIS + tristate "Renesas R-Car MFIS driver" + depends on ARCH_RENESAS || COMPILE_TEST + depends on MAILBOX + help + Select this option to enable the Renesas R-Car MFIS core driver for + the MFIS device found on SoCs like R-Car. On families like Gen5, this + is needed to communicate with the SCP. + config PWC_RZV2M bool "Renesas RZ/V2M PWC support" if COMPILE_TEST =20 diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 655dbcb08747..81bde85c2178 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_SYS_R9A09G057) +=3D r9a09g057-sys.o =20 # Family obj-$(CONFIG_PWC_RZV2M) +=3D pwc-rzv2m.o +obj-$(CONFIG_RCAR_MFIS) +=3D rcar-mfis.o obj-$(CONFIG_RST_RCAR) +=3D rcar-rst.o obj-$(CONFIG_RZN1_IRQMUX) +=3D rzn1_irqmux.o obj-$(CONFIG_SYSC_RZ) +=3D rz-sysc.o diff --git a/drivers/soc/renesas/rcar-mfis.c b/drivers/soc/renesas/rcar-mfi= s.c new file mode 100644 index 000000000000..059539eb8ab0 --- /dev/null +++ b/drivers/soc/renesas/rcar-mfis.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Renesas R-Car MFIS (Multifunctional Interface) driver + * + * Copyright (C) Renesas Solutions Corp. + * Kuninori Morimoto + * Wolfram Sang + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MFISWPCNTR 0x0900 +#define MFISWACNTR 0x0904 + +#define MFIS_X5H_IICR(i) ((i) * 0x1000 + 0x00) +#define MFIS_X5H_EICR(i) ((i) * 0x1000 + 0x04) + +#define MFIS_UNPROTECT_KEY 0xACCE0000 + +struct mfis_priv; + +struct mfis_reg { + void __iomem *base; + resource_size_t start; + struct mfis_priv *priv; +}; + +struct mfis_info { + u32 unprotect_mask; + unsigned int mb_num_channels; + unsigned int mb_reg_comes_from_dt:1; + unsigned int mb_tx_uses_eicr:1; + unsigned int mb_channels_are_unidir:1; +}; + +struct mfis_chan_priv { + u32 reg; + int irq; +}; + +struct mfis_priv { + spinlock_t unprotect_lock; /* guards access to the unprotection reg */ + struct device *dev; + struct mfis_reg common_reg; + struct mfis_reg mbox_reg; + const struct mfis_info *info; + + /* mailbox private data */ + struct mbox_controller mbox; + struct mfis_chan_priv *chan_privs; +}; + +static u32 mfis_read(struct mfis_reg *mreg, unsigned int reg) +{ + return ioread32(mreg->base + reg); +} + +static void mfis_write(struct mfis_reg *mreg, u32 reg, u32 val) +{ + struct mfis_priv *priv =3D mreg->priv; + u32 unprotect_mask =3D priv->info->unprotect_mask; + u32 unprotect_code; + unsigned long flags; + + /* + * [Gen4] key: 0xACCE0000, mask: 0x0000FFFF + * [Gen5] key: 0xACC00000, mask: 0x000FFFFF + */ + unprotect_code =3D (MFIS_UNPROTECT_KEY & ~unprotect_mask) | + ((mreg->start + reg) & unprotect_mask); + + spin_lock_irqsave(&priv->unprotect_lock, flags); + iowrite32(unprotect_code, priv->common_reg.base + MFISWACNTR); + iowrite32(val, mreg->base + reg); + spin_unlock_irqrestore(&priv->unprotect_lock, flags); +} + +/******************************************************** + * Mailbox * + ********************************************************/ + +#define mfis_mb_mbox_to_priv(_m) container_of((_m), struct mfis_priv, mbox) + +static irqreturn_t mfis_mb_iicr_interrupt(int irq, void *data) +{ + struct mbox_chan *chan =3D data; + struct mfis_priv *priv =3D mfis_mb_mbox_to_priv(chan->mbox); + struct mfis_chan_priv *chan_priv =3D chan->con_priv; + + mbox_chan_received_data(chan, NULL); + /* Stop remote(!) doorbell */ + mfis_write(&priv->mbox_reg, chan_priv->reg, 0); + + return IRQ_HANDLED; +} + +static int mfis_mb_startup(struct mbox_chan *chan) +{ + struct mfis_chan_priv *chan_priv =3D chan->con_priv; + + if (!chan_priv->irq) + return 0; + + return request_irq(chan_priv->irq, mfis_mb_iicr_interrupt, 0, + dev_name(chan->mbox->dev), chan); +} + +static void mfis_mb_shutdown(struct mbox_chan *chan) +{ + struct mfis_chan_priv *chan_priv =3D chan->con_priv; + + if (chan_priv->irq) + free_irq(chan_priv->irq, chan); +} + +static int mfis_mb_iicr_send_data(struct mbox_chan *chan, void *data) +{ + struct mfis_priv *priv =3D mfis_mb_mbox_to_priv(chan->mbox); + struct mfis_chan_priv *chan_priv =3D chan->con_priv; + + /* Our doorbell still active? */ + if (mfis_read(&priv->mbox_reg, chan_priv->reg) & BIT(0)) + return -EBUSY; + + /* Start our doorbell */ + mfis_write(&priv->mbox_reg, chan_priv->reg, BIT(0)); + + return 0; +} + +static bool mfis_mb_iicr_last_tx_done(struct mbox_chan *chan) +{ + struct mfis_priv *priv =3D mfis_mb_mbox_to_priv(chan->mbox); + struct mfis_chan_priv *chan_priv =3D chan->con_priv; + + /* Our doorbell still active? */ + return !(mfis_read(&priv->mbox_reg, chan_priv->reg) & BIT(0)); +} + +/* For MFIS variants using the IICR/EICR register pair */ +static const struct mbox_chan_ops mfis_iicr_ops =3D { + .startup =3D mfis_mb_startup, + .shutdown =3D mfis_mb_shutdown, + .send_data =3D mfis_mb_iicr_send_data, + .last_tx_done =3D mfis_mb_iicr_last_tx_done, +}; + +static struct mbox_chan *mfis_mb_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + struct mfis_priv *priv =3D mfis_mb_mbox_to_priv(mbox); + struct mfis_chan_priv *chan_priv; + struct mbox_chan *chan; + u32 chan_num, chan_flags; + bool tx_uses_eicr, is_only_rx; + + if (sp->args_count !=3D 2) + return ERR_PTR(-EINVAL); + + chan_num =3D sp->args[0]; + chan_flags =3D sp->args[1]; + + if (chan_num >=3D priv->info->mb_num_channels) + return ERR_PTR(-EINVAL); + + /* Channel layout is described in mfis_mb_probe() */ + if (priv->info->mb_channels_are_unidir) { + is_only_rx =3D chan_flags & MFIS_CHANNEL_RX; + chan =3D mbox->chans + 2 * chan_num + is_only_rx; + } else { + is_only_rx =3D false; + chan =3D mbox->chans + chan_num; + } + + if (priv->info->mb_reg_comes_from_dt) { + tx_uses_eicr =3D chan_flags & MFIS_CHANNEL_EICR; + if (tx_uses_eicr) + chan +=3D mbox->num_chans / 2; + } else { + tx_uses_eicr =3D priv->info->mb_tx_uses_eicr; + } + + chan_priv =3D chan->con_priv; + chan_priv->reg =3D (tx_uses_eicr ^ is_only_rx) ? MFIS_X5H_EICR(chan_num) : + MFIS_X5H_IICR(chan_num); + + if (!priv->info->mb_channels_are_unidir || is_only_rx) { + char irqname[8]; + char suffix =3D tx_uses_eicr ? 'i' : 'e'; + + /* "ch0i" or "ch0e" */ + scnprintf(irqname, sizeof(irqname), "ch%u%c", chan_num, suffix); + + chan_priv->irq =3D of_irq_get_byname(mbox->dev->of_node, irqname); + if (chan_priv->irq < 0) + return ERR_PTR(chan_priv->irq); + if (chan_priv->irq =3D=3D 0) + return ERR_PTR(-ENOENT); + } + + return chan; +} + +static int mfis_mb_probe(struct mfis_priv *priv) +{ + struct device *dev =3D priv->dev; + struct mbox_controller *mbox; + struct mbox_chan *chan; + unsigned int num_chan =3D priv->info->mb_num_channels; + + if (priv->info->mb_channels_are_unidir) { + /* Channel layout: Ch0-TX, Ch0-RX, Ch1-TX... */ + num_chan *=3D 2; + } + + if (priv->info->mb_reg_comes_from_dt) { + /* Channel layout: IICR channels, EICR channels */ + num_chan *=3D 2; + } + + chan =3D devm_kcalloc(dev, num_chan, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + priv->chan_privs =3D devm_kcalloc(dev, num_chan, sizeof(*priv->chan_privs= ), + GFP_KERNEL); + if (!priv->chan_privs) + return -ENOMEM; + + mbox =3D &priv->mbox; + + for (unsigned int i =3D 0; i < num_chan; i++) + chan[i].con_priv =3D &priv->chan_privs[i]; + + mbox->chans =3D chan; + mbox->num_chans =3D num_chan; + mbox->txdone_poll =3D true; + mbox->ops =3D &mfis_iicr_ops; + mbox->dev =3D dev; + mbox->of_xlate =3D mfis_mb_of_xlate; + + return devm_mbox_controller_register(dev, mbox); +} + +/******************************************************** + * Common * + ********************************************************/ +static int mfis_reg_probe(struct platform_device *pdev, struct mfis_priv *= priv, + struct mfis_reg *mreg, const char *name, bool required) +{ + struct resource *res; + void __iomem *base; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + + /* If there is no mailbox resource, registers are in the common space */ + if (!res && !required) { + *mreg =3D priv->common_reg; + } else { + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + mreg->base =3D base; + mreg->start =3D res->start; + mreg->priv =3D priv; + } + + return 0; +} + +static int mfis_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mfis_priv *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->info =3D of_device_get_match_data(dev); + if (!priv->info) + return -ENOENT; + + spin_lock_init(&priv->unprotect_lock); + + ret =3D mfis_reg_probe(pdev, priv, &priv->common_reg, "common", true); + if (ret) + return ret; + + ret =3D mfis_reg_probe(pdev, priv, &priv->mbox_reg, "mboxes", false); + if (ret) + return ret; + + return mfis_mb_probe(priv); +} + +static const struct mfis_info mfis_info_r8a78000 =3D { + .unprotect_mask =3D 0x000fffff, + .mb_num_channels =3D 64, + .mb_reg_comes_from_dt =3D true, + .mb_channels_are_unidir =3D true, +}; + +static const struct mfis_info mfis_info_r8a78000_scp =3D { + .unprotect_mask =3D 0x000fffff, + .mb_num_channels =3D 32, + .mb_tx_uses_eicr =3D true, + .mb_channels_are_unidir =3D true, +}; + +static const struct of_device_id mfis_mfd_of_match[] =3D { + { .compatible =3D "renesas,r8a78000-mfis", .data =3D &mfis_info_r8a78000,= }, + { .compatible =3D "renesas,r8a78000-mfis-scp", .data =3D &mfis_info_r8a78= 000_scp, }, + {} +}; +MODULE_DEVICE_TABLE(of, mfis_mfd_of_match); + +static struct platform_driver mfis_driver =3D { + .driver =3D { + .name =3D "rcar-mfis", + .of_match_table =3D mfis_mfd_of_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D mfis_probe, +}; +module_platform_driver(mfis_driver); + +MODULE_AUTHOR("Kuninori Morimoto "); +MODULE_AUTHOR("Wolfram Sang "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Renesas R-Car MFIS driver"); --=20 2.51.0 From nobody Mon Apr 6 23:25:40 2026 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1673D3AD500 for ; Thu, 2 Apr 2026 11:27:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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2 Apr 2026 13:27:43 +0200 X-UD-Smtp-Session: l3s3148p1@0lUmfXhOq9BUhsJN From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: Krzysztof Kozlowski , Marek Vasut , linux-kernel@vger.kernel.org, Wolfram Sang , Geert Uytterhoeven , Magnus Damm Subject: [PATCH v4 3/3] soc: renesas: add X5H PRR support Date: Thu, 2 Apr 2026 13:27:07 +0200 Message-ID: <20260402112709.13002-4-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260402112709.13002-1-wsa+renesas@sang-engineering.com> References: <20260402112709.13002-1-wsa+renesas@sang-engineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On this SoC, PRR is now inside the MFIS memory block, so we need to access it similar to e.g. RZ/G2L. Suggested-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- Changes since v3: none drivers/soc/renesas/renesas-soc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesa= s-soc.c index 38ff0b823bda..60b09020c935 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -442,8 +442,14 @@ static const struct renesas_id id_prr __initconst =3D { .mask =3D 0xff00, }; =20 +static const struct renesas_id id_mfis __initconst =3D { + .offset =3D 0x44, + .mask =3D 0xff00, +}; + static const struct of_device_id renesas_ids[] __initconst =3D { { .compatible =3D "renesas,bsid", .data =3D &id_bsid }, + { .compatible =3D "renesas,r8a78000-mfis", .data =3D &id_mfis }, { .compatible =3D "renesas,r9a07g043-sysc", .data =3D &id_rzg2l }, { .compatible =3D "renesas,r9a07g044-sysc", .data =3D &id_rzg2l }, { .compatible =3D "renesas,r9a07g054-sysc", .data =3D &id_rzg2l }, @@ -501,7 +507,7 @@ static int __init renesas_soc_init(void) product =3D readl(chipid + id->offset); iounmap(chipid); =20 - if (id =3D=3D &id_prr) { + if (id =3D=3D &id_prr || id =3D=3D &id_mfis) { /* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */ if ((product & 0x7fff) =3D=3D 0x5210) product ^=3D 0x11; --=20 2.51.0