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charset="utf-8" Add devicetree changes to enable second Mobile Display Subsystem (mdss1), Display Processing Unit(DPU), Display Port(DP), Display clock controller (dispcc1) and eDP PHYs on the Qualcomm Lemans platform. Signed-off-by: Mahadevan P Signed-off-by: Mani Chandana Ballary Kuntumalla --- arch/arm64/boot/dts/qcom/lemans.dtsi | 289 ++++++++++++++++++++++++--- 1 file changed, 262 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index bc0ec9a80284..4e608bd6486c 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5474,7 +5474,7 @@ mdss0_dp1: displayport-controller@af5c000 { phys =3D <&mdss0_dp1_phy>; phy-names =3D "dp"; =20 - operating-points-v2 =3D <&dp1_opp_table>; + operating-points-v2 =3D <&dp_opp_table>; power-domains =3D <&rpmhpd SA8775P_MMCX>; =20 #sound-dai-cells =3D <0>; @@ -5499,30 +5499,6 @@ port@1 { mdss0_dp1_out: endpoint { }; }; }; - - dp1_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-162000000 { - opp-hz =3D /bits/ 64 <162000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz =3D /bits/ 64 <270000000>; - required-opps =3D <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz =3D /bits/ 64 <540000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz =3D /bits/ 64 <810000000>; - required-opps =3D <&rpmhpd_opp_nom>; - }; - }; }; }; =20 @@ -7055,6 +7031,265 @@ compute-cb@3 { }; }; =20 + mdss1: display-subsystem@22000000 { + compatible =3D "qcom,sa8775p-mdss"; + reg =3D <0x0 0x22000000 0x0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets =3D <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1800 0x402>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + display-controller@22001000 { + compatible =3D "qcom,sa8775p-dpu"; + reg =3D <0x0 0x22001000 0x0 0x8f000>, + <0x0 0x220b0000 0x0 0x3000>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdss0_mdp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu1_intf0_out: endpoint { + remote-endpoint =3D <&mdss1_dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu1_intf4_out: endpoint { + remote-endpoint =3D <&mdss1_dp1_in>; + }; + }; + }; + }; + + mdss1_dp0_phy: phy@220c2a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + reg =3D <0x0 0x220c2a00 0x0 0x200>, + <0x0 0x220c2200 0x0 0xd0>, + <0x0 0x220c2600 0x0 0xd0>, + <0x0 0x220c2000 0x0 0x1c8>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss1_dp1_phy: phy@220c5a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + reg =3D <0x0 0x220c5a00 0x0 0x200>, + <0x0 0x220c5200 0x0 0xd0>, + <0x0 0x220c5600 0x0 0xd0>, + <0x0 0x220c5000 0x0 0x1c8>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss1_dp0: displayport-controller@22154000 { + compatible =3D "qcom,sa8775p-dp"; + reg =3D <0x0 0x22154000 0x0 0x104>, + <0x0 0x22154200 0x0 0x0c0>, + <0x0 0x22155000 0x0 0x770>, + <0x0 0x22156000 0x0 0x09c>, + <0x0 0x22157000 0x0 0x09c>, + <0x0 0x22158000 0x0 0x09c>, + <0x0 0x22159000 0x0 0x09c>, + <0x0 0x2215a000 0x0 0x23c>, + <0x0 0x2215b000 0x0 0x23c>; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <12>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; + phys =3D <&mdss1_dp0_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss1_dp0_in: endpoint { + remote-endpoint =3D <&dpu1_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss1_dp0_out: endpoint { }; + }; + }; + }; + + mdss1_dp1: displayport-controller@2215c000 { + compatible =3D "qcom,sa8775p-dp"; + reg =3D <0x0 0x2215c000 0x0 0x104>, + <0x0 0x2215c200 0x0 0x0c0>, + <0x0 0x2215d000 0x0 0x770>, + <0x0 0x2215e000 0x0 0x09c>, + <0x0 0x2215f000 0x0 0x09c>, + <0x0 0x22160000 0x0 0x09c>, + <0x0 0x22161000 0x0 0x09c>, + <0x0 0x22162000 0x0 0x23c>, + <0x0 0x22163000 0x0 0x23c>; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <13>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + assigned-clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; + phys =3D <&mdss1_dp1_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss1_dp1_in: endpoint { + remote-endpoint =3D <&dpu1_intf4_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss1_dp1_out: endpoint { }; + }; + }; + + }; + }; + dispcc1: clock-controller@22100000 { compatible =3D "qcom,sa8775p-dispcc1"; reg =3D <0x0 0x22100000 0x0 0x20000>; @@ -7062,13 +7297,13 @@ dispcc1: clock-controller@22100000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, <0>, <0>, <0>, <0>; power-domains =3D <&rpmhpd SA8775P_MMCX>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; - status =3D "disabled"; }; =20 ethernet1: ethernet@23000000 { --=20 2.34.1 From nobody Sun Apr 5 14:05:23 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71BED3DF006; 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charset="utf-8" This change enables DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to edp2 and edp3. Signed-off-by: Mani Chandana Ballary Kuntumalla --- .../boot/dts/qcom/lemans-ride-common.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/= boot/dts/qcom/lemans-ride-common.dtsi index 31bd00546d55..9b48e6134ff9 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -154,6 +154,30 @@ dp1_connector_in: endpoint { }; }; =20 + dp2-connector { + compatible =3D "dp-connector"; + label =3D "eDP2"; + type =3D "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint =3D <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible =3D "dp-connector"; + label =3D "eDP3"; + type =3D "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint =3D <&mdss1_dp1_out>; + }; + }; + }; + dp-dsi0-connector { compatible =3D "dp-connector"; label =3D "DSI0"; @@ -613,6 +637,50 @@ &mdss0_dsi1_phy { status =3D "okay"; }; =20 +&mdss1 { + status =3D "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 =3D <&dp2_hot_plug_det>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&mdss1_dp0_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp2_connector_in>; +}; + +&mdss1_dp0_phy { + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l4a>; + + status =3D "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 =3D <&dp3_hot_plug_det>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&mdss1_dp1_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp3_connector_in>; +}; + +&mdss1_dp1_phy { + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l4a>; + + status =3D "okay"; +}; + &pmm8654au_0_gpios { gpio-line-names =3D "DS_EN", "POFF_COMPLETE", @@ -790,6 +858,18 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; =20 + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins =3D "gpio104"; + function =3D "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins =3D "gpio103"; + function =3D "edp3_hot"; + bias-disable; + }; + io_expander_intr_active: io-expander-intr-active-state { pins =3D "gpio98"; function =3D "gpio"; --=20 2.34.1 From nobody Sun Apr 5 14:05:23 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 443AE1E1A17; Thu, 2 Apr 2026 09:50:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775123447; cv=none; b=Uo9XvSt+bQ2PdYWXh6LGr8J8XhhtmKUHzcITu0pbl1SSiTYBYyHjfqj3bWYZs3w81TCvD8CtJPtR+rZMSG0Y9D+5gtmPAzYEOiNpCQSCiaGNv145PIvstmELEZ+C64MHXuuzqLy0YIcP0jhBzYo0qeLNdGQKrh+6Kic/8yPQEKg= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 2 Apr 2026 09:50:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4d6qk2m86k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Apr 2026 09:50:16 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 6329oGHC004362; Thu, 2 Apr 2026 09:50:16 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-mkuntuma-hyd.qualcomm.com [10.213.97.145]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 6329oGYd004354 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Apr 2026 09:50:16 +0000 (GMT) Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 4582077) id B402F5ED; Thu, 2 Apr 2026 15:20:15 +0530 (+0530) From: Mani Chandana Ballary Kuntumalla To: dmitry.baryshkov@oss.qualcomm.com, marijn.suijten@somainline.org, swboyd@chromium.org, mripard@kernel.org, abel.vesa@linaro.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, jessica.zhang@oss.qualcomm.com, abhinav.kumar@linux.dev, sean@poorly.run, airlied@gmail.com, simona@ffwll.ch, alex.vinarskis@gmail.com Cc: Vishnu Saini , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, quic_rajeevny@quicinc.com, quic_vproddut@quicinc.com, quic_riteshk@quicinc.com, Mani Chandana Ballary Kuntumalla Subject: [PATCH v5 3/3] arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port Date: Thu, 2 Apr 2026 15:20:03 +0530 Message-Id: <20260402095003.3758176-4-quic_mkuntuma@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260402095003.3758176-1-quic_mkuntuma@quicinc.com> References: <20260402095003.3758176-1-quic_mkuntuma@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Authority-Analysis: v=2.4 cv=RYydyltv c=1 sm=1 tr=0 ts=69ce3bdc cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=0voD-ITsHmux3e9IgYMA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAyMDA4OCBTYWx0ZWRfX1hsR09aS5PFY h6bJ7zyEy1VJKQ4pHwNZhEM512SKuAZ1zILLsdKWeZKUZmUph3Kd9yCAecJQs6Sd8sEb4vLD9iA emJcDbPIFavK8/4WVR7cEGmzmwkNIRNcctw7QtXA6CVK7aoLxtAng4JAvW7RVTK6C5mi1GJN1BR ON/ZJVIr650BiXvSiaJWASSKjMyuyVwCJXIEuRX2n+BmzJQ2XpnKQCOZ1LDqbe6cr711fVntmnI T6RuJYU2z3iRaWDAioFNyfOe1s/TpszvKuCxcIRz3MD7bR6VF+vhghlcBPl23kKqoML967eOJDk j/7XPjphj9XGDKFeFwatt0s31Zq7mleDIR7vn5eCpbeT/lb21kp+vNLykmL5b57FJcqbT6zqY8Q sKWy6jQC9+49Dzt3RmXHD8ZvFShEzpWIpKdJT9hhlpIZC4E8J+odVv+JG5CWrIHBQ/3wCvXl2ID 18zku2RR+9hgR30EuDA== X-Proofpoint-ORIG-GUID: f6XuQancGbzBxrIPkTdPrUqEW_W-HNuu X-Proofpoint-GUID: f6XuQancGbzBxrIPkTdPrUqEW_W-HNuu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-02_01,2026-04-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604020088 Content-Type: text/plain; charset="utf-8" From: Vishnu Saini Enable DP controllers, DPTX0 and DPTX1 alongside their corresponding PHYs of mdss1 which corresponds to eDP2 and eDP3. Signed-off-by: Vishnu Saini Signed-off-by: Mani Chandana Ballary Kuntumalla --- .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/= arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 268fc6b05d4b..44bd9b1a1765 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -11,6 +11,30 @@ &{/} { model =3D "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; =20 + dp2-connector { + compatible =3D "dp-connector"; + label =3D "eDP2"; + type =3D "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint =3D <&mdss1_dp0_out>; + }; + }; + }; + + dp3-connector { + compatible =3D "dp-connector"; + label =3D "eDP3"; + type =3D "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint =3D <&mdss1_dp1_out>; + }; + }; + }; + vreg_0p9: regulator-0v9 { compatible =3D "regulator-fixed"; regulator-name =3D "VREG_0P9"; @@ -141,6 +165,44 @@ mac_addr1: mac-addr@0 { }; }; =20 +&mdss1 { + status =3D "okay"; +}; + +&mdss1_dp0 { + pinctrl-0 =3D <&dp2_hot_plug_det>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&mdss1_dp1 { + pinctrl-0 =3D <&dp3_hot_plug_det>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&mdss1_dp0_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp2_connector_in>; +}; + +&mdss1_dp1_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp3_connector_in>; +}; + +&mdss1_dp0_phy { + status =3D "okay"; +}; + +&mdss1_dp1_phy { + status =3D "okay"; +}; + &pcie0 { iommu-map =3D <0x0 &pcie_smmu 0x0 0x1>, <0x100 &pcie_smmu 0x1 0x1>, @@ -235,6 +297,18 @@ &serdes1 { }; =20 &tlmm { + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins =3D "gpio104"; + function =3D "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins =3D "gpio103"; + function =3D "edp3_hot"; + bias-disable; + }; + ethernet1_default: ethernet1-default-state { ethernet1-mdc-pins { pins =3D "gpio20"; --=20 2.34.1