From nobody Mon Apr 6 12:12:13 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E2C4A372B5E; Thu, 2 Apr 2026 09:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775121019; cv=none; b=cII2Ftxni+vg0RmXmo+r63K9GdXjVcrF5yhL7hSTAMyK2sNyq7iPAezi/yd4C2SZG86xeMjkCBjWyLY8bOmno7f/v1RiwxQ1Zi5M8KiycTbYTvYS5jJujeLvaoScFR9BpzEFjsqLkoBcVGuSatMvJjadQUIff7T6pNGfzk885dE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775121019; c=relaxed/simple; bh=XMEYafMe/IJWQCctVc/IEI6fLAPeHIYI3n1vF/9z39E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NcYZ3gnXwXrtbTcQ6w0pMy1aI5d5VpP5caUZ5NDOHtcacPVpyIaXcoNzh/ZSm6qD7gjDNXgNoGgO26DtrHGbNnjmoCbtrMMQpAu2ykN4MzTRn4qqJcK+3tuVWi/w/evcZsfdBB6h8cLI4+tbobuwxz5ZQ0N2kdB6SyMfU/5dWBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: fvsiPg6LSqO1gt2GNd3jdg== X-CSE-MsgGUID: +9xqlMxaRumMdFcKe8Q8sA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Apr 2026 18:10:17 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.136]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7F24E40E20DF; Thu, 2 Apr 2026 18:10:08 +0900 (JST) From: John Madieu To: Geert Uytterhoeven , Kuninori Morimoto , Vinod Koul , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Conor Dooley , Frank Li , Liam Girdwood , Magnus Damm , Thomas Gleixner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , Claudiu Beznea , Biju Das , Fabrizio Castro , Lad Prabhakar , John Madieu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-sound@vger.kernel.org, John Madieu Subject: [PATCH v2 21/24] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator Date: Thu, 2 Apr 2026 11:05:20 +0200 Message-ID: <20260402090524.9137-22-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402090524.9137-1-john.madieu.xa@bp.renesas.com> References: <20260402090524.9137-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Renesas 5P35023 (Versa3) programmable clock generator on the I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the audio subsystem. The Versa3 provides the following audio-related clock outputs: - Output 0: 24MHz (reference) - Output 1: 12.288MHz (audio, 48kHz family) - Output 2: 11.2896MHz (audio, 44.1kHz family) - Output 3: 12.288MHz (audio) These clocks are required for the audio codec found on the RZ/G3E SMARC EVK. Signed-off-by: John Madieu --- Changes: v2: No changes .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3e-smarc-som.dtsi index d978619155d2..89428c804efb 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -77,6 +77,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others { regulator-always-on; }; =20 + x2: x2-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + /* 32.768kHz crystal */ x3: x3-clock { compatible =3D "fixed-clock"; @@ -130,6 +136,20 @@ raa215300: pmic@12 { =20 interrupts-extended =3D <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING= >; }; + + versa3: clock-generator@68 { + compatible =3D "renesas,5p35023"; + reg =3D <0x68>; + #clock-cells =3D <1>; + clocks =3D <&x2>; + + assigned-clocks =3D <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates =3D <24000000>, <12288000>, + <11289600>, <12288000>, + <25000000>, <25000000>; + }; }; =20 &i3c { --=20 2.25.1