From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0329F3A3807; Thu, 2 Apr 2026 08:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117692; cv=none; b=jDCAZ4YriAIc3t7273788D1xx/T2+vUTmxm6OuFYSJY/nmoZWgivmNOzJqF862kWCMzeM7ETJEaUnM+lpkBPKA4SY4KYtkd3aKApFFDuoTSJBePu280waqFgOLcZOJjC/ru7GmwHjLXe8o4yWTHJr88IZ47u1XNZmxuXxGZYH/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117692; c=relaxed/simple; bh=WjsTHLjgxsy+mXRsoUwpiqJQYbq1MnNhmtWxtQbbl8g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=u7uUjJSH2lvy1HnDKnzwCVld+w9+lfPhZfhJv0cVUTOs7SfQ3VIB2uT+hmkOW2fBtNVwXU1jdxxDs7VKUElVNJVBGdn1jhcPNMMfu6IB9p33ON6IIlio5MKwBRqBPK3+ObvjbB7YJGXliiJcLN6JOtCaa9Qwu++5jh2ThTZGl98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=jfID6u8Q; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="jfID6u8Q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=MHv2qgvbLAFuri5 w6URQ/pAxxfhBNmmanOC7CAD1enM=; b=jfID6u8QVOmLv8SG7jCek4QiIlu1g6v 0zhyhxt0P+yCk1McOMMUbeQ7RQApZrdDhz95GKCe+uEkQT4pUigi/1QGmMDDExLB vHM19CoR6bLa0Mz90vYZK93NaCKsJfQxskAmOHfl/i4cQfgK1am3P6bzElOzlHVE AwJy0+P/H05Y= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgCX5UBEJc5pC9uuUw--.170S3; Thu, 02 Apr 2026 16:14:01 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Wenliang Yan , Jonathan Corbet , linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210 Date: Thu, 2 Apr 2026 04:13:43 -0400 Message-Id: <20260402081350.65559-2-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260402081350.65559-1-wenliang202407@163.com> References: <20260402081350.65559-1-wenliang202407@163.com> X-CM-TRANSID: QCgvCgCX5UBEJc5pC9uuUw--.170S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cw4UGFWkZr13Zw43Wr17ZFb_yoW8Xr43pF s3CFyUWrySqr1fZ39rKFsY9F15Jwn7ua12kFnrGw4SqF4DGa4Fq393Kw1qyFn8ArWfXFW7 WFWI9r4Fg397Ar7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUgNVkUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCvwlpPWnOJUkevgAA3J Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a compatible string for SQ52210, provide brief descriptions for both INA3221 and SQ52210, and define the compatibility relationship between SQ52210 and INA3221. SQ52210 is backward compatible with INA3221. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wenliang Yan --- .../devicetree/bindings/hwmon/ti,ina3221.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml b/Docu= mentation/devicetree/bindings/hwmon/ti,ina3221.yaml index 5f10f1207d69..2dd2fd148792 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml @@ -10,9 +10,22 @@ maintainers: - Jean Delvare - Guenter Roeck =20 +description: | + The INA3221 is a three-channel, high-side current and bus voltage monito= r. + + The Silergy SQ52210 is a power monitor that extends the functionality of + the INA3221 by adding additional current registers, power registers, and + alert registers. These features are configured internally by the driver + and require no board-level device tree configuration. + properties: compatible: - const: ti,ina3221 + oneOf: + - items: + - const: silergy,sq52210 + - const: ti,ina3221 + - items: + - const: ti,ina3221 =20 reg: maxItems: 1 --=20 2.17.1 From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA37B35F8A8; Thu, 2 Apr 2026 08:14:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117697; cv=none; b=NOe+lFxjd4R+/PFER4cwEfC3s3zLu4uIgJaxg/nv6bIEzolEUbRypCI7FMg1joL8kpVCwysOh5hXb2x8iLAn4MM3U51cizKZkIPZ2yOHpE828CmUguOpjYP+D9X0JxwlV0mZPIy7wHNtMlB9f/dXP6dmMiWLijTTHxxcylrVVrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117697; c=relaxed/simple; bh=H/w+6on8fYV8qpYT0kb7Mj2iA2mlwXEn1PrOId/TyGo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Rj0EolbepKnkRgSykO/QWk14iMiqdwAoRNhHRT3y2jc+XPpv1t3QGrkUpOiKVHFTzMe7T+8euHY+V6L632L2AF8qAMQA0H0XK/ZP+dUjBhrs1yom0dLz+SPgc2ifS2YWxrq/ue5zWiD7TcR4kATQZ1nq4yoE8jah4nJmJLMPL8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=qTefBHeZ; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="qTefBHeZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=oQP23GsQvFrcqDF p4tVk7ny6xZlM2KY/EMMUq56/WtE=; b=qTefBHeZ3CL5Gv8A8NvxU3Qmqz6iKZZ FhMqGf/PLytbiFyok5Cd4YXF+uEA5hHOFVdYccRu8Ss0exGf27ZqX2FuFeOTLrP2 4vuwbndqVGI4l3OJSCkWhAOde08OdMV8W1gLa+Gf1Qv09/T7RT5BpQ3Hf9xuH3Pb Dt+cYovS2L+o= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgCX5UBEJc5pC9uuUw--.170S4; Thu, 02 Apr 2026 16:14:02 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/8] hwmon: (ina3221) Add support for SQ52210 Date: Thu, 2 Apr 2026 04:13:44 -0400 Message-Id: <20260402081350.65559-3-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260402081350.65559-1-wenliang202407@163.com> References: <20260402081350.65559-1-wenliang202407@163.com> X-CM-TRANSID: QCgvCgCX5UBEJc5pC9uuUw--.170S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFW8Xr1UJFWDXrW3AF1kXwb_yoW5ur1fpa 1rAa4rtr45Xr4Ig3yfKFs5tF15tr4xW3yIvrnrK3yIvF4DAry0gF1rGw4vyF98ZFyfZFsr X34Iy3y8uwnrJr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRbzV8UUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbC5wtpPWnOJUu5MwAA37 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add Compatible for SQ52210. Compared to the INA3221, the SQ52210 also has current registers, power registers, and limit-related registers. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 5ecc68dcf169..47ef4fe694ea 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -34,6 +34,17 @@ #define INA3221_SHUNT_SUM 0x0d #define INA3221_CRIT_SUM 0x0e #define INA3221_MASK_ENABLE 0x0f +#define SQ52210_ALERT_CONFIG 0x12 +#define SQ52210_CALIBRATION 0x14 +#define SQ52210_CURRENT1 0x15 +#define SQ52210_CURRENT2 0x16 +#define SQ52210_CURRENT3 0x17 +#define SQ52210_POWER1 0x18 +#define SQ52210_POWER2 0x19 +#define SQ52210_POWER3 0x1A +#define SQ52210_ALERT_LIMIT1 0x1B +#define SQ52210_ALERT_LIMIT2 0x1C +#define SQ52210_ALERT_LIMIT3 0x1D =20 #define INA3221_CONFIG_MODE_MASK GENMASK(2, 0) #define INA3221_CONFIG_MODE_POWERDOWN 0 @@ -108,8 +119,11 @@ struct ina3221_input { bool summation_disable; }; =20 +enum ina3221_ids { ina3221, sq52210 }; + /** * struct ina3221_data - device specific information + * @chip: Chip type identifier * @pm_dev: Device pointer for pm runtime * @regmap: Register map of the device * @fields: Register fields of the device @@ -120,6 +134,8 @@ struct ina3221_input { * @single_shot: running in single-shot operating mode */ struct ina3221_data { + enum ina3221_ids chip; + struct device *pm_dev; struct regmap *regmap; struct regmap_field *fields[F_MAX_FIELDS]; @@ -734,6 +750,7 @@ static const struct regmap_range ina3221_yes_ranges[] = =3D { regmap_reg_range(INA3221_CONFIG, INA3221_BUS3), regmap_reg_range(INA3221_SHUNT_SUM, INA3221_SHUNT_SUM), regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE), + regmap_reg_range(SQ52210_ALERT_CONFIG, SQ52210_POWER3), }; =20 static const struct regmap_access_table ina3221_volatile_table =3D { @@ -818,13 +835,18 @@ static int ina3221_probe(struct i2c_client *client) struct device *dev =3D &client->dev; struct ina3221_data *ina; struct device *hwmon_dev; + enum ina3221_ids chip; char name[32]; int i, ret; =20 + chip =3D (uintptr_t)i2c_get_match_data(client); + ina =3D devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); if (!ina) return -ENOMEM; =20 + ina->chip =3D chip; + ina->regmap =3D devm_regmap_init_i2c(client, &ina3221_regmap_config); if (IS_ERR(ina->regmap)) { dev_err(dev, "Unable to allocate register map\n"); @@ -996,13 +1018,21 @@ static DEFINE_RUNTIME_DEV_PM_OPS(ina3221_pm, ina3221= _suspend, ina3221_resume, NULL); =20 static const struct of_device_id ina3221_of_match_table[] =3D { - { .compatible =3D "ti,ina3221", }, + { + .compatible =3D "silergy,sq52210", + .data =3D (void *)sq52210 + }, + { + .compatible =3D "ti,ina3221", + .data =3D (void *)ina3221 + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, ina3221_of_match_table); =20 static const struct i2c_device_id ina3221_ids[] =3D { - { "ina3221" }, + { "ina3221", ina3221 }, + { "sq52210", sq52210 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(i2c, ina3221_ids); --=20 2.17.1 From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FB0D32ED24; Thu, 2 Apr 2026 08:14:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117692; 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dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="OZ/PyqNx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=+v5Xg+kWjmKbK5f EihGrPO5x4iH9HqOpoWxZg+Vd674=; b=OZ/PyqNx93ikLYWnP2WAHx1kbf9ZyFg TQEyMH/+kr5JhxtQSOWwyilLJfxL34+0p8Io72x9VYezB9Inz3hSQ+w41MN3bw8G 0AldHEQoqRWW5DklZxHR7YauS3M7V15Af/xVurR6NQcuCynqDYHZxKbGr+GNpu8s 3ZVdV6zHsnoM= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgCX5UBEJc5pC9uuUw--.170S5; Thu, 02 Apr 2026 16:14:04 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 3/8] hwmon: (ina3221) Pre-calculate current and power LSB Date: Thu, 2 Apr 2026 04:13:45 -0400 Message-Id: <20260402081350.65559-4-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260402081350.65559-1-wenliang202407@163.com> References: <20260402081350.65559-1-wenliang202407@163.com> X-CM-TRANSID: QCgvCgCX5UBEJc5pC9uuUw--.170S5 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jr4kGF47WrW3Jw1kur1fCrg_yoW7XF4DpF 4rKr1rta40q3WfKa9Ikw4xGF1rtr97Jr42krZrWw1IqFsFkryqk3yrJFyDtFy5Ar15ZF13 X3y7tr4Duan2yaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRYLvtUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCvwxqPmnOJUwfBQAA3z Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The LSB for current and power can be pre-calculated for data read/write operations. The current LSB is determined by the calibration value and shunt resistor value, with the calibration value fixed within the driver. The power LSB can be derived from the current LSB. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 85 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 47ef4fe694ea..e99ac5ef4d8a 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -67,6 +67,7 @@ =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 +#define SQ52210_SHUNT_LSB 40000000 /* pV/LSB */ =20 enum ina3221_fields { /* Configuration */ @@ -121,8 +122,16 @@ struct ina3221_input { =20 enum ina3221_ids { ina3221, sq52210 }; =20 +struct ina3221_config { + bool has_current_reg; /* chip has internal current reg */ + bool has_power_reg; /* chip has internal power reg */ + int calibration_value; /* calculate current_lsb */ + int power_lsb_factor; +}; + /** * struct ina3221_data - device specific information + * @config: Used to store characteristics of different chips * @chip: Chip type identifier * @pm_dev: Device pointer for pm runtime * @regmap: Register map of the device @@ -131,9 +140,12 @@ enum ina3221_ids { ina3221, sq52210 }; * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE + * @current_lsb_uA: The value of one LSB corresponding to the current regi= ster + * @power_lsb_uW: The value of one LSB corresponding to the power register * @single_shot: running in single-shot operating mode */ struct ina3221_data { + const struct ina3221_config *config; enum ina3221_ids chip; =20 struct device *pm_dev; @@ -143,10 +155,30 @@ struct ina3221_data { u32 reg_config; int summation_shunt_resistor; u32 summation_channel_control; + long current_lsb_uA; + long power_lsb_uW; =20 bool single_shot; }; =20 +static const struct ina3221_config ina3221_config[] =3D { + [ina3221] =3D { + .has_current_reg =3D false, + .has_power_reg =3D false, + }, + [sq52210] =3D { + .has_current_reg =3D true, + .has_power_reg =3D true, + /* + * With this default value configuration, + * the following formula can be obtained: + * Current_LSB =3D Shunt_LSB / Rshunt + */ + .calibration_value =3D 256, + .power_lsb_factor =3D 20, + }, +}; + static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channe= l) { /* Summation channel checks shunt resistor values */ @@ -697,6 +729,25 @@ static const struct hwmon_chip_info ina3221_chip_info = =3D { }; =20 /* Extra attribute groups */ + +/* + * Calculate the value corresponding to one LSB of the current and + * power registers. + * formula : Current_LSB =3D Shunt_LSB / Rshunt + * Power_LSB =3D power_lsb_factor * Current_LSB + */ +static int ina3221_set_shunt(struct ina3221_data *ina, unsigned long val) +{ + if (!val || val > SQ52210_SHUNT_LSB) + return -EINVAL; + + ina->current_lsb_uA =3D DIV_ROUND_CLOSEST(SQ52210_SHUNT_LSB, val); + ina->power_lsb_uW =3D ina->config->power_lsb_factor * + ina->current_lsb_uA; + + return 0; +} + static ssize_t ina3221_shunt_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -730,6 +781,17 @@ static ssize_t ina3221_shunt_store(struct device *dev, /* Update summation_shunt_resistor for summation channel */ ina->summation_shunt_resistor =3D ina3221_summation_shunt_resistor(ina); =20 + /* + * The current and power registers can only be used when + * all enabled channels have identical shunt resistors + */ + if (ina->summation_shunt_resistor) { + if (ina->config->has_current_reg) { + ret =3D ina3221_set_shunt(ina, val); + if (ret < 0) + return ret; + } + } return count; } =20 @@ -846,6 +908,7 @@ static int ina3221_probe(struct i2c_client *client) return -ENOMEM; =20 ina->chip =3D chip; + ina->config =3D &ina3221_config[chip]; =20 ina->regmap =3D devm_regmap_init_i2c(client, &ina3221_regmap_config); if (IS_ERR(ina->regmap)) { @@ -892,6 +955,16 @@ static int ina3221_probe(struct i2c_client *client) ina->summation_channel_control |=3D BIT(14 - i); } =20 + /* + * The current and power registers can only be used when + * all enabled channels have identical shunt resistors + */ + if (ina->summation_shunt_resistor) { + ret =3D ina3221_set_shunt(ina, ina->summation_shunt_resistor); + if (ret < 0) + return ret; + } + ina->pm_dev =3D dev; dev_set_drvdata(dev, ina); =20 @@ -1009,6 +1082,18 @@ static int ina3221_resume(struct device *dev) dev_err(dev, "Unable to control summation channel\n"); return ret; } + /* + * The calibration register can only be enabled when all + * shunt resistor values are identical. + */ + if (ina->config->has_current_reg) { + ret =3D regmap_write(ina->regmap, SQ52210_CALIBRATION, + ina->config->calibration_value); + if (ret) { + dev_err(dev, "Unable to set calibration value\n"); + return ret; + } + } } =20 return 0; --=20 2.17.1 From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CE2B369213; Thu, 2 Apr 2026 08:14:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117696; cv=none; b=exICS5M8FL6HuwGzJZK5BXFV4N6Y1vWlnjdnXeUAFdsYLHWpcay4YfY5KinL8hqfmAg9zTAIwFV3ds4fDvafK3R3SUck62ZYs7EhkWXpKCEU7oKLmCJ1iIp+QqsdgP1eWo/zk+vkJuVfNjNw2U8S36k4DMzcVr/cLH0edPu8Hvo= ARC-Message-Signature: i=1; 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charset="utf-8" Add alert configuration for initialization and resume. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index e99ac5ef4d8a..74dd937cc568 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -65,6 +65,8 @@ =20 #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 +#define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) + #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 #define SQ52210_SHUNT_LSB 40000000 /* pV/LSB */ @@ -123,6 +125,7 @@ struct ina3221_input { enum ina3221_ids { ina3221, sq52210 }; =20 struct ina3221_config { + bool has_alerts_add; /* chip has addtional alert functions */ bool has_current_reg; /* chip has internal current reg */ bool has_power_reg; /* chip has internal power reg */ int calibration_value; /* calculate current_lsb */ @@ -140,6 +143,7 @@ struct ina3221_config { * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation * @summation_channel_control: Value written to SCC field in INA3221_MASK_= ENABLE + * @alert_type_select: Used to store the alert trigger type * @current_lsb_uA: The value of one LSB corresponding to the current regi= ster * @power_lsb_uW: The value of one LSB corresponding to the power register * @single_shot: running in single-shot operating mode @@ -155,6 +159,7 @@ struct ina3221_data { u32 reg_config; int summation_shunt_resistor; u32 summation_channel_control; + u32 alert_type_select; long current_lsb_uA; long power_lsb_uW; =20 @@ -163,10 +168,12 @@ struct ina3221_data { =20 static const struct ina3221_config ina3221_config[] =3D { [ina3221] =3D { + .has_alerts_add =3D false, .has_current_reg =3D false, .has_power_reg =3D false, }, [sq52210] =3D { + .has_alerts_add =3D true, .has_current_reg =3D true, .has_power_reg =3D true, /* @@ -948,6 +955,10 @@ static int ina3221_probe(struct i2c_client *client) ina->reg_config &=3D ~INA3221_CONFIG_CHx_EN(i); } =20 + /* Initialize alert_type_select */ + if (ina->config->has_alerts_add) + ina->alert_type_select =3D 0; + /* Initialize summation_shunt_resistor for summation channel control */ ina->summation_shunt_resistor =3D ina3221_summation_shunt_resistor(ina); for (i =3D 0; i < INA3221_NUM_CHANNELS; i++) { @@ -1096,6 +1107,17 @@ static int ina3221_resume(struct device *dev) } } =20 + /* Restore alert config register value to hardware */ + if (ina->config->has_alerts_add) { + ret =3D regmap_update_bits(ina->regmap, SQ52210_ALERT_CONFIG, + SQ52210_ALERT_CONFIG_MASK, + ina->alert_type_select & SQ52210_ALERT_CONFIG_MASK); + if (ret) { + dev_err(dev, "Unable to select alert type\n"); + return ret; + } + } + return 0; } =20 --=20 2.17.1 From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F3E33BC680; Thu, 2 Apr 2026 08:14:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117699; cv=none; b=nX3yjg2vrDuLoryyZqZxsxlSkNWycZ8IY9ozwiri6oiFA2fbKrgDDRA4rsqmS49NBkIGpE7/ZLdH6c93YTntfSLJgjv+LXQPAceWaln1Bam4CzMef9rsx4//QWpTMMdXB2JguDUvG3p7EFTiNhvPKOn9zKIeb/knQKavKFq7xVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117699; c=relaxed/simple; bh=nCEllRTgwqT6TYyQ3z6bOo7HSLfLd9xP3chQac1O5Ms=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; 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Thu, 02 Apr 2026 16:14:06 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Shuah Khan , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 5/8] hwmon: (ina3221) Introduce power attribute and alert characteristics Date: Thu, 2 Apr 2026 04:13:47 -0400 Message-Id: <20260402081350.65559-6-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260402081350.65559-1-wenliang202407@163.com> References: <20260402081350.65559-1-wenliang202407@163.com> X-CM-TRANSID: QCgvCgCX5UBEJc5pC9uuUw--.170S7 X-Coremail-Antispam: 1Uf129KBjvJXoWxtryfCryfCF48WFW5WF47CFg_yoW7WrW5pa ykX3yfJr18Ar93Zw4xKF4UXFn8t3yxGay7Jr1I9393J3ZrAr1vqr48K3W0qas0kryfur1F k34xXrWrGr13GrDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JjBuWQUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbC6BBrP2nOJVCviQAA3Y Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SQ52210 has built-in current and power sensors as well as multiple alert functions. Add power attributes and different critical characteristics in hwmon to report the corresponding data. Signed-off-by: Wenliang Yan --- Documentation/hwmon/ina3221.rst | 24 ++++++++++++++ drivers/hwmon/ina3221.c | 57 ++++++++++++++++++++++++++++++--- 2 files changed, 77 insertions(+), 4 deletions(-) diff --git a/Documentation/hwmon/ina3221.rst b/Documentation/hwmon/ina3221.= rst index 8c12c54d2c24..87637d7276ec 100644 --- a/Documentation/hwmon/ina3221.rst +++ b/Documentation/hwmon/ina3221.rst @@ -13,6 +13,13 @@ Supported chips: =20 https://www.ti.com/ =20 + * Silergy SQ52210 + + Prefix: 'SQ52210' + + Addresses: I2C 0x40 - 0x43 + + Author: Andrew F. Davis =20 Description @@ -23,6 +30,9 @@ side of up to three D.C. power supplies. The INA3221 moni= tors both shunt drop and supply voltage, with programmable conversion times and averaging, curr= ent and power are calculated host-side from these. =20 +The SQ52210 is a mostly compatible chip from Silergy. It incorporates inte= rnal +current and power registers, and provides an extra configurable alert func= tion. + Sysfs entries ------------- =20 @@ -72,3 +82,17 @@ update_interval Data conversion time in millisec= ond, following: Note that setting update_interval to 0ms sets both= BC and SC to 140 us (minimum conversion time). =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Additional sysfs entries for sq52210 +------------------------------------- + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +in[123]_crit Critical high bus voltage(mV) +in[123]_crit_alarm Bus voltage critical high alarm +in[123]_lcrit Critical low bus voltage(mV) +in[123]_lcrit_alarm Bus voltage critical low alarm +power[123]_input Power(uW) for channels 1, 2, and 3 respectively +power[123]_crit Critical high power(uW) +power[123]_crit_alarm Power critical high alarm +curr[123]_lcrit Critical low current(mA) +curr[123]_lcrit_alarm Current critical low alarm diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 74dd937cc568..a39f5f2c486b 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -645,6 +645,8 @@ static umode_t ina3221_is_visible(const void *drvdata, { const struct ina3221_data *ina =3D drvdata; const struct ina3221_input *input =3D NULL; + bool has_alerts_add =3D ina->config->has_alerts_add; + bool has_power_reg =3D ina->config->has_power_reg; =20 switch (type) { case hwmon_chip: @@ -672,6 +674,16 @@ static umode_t ina3221_is_visible(const void *drvdata, return 0444; case hwmon_in_enable: return 0644; + case hwmon_in_crit: + case hwmon_in_lcrit: + if (has_alerts_add) + return 0644; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + if (has_alerts_add) + return 0444; + return 0; default: return 0; } @@ -684,6 +696,31 @@ static umode_t ina3221_is_visible(const void *drvdata, case hwmon_curr_crit: case hwmon_curr_max: return 0644; + case hwmon_curr_lcrit_alarm: + if (has_alerts_add) + return 0444; + return 0; + case hwmon_curr_lcrit: + if (has_alerts_add) + return 0644; + return 0; + default: + return 0; + } + case hwmon_power: + switch (attr) { + case hwmon_power_input: + if (has_power_reg) + return 0444; + return 0; + case hwmon_power_crit_alarm: + if (has_power_reg) + return 0444; + return 0; + case hwmon_power_crit: + if (has_power_reg) + return 0644; + return 0; default: return 0; } @@ -694,7 +731,14 @@ static umode_t ina3221_is_visible(const void *drvdata, =20 #define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \ HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \ - HWMON_C_MAX | HWMON_C_MAX_ALARM) + HWMON_C_MAX | HWMON_C_MAX_ALARM | \ + HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM) +#define SQ52210_HWMON_POWER_CONFIG (HWMON_P_INPUT | \ + HWMON_P_CRIT | HWMON_P_CRIT_ALARM) +#define SQ52210_HWMON_BUS_CONFIG (HWMON_I_INPUT | \ + HWMON_I_ENABLE | HWMON_I_LABEL | \ + HWMON_I_LCRIT_ALARM | HWMON_I_LCRIT |\ + HWMON_I_CRIT_ALARM | HWMON_I_CRIT) =20 static const struct hwmon_channel_info * const ina3221_info[] =3D { HWMON_CHANNEL_INFO(chip, @@ -704,9 +748,9 @@ static const struct hwmon_channel_info * const ina3221_= info[] =3D { /* 0: dummy, skipped in is_visible */ HWMON_I_INPUT, /* 1-3: input voltage Channels */ - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, - HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, + SQ52210_HWMON_BUS_CONFIG, + SQ52210_HWMON_BUS_CONFIG, + SQ52210_HWMON_BUS_CONFIG, /* 4-6: shunt voltage Channels */ HWMON_I_INPUT, HWMON_I_INPUT, @@ -720,6 +764,11 @@ static const struct hwmon_channel_info * const ina3221= _info[] =3D { INA3221_HWMON_CURR_CONFIG, /* 4: summation of current channels */ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM), + HWMON_CHANNEL_INFO(power, + /* 1-3: power channels*/ + SQ52210_HWMON_POWER_CONFIG, + SQ52210_HWMON_POWER_CONFIG, + SQ52210_HWMON_POWER_CONFIG), NULL }; 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charset="utf-8" SQ52210 adds power, current, and limit registers. The ina3221_read_value function has been refactored to adapt to the new register data reading format. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 67 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index a39f5f2c486b..06e42512a235 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -66,6 +66,14 @@ #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) =20 #define SQ52210_ALERT_CONFIG_MASK GENMASK(15, 4) +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6)) +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5)) +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4)) + +#define SQ52210_ALERT_ALL_SUL_MASK (BIT(15) | BIT(14) | BIT(13)) +#define SQ52210_ALERT_ALL_BOL_MASK (BIT(12) | BIT(11) | BIT(10)) +#define SQ52210_ALERT_ALL_BUL_MASK (BIT(9) | BIT(8) | BIT(7)) +#define SQ52210_ALERT_ALL_POL_MASK (BIT(6) | BIT(5) | BIT(4)) =20 #define INA3221_CONFIG_DEFAULT 0x7127 #define INA3221_RSHUNT_DEFAULT 10000 @@ -108,6 +116,13 @@ enum ina3221_channels { INA3221_NUM_CHANNELS }; =20 +enum sq52210_alert_types { + SQ52210_ALERT_SUL, + SQ52210_ALERT_BOL, + SQ52210_ALERT_BUL, + SQ52210_ALERT_POL +}; + /** * struct ina3221_input - channel input source specific information * @label: label of channel input source @@ -284,13 +299,59 @@ static int ina3221_read_value(struct ina3221_data *in= a, unsigned int reg, =20 /* * Shunt Voltage Sum register has 14-bit value with 1-bit shift + * Current registers have 15-bit value + * Power registers have 16-bit value + * ALERT_LIMIT registers have 16-bit value with 3-bit shift * Other Shunt Voltage registers have 12 bits with 3-bit shift */ - if (reg =3D=3D INA3221_SHUNT_SUM || reg =3D=3D INA3221_CRIT_SUM) + switch (reg) { + case INA3221_SHUNT_SUM: + case INA3221_CRIT_SUM: *val =3D sign_extend32(regval >> 1, 14); - else + break; + case SQ52210_CURRENT1: + case SQ52210_CURRENT2: + case SQ52210_CURRENT3: + *val =3D sign_extend32(regval, 15); + break; + case SQ52210_POWER1: + case SQ52210_POWER2: + case SQ52210_POWER3: + *val =3D regval; + break; + case INA3221_BUS1: + case INA3221_BUS2: + case INA3221_BUS3: + case INA3221_SHUNT1: + case INA3221_SHUNT2: + case INA3221_SHUNT3: + case INA3221_WARN1: + case INA3221_WARN2: + case INA3221_WARN3: + case INA3221_CRIT1: + case INA3221_CRIT2: + case INA3221_CRIT3: *val =3D sign_extend32(regval >> 3, 12); - + break; + case SQ52210_ALERT_LIMIT1: + case SQ52210_ALERT_LIMIT2: + case SQ52210_ALERT_LIMIT3: + /* + * This register is a 16-bit register with the lower 3 bits fixed at 0. + * When used to store bus and shunt alert values, shifting is required. + * However, for POL (Power Over Limit), it functions as a 16-bit unsigned + * register where the lower 3 bits being fixed at 0 will result in some + * loss of precision. + */ + if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK) + *val =3D regval; + else + *val =3D sign_extend32(regval >> 3, 12); + break; + default: + *val =3D 0; + return -EOPNOTSUPP; + } return 0; } =20 --=20 2.17.1 From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 013CF3B894D; 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charset="utf-8" Each channel supports four new alert trigger modes, but only one trigger mode can be active at any given time. Alert values are stored in the same register. The sq52210_alert_limit_write function has been added to write alert threshold values and configure alert source type. SQ52210 adds power attributes to report power data and implements corresponding read/write functions for this purpose. This includes reading power values, reading alert thresholds, reading alert trigger status, and writing alert thresholds. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 176 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 06e42512a235..361d1be979e1 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -92,6 +92,9 @@ enum ina3221_fields { /* Alert Flags: SF is the summation-alert flag */ F_SF, F_CF3, F_CF2, F_CF1, =20 + /* Alert Flags: AFF is the alert function flag */ + F_AFF3, F_AFF2, F_AFF1, + /* sentinel */ F_MAX_FIELDS }; @@ -107,6 +110,10 @@ static const struct reg_field ina3221_reg_fields[] =3D= { [F_CF3] =3D REG_FIELD(INA3221_MASK_ENABLE, 7, 7), [F_CF2] =3D REG_FIELD(INA3221_MASK_ENABLE, 8, 8), [F_CF1] =3D REG_FIELD(INA3221_MASK_ENABLE, 9, 9), + + [F_AFF3] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 1, 1), + [F_AFF2] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 2, 2), + [F_AFF1] =3D REG_FIELD(SQ52210_ALERT_CONFIG, 3, 3), }; =20 enum ina3221_channels { @@ -123,6 +130,18 @@ enum sq52210_alert_types { SQ52210_ALERT_POL }; =20 +static const u32 alert_groups[] =3D { + SQ52210_MASK_ALERT_CHANNEL1, + SQ52210_MASK_ALERT_CHANNEL2, + SQ52210_MASK_ALERT_CHANNEL3, +}; + +static const u8 limit_regs[] =3D { + SQ52210_ALERT_LIMIT1, + SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3, +}; + /** * struct ina3221_input - channel input source specific information * @label: label of channel input source @@ -504,6 +523,145 @@ static int ina3221_read_curr(struct device *dev, u32 = attr, } } =20 +static const u8 ina3221_power_reg[][INA3221_NUM_CHANNELS] =3D { + [hwmon_power_input] =3D { SQ52210_POWER1, SQ52210_POWER2, SQ52210_POWER3 = }, + [hwmon_power_crit] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3 }, + [hwmon_power_crit_alarm] =3D { F_AFF1, F_AFF2, F_AFF3 }, +}; + +static int ina3221_read_power(struct device *dev, u32 attr, int channel, l= ong *val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + u8 reg =3D ina3221_power_reg[attr][channel]; + int regval, ret; + + switch (attr) { + case hwmon_power_input: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + /* Write CONFIG register to trigger a single-shot measurement */ + if (ina->single_shot) { + regmap_write(ina->regmap, INA3221_CONFIG, + ina->reg_config); + + ret =3D ina3221_wait_for_data(ina); + if (ret) + return ret; + } + + fallthrough; + case hwmon_power_crit: + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* Return power in uW */ + *val =3D (u64)regval * (u64)ina->power_lsb_uW; + return 0; + case hwmon_power_crit_alarm: + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val =3D 0; + return 0; + } + + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int sq52210_alert_limit_write(struct ina3221_data *ina, + enum sq52210_alert_types type, int channel, long val) +{ + struct regmap *regmap =3D ina->regmap; + int item =3D channel % INA3221_NUM_CHANNELS; + u8 limit_reg; + u32 alert_group, alert_mask =3D 0; + int regval =3D 0; + int ret; + + if (item >=3D ARRAY_SIZE(alert_groups) || (type =3D=3D SQ52210_ALERT_POL = && val < 0)) + return -EINVAL; + + alert_group =3D alert_groups[item]; + limit_reg =3D limit_regs[item]; + + /* Clear alerts for this channel group first */ + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0); + if (ret) + return ret; + + /* Determine alert type and calculate register value */ + switch (type) { + /* + * The alert warning logic is implemented by comparing the limit register= values + * with the corresponding alert source register values. The shunt voltage= and bus + * voltage are 13-bit signed values, while power is a 16-bit unsigned val= ue. + * However, the lower 3 bits of the limit register default to 0. Therefor= e, when + * setting warning values, the lower 3 bits will be forced to 0. + * The conversion formulas for the corresponding register values are: + * bus_voltage: (regval / 8mV) << 3 =3D=3D (regval / 1mV) + * shunt_voltage: (regval / 40uV) << 3 =3D=3D (regval / 5uV) + * current: (regval / current_lsb) & 0xfff8 + * power: (regval / current_lsb) & 0xfff8 + */ + case SQ52210_ALERT_SUL: + /* + * For SUL configuration, directly convert it to current + * settings implemented in the ina3221_write_curr function. + */ + return -EOPNOTSUPP; + case SQ52210_ALERT_BOL: + /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */ + alert_mask =3D BIT(12 - item); + /* Bus Register, signed register */ + regval =3D val & 0xfff8; + regval =3D clamp_val(regval, -32760, 32760); + break; + case SQ52210_ALERT_BUL: + /* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */ + alert_mask =3D BIT(9 - item); + /* Bus Register, signed register */ + regval =3D val & 0xfff8; + regval =3D clamp_val(regval, -32760, 32760); + break; + case SQ52210_ALERT_POL: + /* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */ + alert_mask =3D BIT(6 - item); + /* Power Register, unsigned register */ + regval =3D (u32)DIV_U64_ROUND_CLOSEST((u64)val, ina->power_lsb_uW); + regval =3D clamp_val(regval, 0, 65528) & 0xfff8; + break; + default: + /* For unsupported attributes, just clear the configuration */ + ina->alert_type_select &=3D ~alert_group; + return -EOPNOTSUPP; + } + + /* Write limit register value */ + ret =3D regmap_write(regmap, limit_reg, regval); + if (ret) + return ret; + + /* Update alert configuration if limit value is non-zero */ + if (regval) { + ina->alert_type_select =3D (ina->alert_type_select & ~alert_group) | ale= rt_mask; + ret =3D regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, + alert_group, alert_mask); + } else { + ina->alert_type_select &=3D ~alert_group; + } + + return ret; +} + static int ina3221_write_chip(struct device *dev, u32 attr, long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -640,6 +798,18 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_power_crit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_POL, channel, val); + default: + return 0; + } +} + static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { @@ -656,6 +826,9 @@ static int ina3221_read(struct device *dev, enum hwmon_= sensor_types type, case hwmon_curr: ret =3D ina3221_read_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_read_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; @@ -679,6 +852,9 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); break; + case hwmon_power: + ret =3D ina3221_write_power(dev, attr, channel, val); + break; default: ret =3D -EOPNOTSUPP; break; --=20 2.17.1 From nobody Fri Apr 10 17:37:28 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C50DE3612F0; Thu, 2 Apr 2026 08:14:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117692; cv=none; b=MlvrcJJfVASI7DAEZ3rgHYd9NKnyivyhPm4Gh4jz/JZvN7lUVXzZ69C41Ve8ru7Cxlnjh6ydBlqUGENdILQsp0HkYfS0+vby47IJuUbRUPIuozUKboY8TDEyGFDaP6uhdUdo5uCg2iLEuHP0roRf9tgwgbqN+weyVo2QQNa9PVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775117692; c=relaxed/simple; bh=2/1IqI0q4fTjZ9UA7RUZLwwfeD75hWqSzKmKTu22cY8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=R9hKuNjenT43xOqTs5i4Q60hOUzSEpBMMD/KCG48iUBl7EsfIqG4Q9vmJXhrJ1dtw9QCMebxTxVCetqzXzn6jFGgpJVwvR5LJAltdfUEgnvVko2oB1Y2jlNGwYEtz/sCyDHimx3/lZ8jC/i2S+JtyWI4W1nxp7SuS2LLeuqjklY= ARC-Authentication-Results: i=1; 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charset="utf-8" Modified the relevant read/write functions for 'in' and 'curr' attributes, adding support for crit, lcrit, crit_alarm, and lcrit_alarm features. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 109 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 102 insertions(+), 7 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 361d1be979e1..355a32702f33 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -142,6 +142,12 @@ static const u8 limit_regs[] =3D { SQ52210_ALERT_LIMIT3, }; =20 +static const u8 alert_flag[] =3D { + F_AFF1, + F_AFF2, + F_AFF3, +}; + /** * struct ina3221_input - channel input source specific information * @label: label of channel input source @@ -446,6 +452,42 @@ static int ina3221_read_in(struct device *dev, u32 att= r, int channel, long *val) case hwmon_in_enable: *val =3D ina3221_is_enabled(ina, channel); return 0; + case hwmon_in_crit: + case hwmon_in_lcrit: + /* Only for Bus Voltage */ + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + reg =3D limit_regs[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* + * Scale of bus voltage (mV): LSB is 8mV + */ + *val =3D regval * 8; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + /* Only for Bus Voltage */ + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val =3D 0; + return 0; + } + + reg =3D alert_flag[channel]; + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; default: return -EOPNOTSUPP; } @@ -457,8 +499,16 @@ static const u8 ina3221_curr_reg[][INA3221_NUM_CHANNEL= S + 1] =3D { [hwmon_curr_max] =3D { INA3221_WARN1, INA3221_WARN2, INA3221_WARN3, 0 }, [hwmon_curr_crit] =3D { INA3221_CRIT1, INA3221_CRIT2, INA3221_CRIT3, INA3221_CRIT_SUM }, + [hwmon_curr_lcrit] =3D { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2, + SQ52210_ALERT_LIMIT3, 0 }, [hwmon_curr_max_alarm] =3D { F_WF1, F_WF2, F_WF3, 0 }, [hwmon_curr_crit_alarm] =3D { F_CF1, F_CF2, F_CF3, F_SF }, + [hwmon_curr_lcrit_alarm] =3D { F_AFF1, F_AFF2, F_AFF3, 0 }, +}; +static const u8 sq52210_curr_reg[INA3221_NUM_CHANNELS] =3D { + SQ52210_CURRENT1, + SQ52210_CURRENT2, + SQ52210_CURRENT3 }; =20 static int ina3221_read_curr(struct device *dev, u32 attr, @@ -467,6 +517,7 @@ static int ina3221_read_curr(struct device *dev, u32 at= tr, struct ina3221_data *ina =3D dev_get_drvdata(dev); struct ina3221_input *input =3D ina->inputs; u8 reg =3D ina3221_curr_reg[attr][channel]; + bool has_current_reg =3D ina->config->has_current_reg; int resistance_uo, voltage_nv; int regval, ret; =20 @@ -489,10 +540,20 @@ static int ina3221_read_curr(struct device *dev, u32 = attr, if (ret) return ret; } + if (has_current_reg) { + reg =3D sq52210_curr_reg[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* Return current in mA */ + *val =3D DIV_U64_ROUND_CLOSEST((u64)regval * (u64)ina->current_lsb_uA, = 1000); + return 0; + } =20 fallthrough; case hwmon_curr_crit: case hwmon_curr_max: + case hwmon_curr_lcrit: if (!resistance_uo) return -ENODATA; =20 @@ -507,6 +568,7 @@ static int ina3221_read_curr(struct device *dev, u32 at= tr, return 0; case hwmon_curr_crit_alarm: case hwmon_curr_max_alarm: + case hwmon_curr_lcrit_alarm: /* No actual register read if channel is disabled */ if (!ina3221_is_enabled(ina, channel)) { /* Return 0 for alert flags */ @@ -617,7 +679,9 @@ static int sq52210_alert_limit_write(struct ina3221_dat= a *ina, * For SUL configuration, directly convert it to current * settings implemented in the ina3221_write_curr function. */ - return -EOPNOTSUPP; + alert_mask =3D BIT(15 - channel); + regval =3D val; + break; case SQ52210_ALERT_BOL: /* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */ alert_mask =3D BIT(12 - item); @@ -711,12 +775,18 @@ static int ina3221_write_curr(struct device *dev, u32= attr, struct ina3221_input *input =3D ina->inputs; u8 reg =3D ina3221_curr_reg[attr][channel]; int resistance_uo, current_ma, voltage_uv; - int regval; + int regval, ret; =20 - if (channel > INA3221_CHANNEL3) - resistance_uo =3D ina->summation_shunt_resistor; - else + if (attr =3D=3D hwmon_curr_lcrit) { + if (channel > INA3221_CHANNEL3) + return -EOPNOTSUPP; resistance_uo =3D input[channel].shunt_resistor; + } else { + if (channel > INA3221_CHANNEL3) + resistance_uo =3D ina->summation_shunt_resistor; + else + resistance_uo =3D input[channel].shunt_resistor; + } =20 if (!resistance_uo) return -EOPNOTSUPP; @@ -747,7 +817,12 @@ static int ina3221_write_curr(struct device *dev, u32 = attr, else regval =3D DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8; =20 - return regmap_write(ina->regmap, reg, regval); + if (attr =3D=3D hwmon_curr_lcrit) + ret =3D sq52210_alert_limit_write(ina, SQ52210_ALERT_SUL, channel, regva= l); + else + ret =3D regmap_write(ina->regmap, reg, regval); + + return ret; } =20 static int ina3221_write_enable(struct device *dev, int channel, bool enab= le) @@ -798,6 +873,26 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_in(struct device *dev, u32 attr, int channel, lon= g val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + if (attr =3D=3D hwmon_in_lcrit || attr =3D=3D hwmon_in_crit) + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + switch (attr) { + case hwmon_in_lcrit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_BUL, channel, val); + case hwmon_in_crit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_BOL, channel, val); + case hwmon_in_enable: + return ina3221_write_enable(dev, channel, val); + default: + return 0; + } +} + static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -847,7 +942,7 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, break; case hwmon_in: /* 0-align channel ID */ - ret =3D ina3221_write_enable(dev, channel - 1, val); + ret =3D ina3221_write_in(dev, attr, channel - 1, val); break; case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); --=20 2.17.1