From nobody Fri Apr 3 14:41:16 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A3F53914F7; Thu, 2 Apr 2026 07:43:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775115785; cv=none; b=qPBRquy41G48tXrjb3FHJ8wp8xKpyj6e9wy1ErM/ljKOOx/XjlYbMcW0+XX8saOKSTWx1Rx3RC6ut/2xOkf9/ilqeqeOddAByZUhIj/7wP9Q7llPFITkNZkEDxt3gxuD3M0AMVTQKiVdMgSeKd5aeofJ1Etc8eWuWIyZa5+VsRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775115785; c=relaxed/simple; bh=mU310XHwVhgPQM9cd8jQdkCSNVx1P5RF+mXZGiLsODw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cvcUqrkaKyJk3WAwjLVf1bJCsA06IDkbRXbAd+QUHX04dAmDAUtY2CRzYh04NsFb/gTPASgLPC9sKZ0vdhBq88D+uI0UYEitOHl4zE+DMjLNNkxIRSgB0cUKVwvOdOGwZ08NF+al2q0m8edtaabTDEEMCy3j7PJAj4OQrNYsAc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=QF+VoVN4; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="QF+VoVN4" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6327e37c92695625, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1775115603; bh=1mwq6gbcVd4xLMT8LBWMloWlO4wxBN9Av5xb3Dm1xE4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=QF+VoVN4zu3UVjfIwyTpvtPQL2Uvb2IuK0MH3PHmWHMqvmVNiMEPt3kFH5m9I7wmn 0G69vg0OuNcGjbtxQfyDuOz/MADfiyptYuPM2QWsyLQIj1VcTi9w5ult6Zb+Ts9THX LbkogtaCpWvnRbzHh0NkO/ySCpKsLD1X6lHGaKwOR4nYq3rU80XWfvzEqeonXiEvT0 zG/SRbC64AgXpvrsK8mnjp4YTvr6vwKbQiZBazzMn64tJIxeRcLINIH+GSlMmJKFhe qTLR9g8LdKLidrp09iDpfAMV8M6N1xv8pDIvwl4uk2ynmIbGy6zg//4uikdMBoe/bV Bfi14E0BLBG+A== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 6327e37c92695625 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 2 Apr 2026 15:40:03 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 2 Apr 2026 15:40:02 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 2 Apr 2026 15:40:02 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 2 Apr 2026 15:40:02 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v6 08/10] clk: realtek: Add RTD1625-CRT clock controller driver Date: Thu, 2 Apr 2026 15:39:55 +0800 Message-ID: <20260402073957.2742459-9-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260402073957.2742459-1-eleanor.lin@realtek.com> References: <20260402073957.2742459-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Add support for the CRT (Clock, Reset, and Test) domain clock controller on the Realtek RTD1625 SoC. This driver provides essential clock sources (including PLLs), gating, and multiplexing functionalities for the platform's peripherals. Since the reset controller shares the same register space with the CRT clock controller, it is instantiated as an auxiliary device by the core clock driver. This patch also includes the corresponding auxiliary reset driver to handle the CRT domain resets. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v6: - Add the headers used in c file to follow the "Include What You Use" princ= iple. - Move struct rtk_reset_desc array from the clock driver to the dedicated r= eset driver. - Implement and register a dedicated reset auxiliary driver. --- drivers/clk/realtek/Kconfig | 13 + drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-rtd1625-crt.c | 779 ++++++++++++++++++++++ drivers/reset/realtek/Kconfig | 2 + drivers/reset/realtek/Makefile | 2 +- drivers/reset/realtek/reset-rtd1625-crt.c | 186 ++++++ 6 files changed, 982 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/realtek/clk-rtd1625-crt.c create mode 100644 drivers/reset/realtek/reset-rtd1625-crt.c diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig index b31a31e57b3a..6a213cfd66bc 100644 --- a/drivers/clk/realtek/Kconfig +++ b/drivers/clk/realtek/Kconfig @@ -28,4 +28,17 @@ config RTK_CLK_COMMON config RTK_CLK_PLL_MMC bool =20 +config COMMON_CLK_RTD1625 + tristate "RTD1625 Clock Controller" + select RTK_CLK_COMMON + select RTK_CLK_PLL_MMC + help + Support for the clock controller on Realtek RTD1625 SoCs. + + This driver provides clock sources, gating, multiplexing, and + reset control for peripherals on the RTD1625 platform. + + Say Y here if your system is based on the RTD1625 and you need + its peripheral devices to function. + endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index fd7d777902c8..c992f97dfbc7 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -9,3 +9,4 @@ clk-rtk-y +=3D clk-regmap-mux.o clk-rtk-y +=3D freq_table.o =20 clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) +=3D clk-pll-mmc.o +obj-$(CONFIG_COMMON_CLK_RTD1625) +=3D clk-rtd1625-crt.o diff --git a/drivers/clk/realtek/clk-rtd1625-crt.c b/drivers/clk/realtek/cl= k-rtd1625-crt.c new file mode 100644 index 000000000000..fcb8b08722c8 --- /dev/null +++ b/drivers/clk/realtek/clk-rtd1625-crt.c @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk-pll.h" +#include "clk-regmap-gate.h" +#include "clk-regmap-mux.h" + +#define RTD1625_CRT_CLK_MAX 172 +#define RTD1625_CRT_RSTN_MAX 123 + +#define RTD1625_REG_PLL_ACPU1 0x10c +#define RTD1625_REG_PLL_ACPU2 0x110 +#define RTD1625_REG_PLL_SSC_DIG_ACPU0 0x5c0 +#define RTD1625_REG_PLL_SSC_DIG_ACPU1 0x5c4 +#define RTD1625_REG_PLL_SSC_DIG_ACPU2 0x5c8 +#define RTD1625_REG_PLL_SSC_DIG_ACPU_DBG2 0x5dc + +#define RTD1625_REG_PLL_VE1_1 0x114 +#define RTD1625_REG_PLL_VE1_2 0x118 +#define RTD1625_REG_PLL_SSC_DIG_VE1_0 0x580 +#define RTD1625_REG_PLL_SSC_DIG_VE1_1 0x584 +#define RTD1625_REG_PLL_SSC_DIG_VE1_2 0x588 +#define RTD1625_REG_PLL_SSC_DIG_VE1_DBG2 0x59c + +#define RTD1625_REG_PLL_GPU1 0x1c0 +#define RTD1625_REG_PLL_GPU2 0x1c4 +#define RTD1625_REG_PLL_SSC_DIG_GPU0 0x5a0 +#define RTD1625_REG_PLL_SSC_DIG_GPU1 0x5a4 +#define RTD1625_REG_PLL_SSC_DIG_GPU2 0x5a8 +#define RTD1625_REG_PLL_SSC_DIG_GPU_DBG2 0x5bc + +#define RTD1625_REG_PLL_NPU1 0x1c8 +#define RTD1625_REG_PLL_NPU2 0x1cc +#define RTD1625_REG_PLL_SSC_DIG_NPU0 0x800 +#define RTD1625_REG_PLL_SSC_DIG_NPU1 0x804 +#define RTD1625_REG_PLL_SSC_DIG_NPU2 0x808 +#define RTD1625_REG_PLL_SSC_DIG_NPU_DBG2 0x81c + +#define RTD1625_REG_PLL_VE2_1 0x1d0 +#define RTD1625_REG_PLL_VE2_2 0x1d4 +#define RTD1625_REG_PLL_SSC_DIG_VE2_0 0x5e0 +#define RTD1625_REG_PLL_SSC_DIG_VE2_1 0x5e4 +#define RTD1625_REG_PLL_SSC_DIG_VE2_2 0x5e8 +#define RTD1625_REG_PLL_SSC_DIG_VE2_DBG2 0x5fc + +#define RTD1625_REG_PLL_HIFI1 0x1d8 +#define RTD1625_REG_PLL_HIFI2 0x1dc +#define RTD1625_REG_PLL_SSC_DIG_HIFI0 0x6e0 +#define RTD1625_REG_PLL_SSC_DIG_HIFI1 0x6e4 +#define RTD1625_REG_PLL_SSC_DIG_HIFI2 0x6e8 +#define RTD1625_REG_PLL_SSC_DIG_HIFI_DBG2 0x6fc + +#define RTD1625_REG_PLL_BUS1 0x524 + +#define RTD1625_REG_PLL_SSC_DIG_DDSA1 0x564 + +#define RTD1625_REG_PLL_SSC_DIG_DCSB1 0x544 + +static const char * const clk_gpu_parents[] =3D {"pll_gpu", "clk_sys"}; +static CLK_REGMAP_MUX(clk_gpu, clk_gpu_parents, CLK_SET_RATE_PARENT | CLK_= SET_RATE_NO_REPARENT, + 0x28, 12, 0x1); +static const char * const clk_ve_parents[] =3D {"pll_vo", "clk_sysh", "pll= _ve1", "pll_ve2"}; +static CLK_REGMAP_MUX(clk_ve1, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_S= ET_RATE_NO_REPARENT, + 0x4c, 0, 0x3); +static CLK_REGMAP_MUX(clk_ve2, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_S= ET_RATE_NO_REPARENT, + 0x4c, 3, 0x3); +static CLK_REGMAP_MUX(clk_ve4, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_S= ET_RATE_NO_REPARENT, + 0x4c, 6, 0x3); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_misc, CLK_IS_CRITICAL, 0x50, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie0, 0, 0x50, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_gspi, 0, 0x50, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_iso_misc, 0, 0x50, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sds, 0, 0x50, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmi, 0, 0x50, 14, 1); +static CLK_REGMAP_GATE(clk_en_gpu, "clk_gpu", CLK_SET_RATE_PARENT, 0x50, 1= 8, 1); +static CLK_REGMAP_GATE(clk_en_ve1, "clk_ve1", CLK_SET_RATE_PARENT, 0x50, 2= 0, 1); +static CLK_REGMAP_GATE(clk_en_ve2, "clk_ve2", CLK_SET_RATE_PARENT, 0x50, 2= 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_se, 0, 0x50, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_md, 0, 0x54, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tp, CLK_IS_CRITICAL, 0x54, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_rcic, 0, 0x54, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_nf, 0, 0x54, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_emmc, 0, 0x54, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sd, 0, 0x54, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sdio_ip, 0, 0x54, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mipi_csi, 0, 0x54, 18, 1); +static CLK_REGMAP_GATE(clk_en_emmc_ip, "pll_emmc", CLK_SET_RATE_PARENT, 0x= 54, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sdio, 0, 0x54, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sd_ip, 0, 0x54, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tpb, 0, 0x54, 28, 1); +static CLK_REGMAP_GATE(clk_en_misc_sc1, "clk_en_misc", 0, 0x54, 30, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_3, "clk_en_misc", 0, 0x58, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_jpeg, 0, 0x58, 4, 1); +static CLK_REGMAP_GATE(clk_en_acpu, "pll_acpu", CLK_SET_RATE_PARENT, + 0x58, 6, 1); +static CLK_REGMAP_GATE(clk_en_misc_sc0, "clk_en_misc", 0, 0x58, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmirx, 0, 0x58, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hse, CLK_IS_CRITICAL, 0x58, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_fan, 0, 0x5c, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_wrap_sys, 0, 0x5c, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_wrap_sysh, 0, 0x5c, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_mac_sysh, 0, 0x5c, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_r2rdsc, 0, 0x5c, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie1, 0, 0x5c, 18, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_4, "clk_en_misc", 0, 0x5c, 20, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_5, "clk_en_misc", 0, 0x5c, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tsio, 0, 0x5c, 24, 1); +static CLK_REGMAP_GATE(clk_en_ve4, "clk_ve4", CLK_SET_RATE_PARENT, + 0x5c, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_edp, 0, 0x5c, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tsio_trx, 0, 0x5c, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie2, 0, 0x8c, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_earc, 0, 0x8c, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lite, 0, 0x8c, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mipi_dsi, 0, 0x8c, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npupp, 0, 0x8c, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npu, 0, 0x8c, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu0, 0, 0x8c, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu1, 0, 0x8c, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_nsram, 0, 0x8c, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmitop, 0, 0x8c, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu_iso_npu, 0, 0x8c, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_keyladder, 0, 0x8c, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ifcp_klm, 0, 0x8c, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ifcp, 0, 0x8c, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_genpw, 0, 0xb0, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_chip, 0, 0xb0, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_ip, 0, 0xb0, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdlm2m, 0, 0xb0, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_xtal, 0, 0xb0, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_test_mux, 0, 0xb0, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_dla, 0, 0xb0, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tpcw, 0, 0xb0, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_gpu_ts_src, 0, 0xb0, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_vi, 0, 0xb0, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lvds1, 0, 0xb0, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lvds2, 0, 0xb0, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu, 0, 0xb0, 28, 1); +static CLK_REGMAP_GATE(clk_en_ur1, "clk_en_ur_top", 0, 0x884, 0, 1); +static CLK_REGMAP_GATE(clk_en_ur2, "clk_en_ur_top", 0, 0x884, 2, 1); +static CLK_REGMAP_GATE(clk_en_ur3, "clk_en_ur_top", 0, 0x884, 4, 1); +static CLK_REGMAP_GATE(clk_en_ur4, "clk_en_ur_top", 0, 0x884, 6, 1); +static CLK_REGMAP_GATE(clk_en_ur5, "clk_en_ur_top", 0, 0x884, 8, 1); +static CLK_REGMAP_GATE(clk_en_ur6, "clk_en_ur_top", 0, 0x884, 10, 1); +static CLK_REGMAP_GATE(clk_en_ur7, "clk_en_ur_top", 0, 0x884, 12, 1); +static CLK_REGMAP_GATE(clk_en_ur8, "clk_en_ur_top", 0, 0x884, 14, 1); +static CLK_REGMAP_GATE(clk_en_ur9, "clk_en_ur_top", 0, 0x884, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ur_top, CLK_IS_CRITICAL, 0x884, 18= , 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_7, "clk_en_misc", 0, 0x884, 28, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_6, "clk_en_misc", 0, 0x884, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi0, 0, 0x894, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi1, 0, 0x894, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi2, 0, 0x894, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lsadc0, 0, 0x894, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lsadc1, 0, 0x894, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_isomis_dma, 0, 0x894, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_dptx, 0, 0x894, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npu_mipi_csi, 0, 0x894, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_edptx, 0, 0x894, 28, 1); + +#define FREQ_NF_MASK 0x7ffff +#define FREQ_NF(_r, _nf) {.rate =3D _r, .val =3D (_nf),} + +static const struct freq_table acpu_tbl[] =3D { + FREQ_NF(513000000, 0x11000), + FREQ_TABLE_END +}; + +static const struct freq_table ve_tbl[] =3D { + FREQ_NF(553500000, 0x12800), + FREQ_NF(661500000, 0x16800), + FREQ_NF(688500000, 0x17800), + FREQ_TABLE_END +}; + +static const struct freq_table bus_tbl[] =3D { + FREQ_NF(513000000, 0x11000), + FREQ_NF(540000000, 0x12000), + FREQ_NF(553500000, 0x12800), + FREQ_TABLE_END +}; + +static const struct freq_table ddsa_tbl[] =3D { + FREQ_NF(432000000, 0xe000), + FREQ_TABLE_END +}; + +static const struct freq_table gpu_tbl[] =3D { + FREQ_NF(405000000, 0xd000), + FREQ_NF(540000000, 0x12000), + FREQ_NF(661500000, 0x16800), + FREQ_NF(729000000, 0x19000), + FREQ_NF(810000000, 0x1c000), + FREQ_NF(850500000, 0x1d800), + FREQ_TABLE_END +}; + +static const struct freq_table hifi_tbl[] =3D { + FREQ_NF(756000000, 0x1a000), + FREQ_NF(810000000, 0x1c000), + FREQ_TABLE_END +}; + +static const struct freq_table npu_tbl[] =3D { + FREQ_NF(661500000, 0x16800), + FREQ_NF(729000000, 0x19000), + FREQ_NF(810000000, 0x1c000), + FREQ_TABLE_END +}; + +static const struct reg_sequence pll_acpu_seq_power_on[] =3D { + {RTD1625_REG_PLL_ACPU2, 0x5}, + {RTD1625_REG_PLL_ACPU2, 0x7}, + {RTD1625_REG_PLL_ACPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_ACPU2, 0x1e1f8e}, + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x5, 200}, + {RTD1625_REG_PLL_ACPU2, 0x3}, +}; + +static const struct reg_sequence pll_acpu_seq_power_off[] =3D { + {RTD1625_REG_PLL_ACPU2, 0x4}, +}; + +static const struct reg_sequence pll_acpu_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x4}, +}; + +static const struct reg_sequence pll_acpu_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x5}, +}; + +static struct clk_pll pll_acpu =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_acpu", "osc27m", &rtk_clk_pll_ops, CLK= _GET_RATE_NOCACHE), + .seq_power_on =3D pll_acpu_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_acpu_seq_power_on), + .seq_power_off =3D pll_acpu_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_acpu_seq_power_off), + .seq_pre_set_freq =3D pll_acpu_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_acpu_seq_pre_set_freq), + .seq_post_set_freq =3D pll_acpu_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_acpu_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_ACPU1, + .freq_tbl =3D acpu_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_ACPU_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_ACPU2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static const struct reg_sequence pll_ve1_seq_power_on[] =3D { + {RTD1625_REG_PLL_VE1_2, 0x5}, + {RTD1625_REG_PLL_VE1_2, 0x7}, + {RTD1625_REG_PLL_VE1_1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x5, 200}, + {RTD1625_REG_PLL_VE1_2, 0x3}, +}; + +static const struct reg_sequence pll_ve1_seq_power_off[] =3D { + {RTD1625_REG_PLL_VE1_2, 0x4}, +}; + +static const struct reg_sequence pll_ve1_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x4}, +}; + +static const struct reg_sequence pll_ve1_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x5}, +}; + +static struct clk_pll pll_ve1 =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_ve1", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_ve1_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_ve1_seq_power_on), + .seq_power_off =3D pll_ve1_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_ve1_seq_power_off), + .seq_pre_set_freq =3D pll_ve1_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_ve1_seq_pre_set_freq), + .seq_post_set_freq =3D pll_ve1_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_ve1_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_VE1_1, + .freq_tbl =3D ve_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_VE1_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_VE1_2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static struct clk_pll pll_ddsa =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_ddsa", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_DDSA1, + .freq_tbl =3D ddsa_tbl, + .freq_mask =3D FREQ_NF_MASK, +}; + +static struct clk_pll pll_bus =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_bus", "osc27m", &rtk_clk_pll_ro_ops, C= LK_GET_RATE_NOCACHE), + .freq_reg =3D RTD1625_REG_PLL_BUS1, + .freq_tbl =3D bus_tbl, + .freq_mask =3D FREQ_NF_MASK, +}; + +static CLK_FIXED_FACTOR(clk_sys, "clk_sys", "pll_bus", 2, 1, 0); + +static struct clk_pll pll_dcsb =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_dcsb", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_DCSB1, + .freq_tbl =3D bus_tbl, + .freq_mask =3D FREQ_NF_MASK, +}; + +static CLK_FIXED_FACTOR(clk_sysh, "clk_sysh", "pll_dcsb", 1, 1, 0); + +static const struct reg_sequence pll_gpu_seq_power_on[] =3D { + {RTD1625_REG_PLL_GPU2, 0x5}, + {RTD1625_REG_PLL_GPU2, 0x7}, + {RTD1625_REG_PLL_GPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x5, 200}, + {RTD1625_REG_PLL_GPU2, 0x3}, +}; + +static const struct reg_sequence pll_gpu_seq_power_off[] =3D { + {RTD1625_REG_PLL_GPU2, 0x4}, +}; + +static const struct reg_sequence pll_gpu_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x4}, +}; + +static const struct reg_sequence pll_gpu_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x5}, +}; + +static struct clk_pll pll_gpu =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_gpu", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_gpu_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_gpu_seq_power_on), + .seq_power_off =3D pll_gpu_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_gpu_seq_power_off), + .seq_pre_set_freq =3D pll_gpu_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_gpu_seq_pre_set_freq), + .seq_post_set_freq =3D pll_gpu_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_gpu_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_GPU1, + .freq_tbl =3D gpu_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_GPU_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_GPU2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static const struct reg_sequence pll_npu_seq_power_on[] =3D { + {RTD1625_REG_PLL_NPU2, 0x5}, + {RTD1625_REG_PLL_NPU2, 0x7}, + {RTD1625_REG_PLL_NPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x5, 200}, + {RTD1625_REG_PLL_NPU2, 0x3}, +}; + +static const struct reg_sequence pll_npu_seq_power_off[] =3D { + {RTD1625_REG_PLL_NPU2, 0x4}, + {RTD1625_REG_PLL_NPU1, 0x54010}, +}; + +static const struct reg_sequence pll_npu_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x4}, +}; + +static const struct reg_sequence pll_npu_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x5}, +}; + +static struct clk_pll pll_npu =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_npu", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_npu_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_npu_seq_power_on), + .seq_power_off =3D pll_npu_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_npu_seq_power_off), + .seq_pre_set_freq =3D pll_npu_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_npu_seq_pre_set_freq), + .seq_post_set_freq =3D pll_npu_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_npu_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_NPU1, + .freq_tbl =3D npu_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_NPU_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_NPU2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static CLK_FIXED_FACTOR(clk_npu, "clk_npu", "pll_npu", 1, 1, CLK_SET_RATE_= PARENT); +static CLK_FIXED_FACTOR(clk_npu_mipi_csi, "clk_npu_mipi_csi", "pll_npu", 1= , 1, + CLK_SET_RATE_PARENT); + +static const struct reg_sequence pll_ve2_seq_power_on[] =3D { + {RTD1625_REG_PLL_VE2_2, 0x5}, + {RTD1625_REG_PLL_VE2_2, 0x7}, + {RTD1625_REG_PLL_VE2_1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x5, 200}, + {RTD1625_REG_PLL_VE2_2, 0x3}, +}; + +static const struct reg_sequence pll_ve2_seq_power_off[] =3D { + {RTD1625_REG_PLL_VE2_2, 0x4}, +}; + +static const struct reg_sequence pll_ve2_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x4}, +}; + +static const struct reg_sequence pll_ve2_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x5}, +}; + +static struct clk_pll pll_ve2 =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_ve2", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_ve2_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_ve2_seq_power_on), + .seq_power_off =3D pll_ve2_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_ve2_seq_power_off), + .seq_pre_set_freq =3D pll_ve2_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_ve2_seq_pre_set_freq), + .seq_post_set_freq =3D pll_ve2_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_ve2_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_VE2_1, + .freq_tbl =3D ve_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_VE2_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_VE2_2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static const struct reg_sequence pll_hifi_seq_power_on[] =3D { + {RTD1625_REG_PLL_HIFI2, 0x5}, + {RTD1625_REG_PLL_HIFI2, 0x7}, + {RTD1625_REG_PLL_HIFI1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x5, 200}, + {RTD1625_REG_PLL_HIFI2, 0x3}, +}; + +static const struct reg_sequence pll_hifi_seq_power_off[] =3D { + {RTD1625_REG_PLL_HIFI2, 0x4}, +}; + +static const struct reg_sequence pll_hifi_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x4}, +}; + +static const struct reg_sequence pll_hifi_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x5}, +}; + +static struct clk_pll pll_hifi =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_hifi", "osc27m", &rtk_clk_pll_ops, CLK= _GET_RATE_NOCACHE), + .seq_power_on =3D pll_hifi_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_hifi_seq_power_on), + .seq_power_off =3D pll_hifi_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_hifi_seq_power_off), + .seq_pre_set_freq =3D pll_hifi_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_hifi_seq_pre_set_freq), + .seq_post_set_freq =3D pll_hifi_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_hifi_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_HIFI1, + .freq_tbl =3D hifi_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_HIFI_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_HIFI2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static CLK_FIXED_FACTOR(pll_emmc_ref, "pll_emmc_ref", "osc27m", 1, 1, 0); + +static struct clk_pll_mmc pll_emmc =3D { + .pll_ofs =3D 0x1f0, + .ssc_dig_ofs =3D 0x6b0, + .clkr.hw.init =3D CLK_HW_INIT("pll_emmc", "pll_emmc_ref", &rtk_clk_pll_= mmc_ops, 0), + .phase0_hw.init =3D CLK_HW_INIT("pll_emmc_vp0", "pll_emmc", &rtk_clk_pll_= mmc_phase_ops, 0), + .phase1_hw.init =3D CLK_HW_INIT("pll_emmc_vp1", "pll_emmc", &rtk_clk_pll_= mmc_phase_ops, 0), +}; + +static struct clk_regmap *rtd1625_crt_regmap_clks[] =3D { + &clk_en_misc.clkr, + &clk_en_pcie0.clkr, + &clk_en_gspi.clkr, + &clk_en_iso_misc.clkr, + &clk_en_sds.clkr, + &clk_en_hdmi.clkr, + &clk_en_gpu.clkr, + &clk_en_ve1.clkr, + &clk_en_ve2.clkr, + &clk_en_se.clkr, + &clk_en_md.clkr, + &clk_en_tp.clkr, + &clk_en_rcic.clkr, + &clk_en_nf.clkr, + &clk_en_emmc.clkr, + &clk_en_sd.clkr, + &clk_en_sdio_ip.clkr, + &clk_en_mipi_csi.clkr, + &clk_en_emmc_ip.clkr, + &clk_en_sdio.clkr, + &clk_en_sd_ip.clkr, + &clk_en_tpb.clkr, + &clk_en_misc_sc1.clkr, + &clk_en_misc_i2c_3.clkr, + &clk_en_jpeg.clkr, + &clk_en_acpu.clkr, + &clk_en_misc_sc0.clkr, + &clk_en_hdmirx.clkr, + &clk_en_hse.clkr, + &clk_en_fan.clkr, + &clk_en_sata_wrap_sys.clkr, + &clk_en_sata_wrap_sysh.clkr, + &clk_en_sata_mac_sysh.clkr, + &clk_en_r2rdsc.clkr, + &clk_en_pcie1.clkr, + &clk_en_misc_i2c_4.clkr, + &clk_en_misc_i2c_5.clkr, + &clk_en_tsio.clkr, + &clk_en_ve4.clkr, + &clk_en_edp.clkr, + &clk_en_tsio_trx.clkr, + &clk_en_pcie2.clkr, + &clk_en_earc.clkr, + &clk_en_lite.clkr, + &clk_en_mipi_dsi.clkr, + &clk_en_npupp.clkr, + &clk_en_npu.clkr, + &clk_en_aucpu0.clkr, + &clk_en_aucpu1.clkr, + &clk_en_nsram.clkr, + &clk_en_hdmitop.clkr, + &clk_en_aucpu_iso_npu.clkr, + &clk_en_keyladder.clkr, + &clk_en_ifcp_klm.clkr, + &clk_en_ifcp.clkr, + &clk_en_mdl_genpw.clkr, + &clk_en_mdl_chip.clkr, + &clk_en_mdl_ip.clkr, + &clk_en_mdlm2m.clkr, + &clk_en_mdl_xtal.clkr, + &clk_en_test_mux.clkr, + &clk_en_dla.clkr, + &clk_en_tpcw.clkr, + &clk_en_gpu_ts_src.clkr, + &clk_en_vi.clkr, + &clk_en_lvds1.clkr, + &clk_en_lvds2.clkr, + &clk_en_aucpu.clkr, + &clk_en_ur1.clkr, + &clk_en_ur2.clkr, + &clk_en_ur3.clkr, + &clk_en_ur4.clkr, + &clk_en_ur5.clkr, + &clk_en_ur6.clkr, + &clk_en_ur7.clkr, + &clk_en_ur8.clkr, + &clk_en_ur9.clkr, + &clk_en_ur_top.clkr, + &clk_en_misc_i2c_7.clkr, + &clk_en_misc_i2c_6.clkr, + &clk_en_spi0.clkr, + &clk_en_spi1.clkr, + &clk_en_spi2.clkr, + &clk_en_lsadc0.clkr, + &clk_en_lsadc1.clkr, + &clk_en_isomis_dma.clkr, + &clk_en_dptx.clkr, + &clk_en_npu_mipi_csi.clkr, + &clk_en_edptx.clkr, + &clk_gpu.clkr, + &clk_ve1.clkr, + &clk_ve2.clkr, + &clk_ve4.clkr, + &pll_ve1.clkr, + &pll_ddsa.clkr, + &pll_bus.clkr, + &pll_dcsb.clkr, + &pll_gpu.clkr, + &pll_npu.clkr, + &pll_ve2.clkr, + &pll_hifi.clkr, + &pll_emmc.clkr, + &pll_acpu.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_crt_hw_data =3D { + .num =3D RTD1625_CRT_CLK_MAX, + .hws =3D { + [RTD1625_CRT_CLK_EN_MISC] =3D &__clk_regmap_gate_hw(&clk_en_misc), + [RTD1625_CRT_CLK_EN_PCIE0] =3D &__clk_regmap_gate_hw(&clk_en_pcie0), + [RTD1625_CRT_CLK_EN_GSPI] =3D &__clk_regmap_gate_hw(&clk_en_gspi), + [RTD1625_CRT_CLK_EN_ISO_MISC] =3D &__clk_regmap_gate_hw(&clk_en_iso_misc= ), + [RTD1625_CRT_CLK_EN_SDS] =3D &__clk_regmap_gate_hw(&clk_en_sds), + [RTD1625_CRT_CLK_EN_HDMI] =3D &__clk_regmap_gate_hw(&clk_en_hdmi), + [RTD1625_CRT_CLK_EN_GPU] =3D &__clk_regmap_gate_hw(&clk_en_gpu), + [RTD1625_CRT_CLK_EN_VE1] =3D &__clk_regmap_gate_hw(&clk_en_ve1), + [RTD1625_CRT_CLK_EN_VE2] =3D &__clk_regmap_gate_hw(&clk_en_ve2), + [RTD1625_CRT_CLK_EN_MD] =3D &__clk_regmap_gate_hw(&clk_en_md), + [RTD1625_CRT_CLK_EN_TP] =3D &__clk_regmap_gate_hw(&clk_en_tp), + [RTD1625_CRT_CLK_EN_RCIC] =3D &__clk_regmap_gate_hw(&clk_en_rcic), + [RTD1625_CRT_CLK_EN_NF] =3D &__clk_regmap_gate_hw(&clk_en_nf), + [RTD1625_CRT_CLK_EN_EMMC] =3D &__clk_regmap_gate_hw(&clk_en_emmc), + [RTD1625_CRT_CLK_EN_SD] =3D &__clk_regmap_gate_hw(&clk_en_sd), + [RTD1625_CRT_CLK_EN_SDIO_IP] =3D &__clk_regmap_gate_hw(&clk_en_sdio_ip), + [RTD1625_CRT_CLK_EN_MIPI_CSI] =3D &__clk_regmap_gate_hw(&clk_en_mipi_csi= ), + [RTD1625_CRT_CLK_EN_EMMC_IP] =3D &__clk_regmap_gate_hw(&clk_en_emmc_ip), + [RTD1625_CRT_CLK_EN_SDIO] =3D &__clk_regmap_gate_hw(&clk_en_sdio), + [RTD1625_CRT_CLK_EN_SD_IP] =3D &__clk_regmap_gate_hw(&clk_en_sd_ip), + [RTD1625_CRT_CLK_EN_TPB] =3D &__clk_regmap_gate_hw(&clk_en_tpb), + [RTD1625_CRT_CLK_EN_MISC_SC1] =3D &__clk_regmap_gate_hw(&clk_en_misc_sc1= ), + [RTD1625_CRT_CLK_EN_MISC_I2C_3] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_3), + [RTD1625_CRT_CLK_EN_ACPU] =3D &__clk_regmap_gate_hw(&clk_en_acpu), + [RTD1625_CRT_CLK_EN_JPEG] =3D &__clk_regmap_gate_hw(&clk_en_jpeg), + [RTD1625_CRT_CLK_EN_MISC_SC0] =3D &__clk_regmap_gate_hw(&clk_en_misc_sc0= ), + [RTD1625_CRT_CLK_EN_HDMIRX] =3D &__clk_regmap_gate_hw(&clk_en_hdmirx), + [RTD1625_CRT_CLK_EN_HSE] =3D &__clk_regmap_gate_hw(&clk_en_hse), + [RTD1625_CRT_CLK_EN_FAN] =3D &__clk_regmap_gate_hw(&clk_en_fan), + [RTD1625_CRT_CLK_EN_SATA_WRAP_SYS] =3D &__clk_regmap_gate_hw(&clk_en_sat= a_wrap_sys), + [RTD1625_CRT_CLK_EN_SATA_WRAP_SYSH] =3D &__clk_regmap_gate_hw(&clk_en_sa= ta_wrap_sysh), + [RTD1625_CRT_CLK_EN_SATA_MAC_SYSH] =3D &__clk_regmap_gate_hw(&clk_en_sat= a_mac_sysh), + [RTD1625_CRT_CLK_EN_R2RDSC] =3D &__clk_regmap_gate_hw(&clk_en_r2rdsc), + [RTD1625_CRT_CLK_EN_PCIE1] =3D &__clk_regmap_gate_hw(&clk_en_pcie1), + [RTD1625_CRT_CLK_EN_MISC_I2C_4] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_4), + [RTD1625_CRT_CLK_EN_MISC_I2C_5] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_5), + [RTD1625_CRT_CLK_EN_TSIO] =3D &__clk_regmap_gate_hw(&clk_en_tsio), + [RTD1625_CRT_CLK_EN_VE4] =3D &__clk_regmap_gate_hw(&clk_en_ve4), + [RTD1625_CRT_CLK_EN_EDP] =3D &__clk_regmap_gate_hw(&clk_en_edp), + [RTD1625_CRT_CLK_EN_TSIO_TRX] =3D &__clk_regmap_gate_hw(&clk_en_tsio_trx= ), + [RTD1625_CRT_CLK_EN_PCIE2] =3D &__clk_regmap_gate_hw(&clk_en_pcie2), + [RTD1625_CRT_CLK_EN_EARC] =3D &__clk_regmap_gate_hw(&clk_en_earc), + [RTD1625_CRT_CLK_EN_LITE] =3D &__clk_regmap_gate_hw(&clk_en_lite), + [RTD1625_CRT_CLK_EN_MIPI_DSI] =3D &__clk_regmap_gate_hw(&clk_en_mipi_dsi= ), + [RTD1625_CRT_CLK_EN_NPUPP] =3D &__clk_regmap_gate_hw(&clk_en_npupp), + [RTD1625_CRT_CLK_EN_NPU] =3D &__clk_regmap_gate_hw(&clk_en_npu), + [RTD1625_CRT_CLK_EN_AUCPU0] =3D &__clk_regmap_gate_hw(&clk_en_aucpu0), + [RTD1625_CRT_CLK_EN_AUCPU1] =3D &__clk_regmap_gate_hw(&clk_en_aucpu1), + [RTD1625_CRT_CLK_EN_NSRAM] =3D &__clk_regmap_gate_hw(&clk_en_nsram), + [RTD1625_CRT_CLK_EN_HDMITOP] =3D &__clk_regmap_gate_hw(&clk_en_hdmitop), + [RTD1625_CRT_CLK_EN_AUCPU_ISO_NPU] =3D &__clk_regmap_gate_hw(&clk_en_auc= pu_iso_npu), + [RTD1625_CRT_CLK_EN_KEYLADDER] =3D &__clk_regmap_gate_hw(&clk_en_keyladd= er), + [RTD1625_CRT_CLK_EN_IFCP_KLM] =3D &__clk_regmap_gate_hw(&clk_en_ifcp_kl= m), + [RTD1625_CRT_CLK_EN_IFCP] =3D &__clk_regmap_gate_hw(&clk_en_ifcp), + [RTD1625_CRT_CLK_EN_MDL_GENPW] =3D &__clk_regmap_gate_hw(&clk_en_mdl_gen= pw), + [RTD1625_CRT_CLK_EN_MDL_CHIP] =3D &__clk_regmap_gate_hw(&clk_en_mdl_chi= p), + [RTD1625_CRT_CLK_EN_MDL_IP] =3D &__clk_regmap_gate_hw(&clk_en_mdl_ip), + [RTD1625_CRT_CLK_EN_MDLM2M] =3D &__clk_regmap_gate_hw(&clk_en_mdlm2m), + [RTD1625_CRT_CLK_EN_MDL_XTAL] =3D &__clk_regmap_gate_hw(&clk_en_mdl_xta= l), + [RTD1625_CRT_CLK_EN_TEST_MUX] =3D &__clk_regmap_gate_hw(&clk_en_test_mu= x), + [RTD1625_CRT_CLK_EN_DLA] =3D &__clk_regmap_gate_hw(&clk_en_dla), + [RTD1625_CRT_CLK_EN_TPCW] =3D &__clk_regmap_gate_hw(&clk_en_tpcw), + [RTD1625_CRT_CLK_EN_GPU_TS_SRC] =3D &__clk_regmap_gate_hw(&clk_en_gpu_ts= _src), + [RTD1625_CRT_CLK_EN_VI] =3D &__clk_regmap_gate_hw(&clk_en_vi), + [RTD1625_CRT_CLK_EN_LVDS1] =3D &__clk_regmap_gate_hw(&clk_en_lvds1), + [RTD1625_CRT_CLK_EN_LVDS2] =3D &__clk_regmap_gate_hw(&clk_en_lvds2), + [RTD1625_CRT_CLK_EN_AUCPU] =3D &__clk_regmap_gate_hw(&clk_en_aucpu), + [RTD1625_CRT_CLK_EN_UR1] =3D &__clk_regmap_gate_hw(&clk_en_ur1), + [RTD1625_CRT_CLK_EN_UR2] =3D &__clk_regmap_gate_hw(&clk_en_ur2), + [RTD1625_CRT_CLK_EN_UR3] =3D &__clk_regmap_gate_hw(&clk_en_ur3), + [RTD1625_CRT_CLK_EN_UR4] =3D &__clk_regmap_gate_hw(&clk_en_ur4), + [RTD1625_CRT_CLK_EN_UR5] =3D &__clk_regmap_gate_hw(&clk_en_ur5), + [RTD1625_CRT_CLK_EN_UR6] =3D &__clk_regmap_gate_hw(&clk_en_ur6), + [RTD1625_CRT_CLK_EN_UR7] =3D &__clk_regmap_gate_hw(&clk_en_ur7), + [RTD1625_CRT_CLK_EN_UR8] =3D &__clk_regmap_gate_hw(&clk_en_ur8), + [RTD1625_CRT_CLK_EN_UR9] =3D &__clk_regmap_gate_hw(&clk_en_ur9), + [RTD1625_CRT_CLK_EN_UR_TOP] =3D &__clk_regmap_gate_hw(&clk_en_ur_top), + [RTD1625_CRT_CLK_EN_MISC_I2C_7] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_7), + [RTD1625_CRT_CLK_EN_MISC_I2C_6] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_6), + [RTD1625_CRT_CLK_EN_SPI0] =3D &__clk_regmap_gate_hw(&clk_en_spi0), + [RTD1625_CRT_CLK_EN_SPI1] =3D &__clk_regmap_gate_hw(&clk_en_spi1), + [RTD1625_CRT_CLK_EN_SPI2] =3D &__clk_regmap_gate_hw(&clk_en_spi2), + [RTD1625_CRT_CLK_EN_LSADC0] =3D &__clk_regmap_gate_hw(&clk_en_lsadc0), + [RTD1625_CRT_CLK_EN_LSADC1] =3D &__clk_regmap_gate_hw(&clk_en_lsadc1), + [RTD1625_CRT_CLK_EN_ISOMIS_DMA] =3D &__clk_regmap_gate_hw(&clk_en_isomis= _dma), + [RTD1625_CRT_CLK_EN_DPTX] =3D &__clk_regmap_gate_hw(&clk_en_dptx), + [RTD1625_CRT_CLK_EN_NPU_MIPI_CSI] =3D &__clk_regmap_gate_hw(&clk_en_npu_= mipi_csi), + [RTD1625_CRT_CLK_EN_EDPTX] =3D &__clk_regmap_gate_hw(&clk_en_edptx), + [RTD1625_CRT_CLK_GPU] =3D &__clk_regmap_mux_hw(&clk_gpu), + [RTD1625_CRT_CLK_VE1] =3D &__clk_regmap_mux_hw(&clk_ve1), + [RTD1625_CRT_CLK_VE2] =3D &__clk_regmap_mux_hw(&clk_ve2), + [RTD1625_CRT_CLK_VE4] =3D &__clk_regmap_mux_hw(&clk_ve4), + [RTD1625_CRT_PLL_VE1] =3D &__clk_pll_hw(&pll_ve1), + [RTD1625_CRT_PLL_DDSA] =3D &__clk_pll_hw(&pll_ddsa), + [RTD1625_CRT_PLL_BUS] =3D &__clk_pll_hw(&pll_bus), + [RTD1625_CRT_CLK_SYS] =3D &clk_sys.hw, + [RTD1625_CRT_PLL_DCSB] =3D &__clk_pll_hw(&pll_dcsb), + [RTD1625_CRT_CLK_SYSH] =3D &clk_sysh.hw, + [RTD1625_CRT_PLL_GPU] =3D &__clk_pll_hw(&pll_gpu), + [RTD1625_CRT_PLL_NPU] =3D &__clk_pll_hw(&pll_npu), + [RTD1625_CRT_PLL_VE2] =3D &__clk_pll_hw(&pll_ve2), + [RTD1625_CRT_PLL_HIFI] =3D &__clk_pll_hw(&pll_hifi), + [RTD1625_CRT_PLL_EMMC_REF] =3D &pll_emmc_ref.hw, + [RTD1625_CRT_PLL_EMMC] =3D &__clk_pll_mmc_hw(&pll_emmc), + [RTD1625_CRT_PLL_EMMC_VP0] =3D &pll_emmc.phase0_hw, + [RTD1625_CRT_PLL_EMMC_VP1] =3D &pll_emmc.phase1_hw, + [RTD1625_CRT_PLL_ACPU] =3D &__clk_pll_hw(&pll_acpu), + [RTD1625_CRT_CLK_NPU] =3D &clk_npu.hw, + [RTD1625_CRT_CLK_NPU_MIPI_CSI] =3D &clk_npu_mipi_csi.hw, + + [RTD1625_CRT_CLK_MAX] =3D NULL, + }, +}; + +static const struct rtk_clk_desc rtd1625_crt_desc =3D { + .clk_data =3D &rtd1625_crt_hw_data, + .clks =3D rtd1625_crt_regmap_clks, + .num_clks =3D ARRAY_SIZE(rtd1625_crt_regmap_clks), +}; + +static int rtd1625_crt_probe(struct platform_device *pdev) +{ + const struct rtk_clk_desc *desc; + + desc =3D of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + return rtk_clk_probe(pdev, desc, "crt_rst"); +} + +static const struct of_device_id rtd1625_crt_match[] =3D { + {.compatible =3D "realtek,rtd1625-crt-clk", .data =3D &rtd1625_crt_desc,}, + {/* sentinel */} +}; + +static struct platform_driver rtd1625_crt_driver =3D { + .probe =3D rtd1625_crt_probe, + .driver =3D { + .name =3D "rtk-rtd1625-crt-clk", + .of_match_table =3D rtd1625_crt_match, + }, +}; + +static int __init rtd1625_crt_init(void) +{ + return platform_driver_register(&rtd1625_crt_driver); +} +subsys_initcall(rtd1625_crt_init); + +MODULE_DESCRIPTION("Reatek RTD1625 CRT Controller Driver"); +MODULE_AUTHOR("Cheng-Yu Lee "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_CLK"); diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig index 99a14d355803..a44c7834191c 100644 --- a/drivers/reset/realtek/Kconfig +++ b/drivers/reset/realtek/Kconfig @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only config RESET_RTK_COMMON bool + select AUXILIARY_BUS + default COMMON_CLK_RTD1625 diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile index b59a3f7f2453..8ca1fa939f10 100644 --- a/drivers/reset/realtek/Makefile +++ b/drivers/reset/realtek/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_RESET_RTK_COMMON) +=3D common.o +obj-$(CONFIG_RESET_RTK_COMMON) +=3D common.o reset-rtd1625-crt.o diff --git a/drivers/reset/realtek/reset-rtd1625-crt.c b/drivers/reset/real= tek/reset-rtd1625-crt.c new file mode 100644 index 000000000000..ebb15bb68885 --- /dev/null +++ b/drivers/reset/realtek/reset-rtd1625-crt.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include +#include "common.h" + +#define RTD1625_CRT_RSTN_MAX 123 + +static struct rtk_reset_desc rtd1625_crt_reset_descs[] =3D { + /* Bank 0: offset 0x0 */ + [RTD1625_CRT_RSTN_MISC] =3D { .ofs =3D 0x0, .bit =3D 0, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DIP] =3D { .ofs =3D 0x0, .bit =3D 2, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_GSPI] =3D { .ofs =3D 0x0, .bit =3D 4, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDS] =3D { .ofs =3D 0x0, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDS_REG] =3D { .ofs =3D 0x0, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDS_PHY] =3D { .ofs =3D 0x0, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_GPU2D] =3D { .ofs =3D 0x0, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DC_PHY] =3D { .ofs =3D 0x0, .bit =3D 22, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DCPHY_CRT] =3D { .ofs =3D 0x0, .bit =3D 24, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_LSADC] =3D { .ofs =3D 0x0, .bit =3D 26, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SE] =3D { .ofs =3D 0x0, .bit =3D 28, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DLA] =3D { .ofs =3D 0x0, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 1: offset 0x4 */ + [RTD1625_CRT_RSTN_JPEG] =3D { .ofs =3D 0x4, .bit =3D 0, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SD] =3D { .ofs =3D 0x4, .bit =3D 2, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDIO] =3D { .ofs =3D 0x4, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCR_CNT] =3D { .ofs =3D 0x4, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_STITCH] =3D { .ofs =3D 0x4, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY] =3D { .ofs =3D 0x4, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0] =3D { .ofs =3D 0x4, .bit =3D 14, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_CORE] =3D { .ofs =3D 0x4, .bit =3D 16, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_POWER] =3D { .ofs =3D 0x4, .bit =3D 18, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_NONSTICH] =3D { .ofs =3D 0x4, .bit =3D 20, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY_MDIO] =3D { .ofs =3D 0x4, .bit =3D 22, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO] =3D { .ofs =3D 0x4, .bit =3D 24, .wri= te_en =3D 1 }, + [RTD1625_CRT_RSTN_VO2] =3D { .ofs =3D 0x4, .bit =3D 28, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_MISC_SC0] =3D { .ofs =3D 0x4, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 2: offset 0x8 */ + [RTD1625_CRT_RSTN_MD] =3D { .ofs =3D 0x8, .bit =3D 4, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_LVDS1] =3D { .ofs =3D 0x8, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_LVDS2] =3D { .ofs =3D 0x8, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_MISC_SC1] =3D { .ofs =3D 0x8, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_I2C_3] =3D { .ofs =3D 0x8, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_FAN] =3D { .ofs =3D 0x8, .bit =3D 14, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_TVE] =3D { .ofs =3D 0x8, .bit =3D 16, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_AIO] =3D { .ofs =3D 0x8, .bit =3D 18, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_VO] =3D { .ofs =3D 0x8, .bit =3D 20, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_MIPI_CSI] =3D { .ofs =3D 0x8, .bit =3D 22, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_HDMIRX] =3D { .ofs =3D 0x8, .bit =3D 24, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_HDMIRX_WRAP] =3D { .ofs =3D 0x8, .bit =3D 26, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_HDMI] =3D { .ofs =3D 0x8, .bit =3D 28, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DISP] =3D { .ofs =3D 0x8, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 3: offset 0xc */ + [RTD1625_CRT_RSTN_SATA_PHY_POW1] =3D { .ofs =3D 0xc, .bit =3D 0, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SATA_PHY_POW0] =3D { .ofs =3D 0xc, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO1] =3D { .ofs =3D 0xc, .bit =3D 4, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO0] =3D { .ofs =3D 0xc, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_WRAP] =3D { .ofs =3D 0xc, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P1] =3D { .ofs =3D 0xc, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P0] =3D { .ofs =3D 0xc, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_COM] =3D { .ofs =3D 0xc, .bit =3D 14, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_STITCH] =3D { .ofs =3D 0xc, .bit =3D 16, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY] =3D { .ofs =3D 0xc, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1] =3D { .ofs =3D 0xc, .bit =3D 20, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_CORE] =3D { .ofs =3D 0xc, .bit =3D 22, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_POWER] =3D { .ofs =3D 0xc, .bit =3D 24, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_NONSTICH] =3D { .ofs =3D 0xc, .bit =3D 26, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY_MDIO] =3D { .ofs =3D 0xc, .bit =3D 28, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_HDMITOP] =3D { .ofs =3D 0xc, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 4: offset 0x68 */ + [RTD1625_CRT_RSTN_I2C_4] =3D { .ofs =3D 0x68, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_I2C_5] =3D { .ofs =3D 0x68, .bit =3D 4, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_TSIO] =3D { .ofs =3D 0x68, .bit =3D 6, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VI] =3D { .ofs =3D 0x68, .bit =3D 8, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_EDP] =3D { .ofs =3D 0x68, .bit =3D 10, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1_MMU] =3D { .ofs =3D 0x68, .bit =3D 12, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1_MMU_FUNC] =3D { .ofs =3D 0x68, .bit =3D 14, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_HSE_MMU] =3D { .ofs =3D 0x68, .bit =3D 16, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_HSE_MMU_FUNC] =3D { .ofs =3D 0x68, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDLM2M] =3D { .ofs =3D 0x68, .bit =3D 20, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_ISO_GSPI] =3D { .ofs =3D 0x68, .bit =3D 22, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SOFT_NPU] =3D { .ofs =3D 0x68, .bit =3D 24, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SPI2EMMC] =3D { .ofs =3D 0x68, .bit =3D 26, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_EARC] =3D { .ofs =3D 0x68, .bit =3D 28, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1] =3D { .ofs =3D 0x68, .bit =3D 30, .write_= en =3D 1 }, + /* Bank 5: offset 0x90 */ + [RTD1625_CRT_RSTN_PCIE2_STITCH] =3D { .ofs =3D 0x90, .bit =3D 0, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY] =3D { .ofs =3D 0x90, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2] =3D { .ofs =3D 0x90, .bit =3D 4, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_CORE] =3D { .ofs =3D 0x90, .bit =3D 6, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_POWER] =3D { .ofs =3D 0x90, .bit =3D 8, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_NONSTICH] =3D { .ofs =3D 0x90, .bit =3D 10, .writ= e_en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY_MDIO] =3D { .ofs =3D 0x90, .bit =3D 12, .writ= e_en =3D 1 }, + [RTD1625_CRT_RSTN_DCPHY_UMCTL2] =3D { .ofs =3D 0x90, .bit =3D 14, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MIPI_DSI] =3D { .ofs =3D 0x90, .bit =3D 16, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_HIFM] =3D { .ofs =3D 0x90, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_NSRAM] =3D { .ofs =3D 0x90, .bit =3D 20, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_AUCPU0_REG] =3D { .ofs =3D 0x90, .bit =3D 22, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDL_GENPW] =3D { .ofs =3D 0x90, .bit =3D 24, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDL_CHIP] =3D { .ofs =3D 0x90, .bit =3D 26, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDL_IP] =3D { .ofs =3D 0x90, .bit =3D 28, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_TEST_MUX] =3D { .ofs =3D 0x90, .bit =3D 30, .write_= en =3D 1 }, + /* Bank 6: offset 0xb8 */ + [RTD1625_CRT_RSTN_ISO_BIST] =3D { .ofs =3D 0xb8, .bit =3D 0, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MAIN_BIST] =3D { .ofs =3D 0xb8, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MAIN2_BIST] =3D { .ofs =3D 0xb8, .bit =3D 4, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1_BIST] =3D { .ofs =3D 0xb8, .bit =3D 6, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE2_BIST] =3D { .ofs =3D 0xb8, .bit =3D 8, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_DCPHY_BIST] =3D { .ofs =3D 0xb8, .bit =3D 10, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_GPU_BIST] =3D { .ofs =3D 0xb8, .bit =3D 12, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_DISP_BIST] =3D { .ofs =3D 0xb8, .bit =3D 14, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_NPU_BIST] =3D { .ofs =3D 0xb8, .bit =3D 16, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_CAS_BIST] =3D { .ofs =3D 0xb8, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE4_BIST] =3D { .ofs =3D 0xb8, .bit =3D 20, .write_= en =3D 1 }, + /* Bank 7: offset 0x454 (DUMMY0, no write_en) */ + [RTD1625_CRT_RSTN_EMMC] =3D { .ofs =3D 0x454, .bit =3D 0 }, + /* Bank 8: offset 0x458 (DUMMY1, no write_en) */ + [RTD1625_CRT_RSTN_GPU] =3D { .ofs =3D 0x458, .bit =3D 0 }, + /* Bank 9: offset 0x464 (DUMMY4, no write_en) */ + [RTD1625_CRT_RSTN_VE2] =3D { .ofs =3D 0x464, .bit =3D 0 }, + /* Bank 10: offset 0x880 */ + [RTD1625_CRT_RSTN_UR1] =3D { .ofs =3D 0x880, .bit =3D 0, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR2] =3D { .ofs =3D 0x880, .bit =3D 2, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR3] =3D { .ofs =3D 0x880, .bit =3D 4, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR4] =3D { .ofs =3D 0x880, .bit =3D 6, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR5] =3D { .ofs =3D 0x880, .bit =3D 8, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR6] =3D { .ofs =3D 0x880, .bit =3D 10, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR7] =3D { .ofs =3D 0x880, .bit =3D 12, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR8] =3D { .ofs =3D 0x880, .bit =3D 14, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR9] =3D { .ofs =3D 0x880, .bit =3D 16, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR_TOP] =3D { .ofs =3D 0x880, .bit =3D 18, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_I2C_7] =3D { .ofs =3D 0x880, .bit =3D 28, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_I2C_6] =3D { .ofs =3D 0x880, .bit =3D 30, .write= _en =3D 1 }, + /* Bank 11: offset 0x890 */ + [RTD1625_CRT_RSTN_SPI0] =3D { .ofs =3D 0x890, .bit =3D 0, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_SPI1] =3D { .ofs =3D 0x890, .bit =3D 2, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_SPI2] =3D { .ofs =3D 0x890, .bit =3D 4, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_LSADC0] =3D { .ofs =3D 0x890, .bit =3D 16, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_LSADC1] =3D { .ofs =3D 0x890, .bit =3D 18, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_ISOMIS_DMA] =3D { .ofs =3D 0x890, .bit =3D 20, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_AUDIO_ADC] =3D { .ofs =3D 0x890, .bit =3D 22, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_DPTX] =3D { .ofs =3D 0x890, .bit =3D 24, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_AUCPU1_REG] =3D { .ofs =3D 0x890, .bit =3D 26, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_EDPTX] =3D { .ofs =3D 0x890, .bit =3D 28, .write= _en =3D 1 }, +}; + +static int rtd1625_crt_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct rtk_reset_data *data; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->descs =3D rtd1625_crt_reset_descs; + data->rcdev.nr_resets =3D RTD1625_CRT_RSTN_MAX; + return rtk_reset_controller_add(dev, data); +} + +static const struct auxiliary_device_id rtd1625_crt_reset_ids[] =3D { + { + .name =3D "clk_rtk.crt_rst", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, rtd1625_crt_reset_ids); + +static struct auxiliary_driver rtd1625_crt_driver =3D { + .probe =3D rtd1625_crt_reset_probe, + .id_table =3D rtd1625_crt_reset_ids, + .driver =3D { + .name =3D "rtd1625-crt-reset", + }, +}; +module_auxiliary_driver(rtd1625_crt_driver); + +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_RESET"); --=20 2.34.1