From nobody Sun Apr 5 16:48:06 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18108325726; Thu, 2 Apr 2026 07:42:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775115778; cv=none; b=BdepCP+i4rjY15ZXVga/m5laN8Thba9+ENZwoPyeEugRp/csz2LMI75S+XLLAEGH6d2JE2AFTjGyFAVJwLrcNJA7mew+SHbly56YyenGJQt/Z+tDxMvtOWzcStmL3DzHV6VFp25yGyHU3MLXduBvuaJx2mDAms+MEvcFqtNqF3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775115778; c=relaxed/simple; bh=lOM7UJdML7x2kkKnQBqdAiF9huC2bMIMn85rZRVNl/s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MkHPuDiZd3OiYOmymWcKC8I2KUrMld/T1MqWVPycQ0ym/p6+TaJURyRPxZot6Cl0Gi4QJbdMwBtXMYH/qRWgNXPgXYM8lPd+QWkKT2/sJY6GMqf5tYRpRwFhR0uGA3Jc3c8Bmw+u1fTLYyxO/boq2Xte1pz6oKQhCd+7kisnbHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=KbmP2n2h; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="KbmP2n2h" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6327e1QL12695612, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1775115602; bh=hAp03RIE4ZX2JNI9VSy4kBUVv2tGpY6k+LhXl82S4do=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=KbmP2n2hIsnsyQP4f30DjZCO+z0q+dVZXOwmB4mtitTNwvMAITFUDlq9N8hAFVoH6 dxtV7VHZYuXlaD4/RESX5Dcbyhmtm2iWN+Y80U2fNEAuvcRaQf1URAlA+dMN4dI3RD EbsQnFPKCHtg1yrB9oE44wDqGGrHJisFKzTFDNl9d2KvFIjVOdUMWiG41TT6XSfYiW GX5u2LKm5BvcC5L5ogOHuXAkbHz9U+vXvNh+y1kLxhgJBGxQMzVtv3n5t1JYLll4Qh qlgxnRA8XWRfIE2BRGhPq7QGwchj7wL3a66fnDAKWK0mavafOXj/NwwZ7blyx9PB0Y etSu79sKRaQmQ== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 6327e1QL12695612 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 2 Apr 2026 15:40:02 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 2 Apr 2026 15:40:00 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 2 Apr 2026 15:40:00 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v6 05/10] clk: realtek: Add support for gate clock Date: Thu, 2 Apr 2026 15:39:52 +0800 Message-ID: <20260402073957.2742459-6-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260402073957.2742459-1-eleanor.lin@realtek.com> References: <20260402073957.2742459-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and disable_unused for standard regmap gate clocks. Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v6: - Add the headers used in c file to follow the "Include What You Use" princ= iple. --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-regmap-gate.c | 69 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index a89ad77993e9..74375f8127ac 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,5 +2,7 @@ obj-$(CONFIG_RTK_CLK_COMMON) +=3D clk-rtk.o =20 clk-rtk-y +=3D common.o + clk-rtk-y +=3D clk-pll.o +clk-rtk-y +=3D clk-regmap-gate.o clk-rtk-y +=3D freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/cl= k-regmap-gate.c new file mode 100644 index 000000000000..8738d6c6f8dd --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include "clk-regmap-gate.h" +#include + +static int clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg =3D to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask =3D BIT(clkg->bit_idx); + val =3D BIT(clkg->bit_idx); + + if (clkg->write_en) { + mask |=3D BIT(clkg->bit_idx + 1); + val |=3D BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static void clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg =3D to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask =3D BIT(clkg->bit_idx); + val =3D 0; + + if (clkg->write_en) { + mask |=3D BIT(clkg->bit_idx + 1); + val |=3D BIT(clkg->bit_idx + 1); + } + + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg =3D to_clk_regmap_gate(hw); + int ret; + u32 val; + + ret =3D regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops =3D { + .enable =3D clk_regmap_gate_enable, + .disable =3D clk_regmap_gate_disable, + .is_enabled =3D clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "REALTEK_CLK"); + +const struct clk_ops rtk_clk_regmap_gate_ro_ops =3D { + .is_enabled =3D clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "REALTEK_CLK"); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/cl= k-regmap-gate.h new file mode 100644 index 000000000000..b93357bd5a0d --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "common.h" + +struct clk_regmap_gate { + struct clk_regmap clkr; + int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __clk_regmap_gate_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, = \ + _write_en) \ + struct clk_regmap_gate _name =3D { \ + .clkr.hw.init =3D CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs =3D _ofs, \ + .bit_idx =3D _bit_idx, \ + .write_en =3D _write_en, \ + } + +#define CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en)= \ + __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs,= \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_= en) \ + __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, = \ + _ofs, _bit_idx, _write_en) + +#define __CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, = \ + _write_en) \ + struct clk_regmap_gate _name =3D { \ + .clkr.hw.init =3D CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs =3D _ofs, \ + .bit_idx =3D _bit_idx, \ + .write_en =3D _write_en, \ + } + +#define CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en= ) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs= , \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write= _en) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, = \ + _ofs, _bit_idx, _write_en) + +static inline struct clk_regmap_gate *to_clk_regmap_gate(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ --=20 2.34.1