From nobody Mon Apr 6 10:43:20 2026 Received: from server.couthit.com (server.couthit.com [162.240.164.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72F3D38AC8B; Thu, 2 Apr 2026 07:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.240.164.96 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775115616; cv=none; b=ev4fuQyivNaPnMrva2657DU6K2BkZkA5e/Dk9IIsZOR6nF+c7W9UxnkCZs/gdTTn7J0KgLzKQA7XtPOXz8jLVeFOfEPj03Kz4zosDNF5xA8870raQKuvJontqlbv/g+lwvgQWFQ0u9B/zXi6IcOsnitMABLYmusTZ+4bQ9yYI1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775115616; c=relaxed/simple; bh=V/hqpMoCLHxrhThAuZnRODfhvjICEkM0tx12jNGjO7A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nJ8KfSPg/fnIlCXnNg49rbkXxeowppVPfSqCwjJrBoUiXR3U6wVovAkC/PggAEmf3GqQ4w7TalWOfKl/IqBDoeTR9iN8zvQHIuUzUQaXTtycinbEW9MY4FDWbGdYsCaENIXIiSBuHUPU6LxTWciIgENmx9gUIdy9ZVno5fkha1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=couthit.com; spf=pass smtp.mailfrom=couthit.com; dkim=pass (2048-bit key) header.d=couthit.com header.i=@couthit.com header.b=0oRhmgnZ; arc=none smtp.client-ip=162.240.164.96 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=couthit.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=couthit.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=couthit.com header.i=@couthit.com header.b="0oRhmgnZ" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=couthit.com ; s=default; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZkURrzmHyx9TCHCbUwl75CvIGREuQWymqE0tmONEj6c=; b=0oRhmgnZLes0LMX8DuGkDyw6fN Frl71TY5Stn2XomGdm7E8S6+y3/QJcP1EEoywScrMJoEHotkMzL4NEqEK5scF8Bbxqnnc7H7ud+V9 msDqSgqLnpCuVUf16RgPluJQItyjvqoFz1sX/m0zaR8PfZstO/SQf8kmicGFQ9pC1BSDxDpa6CF97 jHOE/FeaUdt9QMJmfFCzQg6vi4L+DFQPlzoM58uDFDqBbpqwDJrgrYORh4+ONQdxs669k+zVW+VrS +zn5v8YPX0E0hkRMq+9Y1aVs/Tvk5s80WsW53o80MS8zg8hPzhRSsuFH3Xnd8AvyKSPtfrghPmAcm HmLDtn5A==; Received: from [115.246.246.98] (port=16281 helo=cypher.couthit.local) by server.couthit.com with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1w8Cev-00000008LE4-20Gd; Thu, 02 Apr 2026 03:40:10 -0400 From: Parvathi Pudi To: nm@ti.com, vigneshr@ti.com, afd@ti.com, khilman@baylibre.com, rogerq@kernel.org, tony@atomide.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com, aaro.koskinen@iki.fi, andreas@kemnade.info Cc: andrew@lunn.ch, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, danishanwar@ti.com, pratheesh@ti.com, j-rameshbabu@ti.com, praneeth@ti.com, srk@ti.com, rogerq@ti.com, krishna@couthit.com, mohan@couthit.com, pmohan@couthit.com, basharath@couthit.com, parvathi@couthit.com, Murali Karicheri Subject: [PATCH v6 3/3] arm: dts: ti: Add device tree support for PRU-ICSS on AM335x Date: Thu, 2 Apr 2026 13:06:41 +0530 Message-ID: <20260402073853.2170099-4-parvathi@couthit.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402073853.2170099-1-parvathi@couthit.com> References: <20260402073853.2170099-1-parvathi@couthit.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.couthit.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - couthit.com X-Get-Message-Sender-Via: server.couthit.com: authenticated_id: parvathi@couthit.com X-Authenticated-Sender: server.couthit.com: parvathi@couthit.com X-Source: X-Source-Args: X-Source-Dir: Content-Type: text/plain; charset="utf-8" From: Roger Quadros The TI Sitara AM335x ICE-V2 consists of single PRU-ICSS instance, This patch adds the new device tree overlay file in-order to enable PRU-ICSS instance, along with makefile changes. PRU-ICSS instance consists of two PRU cores along with various peripherals such as the Interrupt Controller (PRU_INTC), the Industrial Ethernet Peripheral(IEP), the Real Time Media Independent Interface controller (MII_RT), and the Enhanced Capture (eCAP) event module. am33xx-l4.dtsi - Adds IEP and eCAP peripheral as child nodes of the PRUSS subsystem node. am335x-icev2-prueth.dtso - Adds PRU-ICSS instance node along with PRU eth port information and corresponding port configuration. It includes interrupt mapping for packet reception, HW timestamp collection, and PRU Ethernet ports in MII mode, GPIO configuration, boot strapping along with delay configuration for individual PRU Ethernet port and other required nodes. Signed-off-by: Roger Quadros Signed-off-by: Andrew F. Davis Signed-off-by: Murali Karicheri Signed-off-by: Basharath Hussain Khaja Signed-off-by: Parvathi Pudi --- arch/arm/boot/dts/ti/omap/Makefile | 4 + .../ti/omap/am335x-icev2-prueth-overlay.dtso | 156 ++++++++++++++++++ arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 11 ++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.d= tso diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap= /Makefile index 3a4d9204339b..498c36ccb5ea 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -88,6 +88,9 @@ dtb-$(CONFIG_ARCH_OMAP4) +=3D \ am335x-bonegreen-hdmi-00a0-dtbs :=3D am335x-bonegreen-eco.dtb \ am335x-bone-hdmi-00a0.dtbo =20 +am335x-icev2-prueth-dtbs :=3D am335x-icev2.dtb \ + am335x-icev2-prueth-overlay.dtbo + dtb-$(CONFIG_SOC_AM33XX) +=3D \ am335x-baltos-ir2110.dtb \ am335x-baltos-ir3220.dtb \ @@ -106,6 +109,7 @@ dtb-$(CONFIG_SOC_AM33XX) +=3D \ am335x-evmsk.dtb \ am335x-guardian.dtb \ am335x-icev2.dtb \ + am335x-icev2-prueth.dtb \ am335x-lxm.dtb \ am335x-mba335x.dtb \ am335x-moxa-uc-2101.dtb \ diff --git a/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso b/a= rch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso new file mode 100644 index 000000000000..ffed1f3d046a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT overlay for IDK AM335x + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&{/} { + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible =3D "ti,am3359-prueth"; + ti,prus =3D <&pru0>, <&pru1>; + sram =3D <&ocmcram>; + ti,mii-rt =3D <&pruss_mii_rt>; + ti,iep =3D <&pruss_iep>; + ti,ecap =3D <&pruss_ecap>; + interrupts =3D <20 2 2>, <21 3 3>; + interrupt-names =3D "rx_hp", "rx_lp"; + interrupt-parent =3D <&pruss_intc>; + + pinctrl-0 =3D <&pruss_eth_default>; + pinctrl-names =3D "default"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + pruss_emac0: ethernet-port@0 { + reg =3D <0>; + phy-handle =3D <&pruss_eth0_phy>; + phy-mode =3D "mii"; + interrupts =3D <20 2 2>, <26 6 6>, <23 6 6= >; + interrupt-names =3D "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + + pruss_emac1: ethernet-port@1 { + reg =3D <1>; + phy-handle =3D <&pruss_eth1_phy>; + phy-mode =3D "mii"; + interrupts =3D <21 3 3>, <27 9 7>, <24 9 7= >; + interrupt-names =3D "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + }; + }; +}; + +&am33xx_pinmux { + /* MDIO node for PRU-ICSS */ + pruss_mdio_default: pruss-mdio-default-pins { + pinctrl-single,pins =3D < + AM33XX_IOPAD(0x88c, PIN_OUTPUT | MUX_MODE5) /* (V12) gpmc_clk.pr1_mdio_= mdclk */ + AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE5) /* (T13) gpmc_csn3.pr1_mdio_= data */ + >; + }; + + /* Pinmux configuration for PRU-ICSS */ + pruss_eth_default: pruss-eth-default-pins { + pinctrl-single,pins =3D < + AM33XX_IOPAD(0x8a0, PIN_INPUT | MUX_MODE2) /* (R1) lcd_data0.pr1_mii_mt= 0_clk */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE2) /* (T2) lcd_data5.pr1_mii0_= txd0 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE2) /* (T1) lcd_data4.pr1_mii0_= txd1 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE2) /* (R4) lcd_data3.pr1_mii0_= txd2 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE2) /* (R3) lcd_data2.pr1_mii0_= txd3 */ + AM33XX_IOPAD(0x8cc, PIN_INPUT | MUX_MODE5) /* (U4) lcd_data11.pr1_mii0_= rxd0 */ + AM33XX_IOPAD(0x8c8, PIN_INPUT | MUX_MODE5) /* (U3) lcd_data10.pr1_mii0_= rxd1 */ + AM33XX_IOPAD(0x8c4, PIN_INPUT | MUX_MODE5) /* (U2) lcd_data9.pr1_mii0_r= xd2 */ + AM33XX_IOPAD(0x8c0, PIN_INPUT | MUX_MODE5) /* (U1) lcd_data8.pr1_mii0_r= xd3 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE2) /* (R2) lcd_data1.pr1_mii0_= txen */ + AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE5) /* (V4) lcd_data14.pr1_mii_m= r0_clk */ + AM33XX_IOPAD(0x8dc, PIN_INPUT | MUX_MODE5) /* (T5) lcd_data15.pr1_mii0_= rxdv */ + AM33XX_IOPAD(0x8d4, PIN_INPUT | MUX_MODE5) /* (V3) lcd_data13.pr1_mii0_= rxer */ + AM33XX_IOPAD(0x8d0, PIN_INPUT | MUX_MODE5) /* (V2) lcd_data12.pr1_mii0_= rxlink */ + AM33XX_IOPAD(0x8e8, PIN_INPUT | MUX_MODE2) /* (V5) lcd_pclk.pr1_mii0_cr= s */ + + AM33XX_IOPAD(0x840, PIN_INPUT | MUX_MODE5) /* (R13) gpmc_a0.pr1_mii_mt1= _clk */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE5) /* (R14) gpmc_a4.pr1_mii1_t= xd0 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE5) /* (T14) gpmc_a3.pr1_mii1_t= xd1 */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE5) /* (U14) gpmc_a2.pr1_mii1_t= xd2 */ + AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE5) /* (V14) gpmc_a1.pr1_mii1_t= xd3 */ + AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE5) /* (V16) gpmc_a8.pr1_mii1_rx= d0 */ + AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE5) /* (T15) gpmc_a7.pr1_mii1_rx= d1 */ + AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE5) /* (U15) gpmc_a6.pr1_mii1_rx= d2 */ + AM33XX_IOPAD(0x854, PIN_INPUT | MUX_MODE5) /* (V15) gpmc_a5.pr1_mii1_rx= d3 */ + AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE5) /* (U17) gpmc_wpn.pr1_mii1_= txen */ + AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE5) /* (U16) gpmc_a9.pr1_mii_mr1= _clk */ + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE5) /* (T16) gpmc_a10.pr1_mii1_r= xdv */ + AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE5) /* (V17) gpmc_a11.pr1_mii1_r= xer */ + AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE5) /* (U18) gpmc_be1n.pr1_mii1_= rxlink */ + AM33XX_IOPAD(0x8ec, PIN_INPUT | MUX_MODE2) /* (R6) lcd_ac_bias_en.pr1_m= ii1_crs */ + >; + }; +}; + +&gpio3 { + mux-mii-hog { + status =3D "disabled"; + }; + + mux-mii-hog-0 { + gpio-hog; + gpios =3D <10 GPIO_ACTIVE_HIGH>; + /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ + output-low; + line-name =3D "MUX_MII_CTL1"; + }; +}; + +/* + * Disable CPSW switch node and + * MDIO configuration to prevent + * conflict with PRU-ICSS + */ +&mac_sw { + status =3D "disabled"; +}; + +&davinci_mdio_sw { + status =3D "disabled"; +}; + +/* PRU-ICSS MDIO configuration */ +&pruss_mdio { + pinctrl-0 =3D <&pruss_mdio_default>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us =3D <2>; /* PHY datasheet states 1uS min */ + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pruss_eth0_phy: ethernet-phy@1 { + reg =3D <1>; + }; + + pruss_eth1_phy: ethernet-phy@3 { + reg =3D <3>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/t= i/omap/am33xx-l4.dtsi index 89d16fcc773e..a63ef307d918 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -896,6 +896,17 @@ pruss_mii_rt: mii-rt@32000 { reg =3D <0x32000 0x58>; }; =20 + pruss_iep: iep@2e000 { + compatible =3D "ti,am3356-icss-iep"; + reg =3D <0x2e000 0x31c>; + clocks =3D <&pruss_iepclk_mux>; + }; + + pruss_ecap: ecap@30000 { + compatible =3D "ti,pruss-ecap"; + reg =3D <0x30000 0x60>; + }; + pruss_intc: interrupt-controller@20000 { compatible =3D "ti,pruss-intc"; reg =3D <0x20000 0x2000>; --=20 2.43.0