From nobody Sun Jun 14 09:53:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04D3F2EC0A2 for ; Thu, 2 Apr 2026 07:00:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775113217; cv=none; b=JDU48Yny7cSxEpxovpwGRQJ2RSuxy0CGqC3jdWG/LIRTikzoG+80zUX3q5QNOrqWd6inPNKuVmDzHMhyc5zY10T0TsmyMyvWsxInnf+BKI3xsdIJemi1P52uAaOZk0Y5lbADf6j16NYOqp8NTXyAYFdADpd0QjzIP5MWnePFe1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775113217; c=relaxed/simple; bh=tJ4Dq15RK4M6mzHsF8FTUDQ2iBWqSO2kO//BdFrz6DA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FPA1TQkZhbs1ZJfGCseBgJPyG7+4LsMuWYevHPFAjkPyfBwH96NJeG8OGbKW2LR17uVNZYP2SctoSsEVH0lHM+YKC5OrBC9UU3oAiGl3eoJO/F0ToLznpaRe9XxCVEzT4sWPDduF1Qpp5JpaHByD2Ua5p37mByb+3XC3lt6olSY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bCyJeXBo; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bCyJeXBo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775113216; x=1806649216; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tJ4Dq15RK4M6mzHsF8FTUDQ2iBWqSO2kO//BdFrz6DA=; b=bCyJeXBovYBaW8JFkGgKRZM1zkU4IeXOh7aOBuWbb5NE45kRyUGf07Gy gsn+W01yITbBBTykkjfpAp6v6GW0pb4pXG7NbMmcms78pRmepRZMUfQPr HJWWXO2PgT6j65ukAXdF43I913sTllV/j61bDZb9HfhER1DLdLObj6wN2 R5XLLb1j17P7FZUKTRutB/SsoVj3r4ilqSE/bi86jTVsQpXJ6ETXvpHED KCRKVRJ8PfiVWNdaH//fCB/ZoQotbEtnORbFy6Dty/OfuRvBKF+UGr9i7 m8d+eIgxTUCH3ZhWe+50gbUOSoWZvvFQrVkBeSZ2wyYiFK3ibq2zAG21B g==; X-CSE-ConnectionGUID: GheHx58gSFWD7VcCuuhSmg== X-CSE-MsgGUID: xBihEoWXQqyoFRrnV4qvtg== X-IronPort-AV: E=McAfee;i="6800,10657,11746"; a="76053618" X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="76053618" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2026 00:00:16 -0700 X-CSE-ConnectionGUID: X8Qzb7OiQTOJnPdElU6sQw== X-CSE-MsgGUID: acMaGRbvTRO6VXETyWiWhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="231847753" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:14 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 01/10] iommu/vt-d: Block PASID attachment to nested domain with dirty tracking Date: Thu, 2 Apr 2026 14:57:24 +0800 Message-ID: <20260402065734.1687476-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhenzhong Duan Kernel lacks dirty tracking support on nested domain attached to PASID, fails the attachment early if nesting parent domain is dirty tracking configured, otherwise dirty pages would be lost. Cc: stable@vger.kernel.org Fixes: 67f6f56b5912 ("iommu/vt-d: Add set_dev_pasid callback for nested dom= ain") Suggested-by: Kevin Tian Signed-off-by: Zhenzhong Duan Reviewed-by: Kevin Tian Reviewed-by: Yi Liu Link: https://lore.kernel.org/r/20260330101108.12594-2-zhenzhong.duan@intel= .com Signed-off-by: Lu Baolu --- drivers/iommu/intel/nested.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index 2b979bec56ce..16c82ba47d30 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -148,6 +148,7 @@ static int intel_nested_set_dev_pasid(struct iommu_doma= in *domain, { struct device_domain_info *info =3D dev_iommu_priv_get(dev); struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); + struct iommu_domain *s2_domain =3D &dmar_domain->s2_domain->domain; struct intel_iommu *iommu =3D info->iommu; struct dev_pasid_info *dev_pasid; int ret; @@ -155,10 +156,13 @@ static int intel_nested_set_dev_pasid(struct iommu_do= main *domain, if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) return -EOPNOTSUPP; =20 + if (s2_domain->dirty_ops) + return -EINVAL; + if (context_copied(iommu, info->bus, info->devfn)) return -EBUSY; =20 - ret =3D paging_domain_compatible(&dmar_domain->s2_domain->domain, dev); + ret =3D paging_domain_compatible(s2_domain, dev); if (ret) return ret; =20 --=20 2.43.0 From nobody Sun Jun 14 09:53:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E49C37FF7A for ; Thu, 2 Apr 2026 07:00:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775113218; cv=none; b=Ui2scdxD6GdcKdtbL6HW+dR7g7m8pDGrSvR1fvzhIlS4bqGLeWvT6pMDtaJP5iYXZdJe4lhHcuw8o1DGlMqdhW+yII4sbkbrQ8DabzvZKpq73madYjLuVYjURNz3fNlaQQvA5iVbsY2izQ6/2V35CyOECRv/3iR48mkdKCIY4s0= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="231847780" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:16 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 02/10] iommu/vt-d: Rename device_set_dirty_tracking() and pass dmar_domain pointer Date: Thu, 2 Apr 2026 14:57:25 +0800 Message-ID: <20260402065734.1687476-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhenzhong Duan device_set_dirty_tracking() sets dirty tracking on all devices attached to a domain, also on all PASIDs attached to same domain in subsequent patch. So rename it as domain_set_dirty_tracking() and pass dmar_domain pointer to better align to what it does. No functional changes intended. Suggested-by: Lu Baolu Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20260330101108.12594-3-zhenzhong.duan@intel= .com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index ef7613b177b9..965e0330ec4b 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3684,16 +3684,15 @@ static void *intel_iommu_hw_info(struct device *dev= , u32 *length, return vtd; } =20 -/* - * Set dirty tracking for the device list of a domain. The caller must - * hold the domain->lock when calling it. - */ -static int device_set_dirty_tracking(struct list_head *devices, bool enabl= e) +/* Set dirty tracking for the devices that the domain has been attached. */ +static int domain_set_dirty_tracking(struct dmar_domain *domain, bool enab= le) { struct device_domain_info *info; int ret =3D 0; =20 - list_for_each_entry(info, devices, link) { + lockdep_assert_held(&domain->lock); + + list_for_each_entry(info, &domain->devices, link) { ret =3D intel_pasid_setup_dirty_tracking(info->iommu, info->dev, IOMMU_NO_PASID, enable); if (ret) @@ -3713,7 +3712,7 @@ static int parent_domain_set_dirty_tracking(struct dm= ar_domain *domain, spin_lock(&domain->s1_lock); list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { spin_lock_irqsave(&s1_domain->lock, flags); - ret =3D device_set_dirty_tracking(&s1_domain->devices, enable); + ret =3D domain_set_dirty_tracking(s1_domain, enable); spin_unlock_irqrestore(&s1_domain->lock, flags); if (ret) goto err_unwind; @@ -3724,8 +3723,7 @@ static int parent_domain_set_dirty_tracking(struct dm= ar_domain *domain, err_unwind: list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { spin_lock_irqsave(&s1_domain->lock, flags); - device_set_dirty_tracking(&s1_domain->devices, - domain->dirty_tracking); + domain_set_dirty_tracking(s1_domain, domain->dirty_tracking); spin_unlock_irqrestore(&s1_domain->lock, flags); } spin_unlock(&domain->s1_lock); @@ -3742,7 +3740,7 @@ static int intel_iommu_set_dirty_tracking(struct iomm= u_domain *domain, if (dmar_domain->dirty_tracking =3D=3D enable) goto out_unlock; =20 - ret =3D device_set_dirty_tracking(&dmar_domain->devices, enable); + ret =3D domain_set_dirty_tracking(dmar_domain, enable); if (ret) goto err_unwind; =20 @@ -3759,8 +3757,7 @@ static int intel_iommu_set_dirty_tracking(struct iomm= u_domain *domain, return 0; =20 err_unwind: - device_set_dirty_tracking(&dmar_domain->devices, - dmar_domain->dirty_tracking); + domain_set_dirty_tracking(dmar_domain, dmar_domain->dirty_tracking); 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X-CSE-ConnectionGUID: Xo45vM8FRD6CcrqRQzADng== X-CSE-MsgGUID: VDyw9PkZQW2z3kATxeKicA== X-IronPort-AV: E=McAfee;i="6800,10657,11746"; a="76053629" X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="76053629" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2026 00:00:19 -0700 X-CSE-ConnectionGUID: T4MpjILjSBC/1qLdiRJKNw== X-CSE-MsgGUID: +O+6x2juQqy8iYjqKVgpaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="231847803" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:18 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 03/10] iommu/vt-d: Support dirty tracking on PASID Date: Thu, 2 Apr 2026 14:57:26 +0800 Message-ID: <20260402065734.1687476-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhenzhong Duan In order to support passthrough device with PASID capability in QEMU, e.g., DSA device, kernel needs to support attaching PASID to a domain. But attaching is not allowed if the domain is a second stage domain or nested domain with dirty tracking. The reason is kernel lacking support for dirty tracking on such domain attached to PASID. By adding dirty tracking on PASID, the check can be removed. Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20260330101108.12594-4-zhenzhong.duan@intel= .com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 12 +++++++++--- drivers/iommu/intel/nested.c | 6 +----- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 965e0330ec4b..26135ff3a289 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3618,9 +3618,6 @@ static int intel_iommu_set_dev_pasid(struct iommu_dom= ain *domain, if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) return -EOPNOTSUPP; =20 - if (domain->dirty_ops) - return -EINVAL; - if (context_copied(iommu, info->bus, info->devfn)) return -EBUSY; =20 @@ -3688,6 +3685,7 @@ static void *intel_iommu_hw_info(struct device *dev, = u32 *length, static int domain_set_dirty_tracking(struct dmar_domain *domain, bool enab= le) { struct device_domain_info *info; + struct dev_pasid_info *dev_pasid; int ret =3D 0; =20 lockdep_assert_held(&domain->lock); @@ -3695,6 +3693,14 @@ static int domain_set_dirty_tracking(struct dmar_dom= ain *domain, bool enable) list_for_each_entry(info, &domain->devices, link) { ret =3D intel_pasid_setup_dirty_tracking(info->iommu, info->dev, IOMMU_NO_PASID, enable); + if (ret) + return ret; + } + + list_for_each_entry(dev_pasid, &domain->dev_pasids, link_domain) { + info =3D dev_iommu_priv_get(dev_pasid->dev); + ret =3D intel_pasid_setup_dirty_tracking(info->iommu, info->dev, + dev_pasid->pasid, enable); if (ret) break; } diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index 16c82ba47d30..2b979bec56ce 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -148,7 +148,6 @@ static int intel_nested_set_dev_pasid(struct iommu_doma= in *domain, { struct device_domain_info *info =3D dev_iommu_priv_get(dev); struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); - struct iommu_domain *s2_domain =3D &dmar_domain->s2_domain->domain; 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charset="utf-8" From: Zhenzhong Duan Add test case for dirty tracking on a domain attached to PASID, also confirm attachment to PASID fail if device doesn't support dirty tracking. Suggested-by: Lu Baolu Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20260330101108.12594-5-zhenzhong.duan@intel= .com Signed-off-by: Lu Baolu --- tools/testing/selftests/iommu/iommufd.c | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selfte= sts/iommu/iommufd.c index dadad277f4eb..d1fe5dbc2813 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -2275,6 +2275,33 @@ TEST_F(iommufd_dirty_tracking, set_dirty_tracking) test_ioctl_destroy(hwpt_id); } =20 +TEST_F(iommufd_dirty_tracking, pasid_set_dirty_tracking) +{ + uint32_t stddev_id, ioas_id, hwpt_id, pasid =3D 100; + uint32_t dev_flags =3D MOCK_FLAGS_DEVICE_PASID; + + /* Regular case */ + test_cmd_hwpt_alloc(self->idev_id, self->ioas_id, + IOMMU_HWPT_ALLOC_PASID | IOMMU_HWPT_ALLOC_DIRTY_TRACKING, + &hwpt_id); + test_cmd_mock_domain_flags(hwpt_id, dev_flags, &stddev_id, NULL, NULL); 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charset="utf-8" From: Bjorn Helgaas dmar_readl() and dmar_readq() do nothing other than expand to the generic readl() and readq(), and the dmar_read*() wrappers are used inconsistently. Remove the dmar_read*() wrappers and use readl() and readq() directly. Signed-off-by: Bjorn Helgaas Reviewed-by: Samiullah Khawaja Link: https://lore.kernel.org/r/20260217214438.3395039-2-bhelgaas@google.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 2 -- drivers/iommu/intel/debugfs.c | 18 +++++++++--------- drivers/iommu/intel/dmar.c | 22 +++++++++++----------- drivers/iommu/intel/iommu.c | 10 +++++----- drivers/iommu/intel/irq_remapping.c | 2 +- drivers/iommu/intel/perfmon.c | 28 ++++++++++++++-------------- drivers/iommu/intel/prq.c | 12 ++++++------ 7 files changed, 46 insertions(+), 48 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 599913fb65d5..dbd8d196d154 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -148,9 +148,7 @@ =20 #define OFFSET_STRIDE (9) =20 -#define dmar_readq(a) readq(a) #define dmar_writeq(a,v) writeq(v,a) -#define dmar_readl(a) readl(a) #define dmar_writel(a, v) writel(v, a) =20 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) diff --git a/drivers/iommu/intel/debugfs.c b/drivers/iommu/intel/debugfs.c index 617fd81a80f0..21e4e465ca58 100644 --- a/drivers/iommu/intel/debugfs.c +++ b/drivers/iommu/intel/debugfs.c @@ -133,13 +133,13 @@ static int iommu_regset_show(struct seq_file *m, void= *unused) */ raw_spin_lock_irqsave(&iommu->register_lock, flag); for (i =3D 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) { - value =3D dmar_readl(iommu->reg + iommu_regs_32[i].offset); + value =3D readl(iommu->reg + iommu_regs_32[i].offset); seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", iommu_regs_32[i].regs, iommu_regs_32[i].offset, value); } for (i =3D 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) { - value =3D dmar_readq(iommu->reg + iommu_regs_64[i].offset); + value =3D readq(iommu->reg + iommu_regs_64[i].offset); seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", iommu_regs_64[i].regs, iommu_regs_64[i].offset, value); @@ -247,7 +247,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct int= el_iommu *iommu, u16 bus) tbl_wlk.ctx_entry =3D context; m->private =3D &tbl_wlk; =20 - if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { + if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { pasid_dir_ptr =3D context->lo & VTD_PAGE_MASK; pasid_dir_size =3D get_pasid_dir_size(context); pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size); @@ -285,7 +285,7 @@ static int dmar_translation_struct_show(struct seq_file= *m, void *unused) =20 rcu_read_lock(); for_each_active_iommu(iommu, drhd) { - sts =3D dmar_readl(iommu->reg + DMAR_GSTS_REG); + sts =3D readl(iommu->reg + DMAR_GSTS_REG); if (!(sts & DMA_GSTS_TES)) { seq_printf(m, "DMA Remapping is not enabled on %s\n", iommu->name); @@ -364,13 +364,13 @@ static int domain_translation_struct_show(struct seq_= file *m, if (seg !=3D iommu->segment) continue; =20 - sts =3D dmar_readl(iommu->reg + DMAR_GSTS_REG); + sts =3D readl(iommu->reg + DMAR_GSTS_REG); if (!(sts & DMA_GSTS_TES)) { seq_printf(m, "DMA Remapping is not enabled on %s\n", iommu->name); continue; } - if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) + if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) scalable =3D true; else scalable =3D false; @@ -538,8 +538,8 @@ static int invalidation_queue_show(struct seq_file *m, = void *unused) raw_spin_lock_irqsave(&qi->q_lock, flags); seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n", (u64)virt_to_phys(qi->desc), - dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, - dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); + readq(iommu->reg + DMAR_IQH_REG) >> shift, + readq(iommu->reg + DMAR_IQT_REG) >> shift); invalidation_queue_entry_show(m, iommu); raw_spin_unlock_irqrestore(&qi->q_lock, flags); seq_putc(m, '\n'); @@ -620,7 +620,7 @@ static int ir_translation_struct_show(struct seq_file *= m, void *unused) seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", iommu->name); =20 - sts =3D dmar_readl(iommu->reg + DMAR_GSTS_REG); + sts =3D readl(iommu->reg + DMAR_GSTS_REG); if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { irta =3D virt_to_phys(iommu->ir_table->base); seq_printf(m, " IR table address:%llx\n", irta); diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 69222dbd2af0..ae8b5ed70f22 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -899,8 +899,8 @@ dmar_validate_one_drhd(struct acpi_dmar_header *entry, = void *arg) return -EINVAL; } =20 - cap =3D dmar_readq(addr + DMAR_CAP_REG); - ecap =3D dmar_readq(addr + DMAR_ECAP_REG); + cap =3D readq(addr + DMAR_CAP_REG); + ecap =3D readq(addr + DMAR_ECAP_REG); =20 if (arg) iounmap(addr); @@ -982,8 +982,8 @@ static int map_iommu(struct intel_iommu *iommu, struct = dmar_drhd_unit *drhd) goto release; } =20 - iommu->cap =3D dmar_readq(iommu->reg + DMAR_CAP_REG); - iommu->ecap =3D dmar_readq(iommu->reg + DMAR_ECAP_REG); + iommu->cap =3D readq(iommu->reg + DMAR_CAP_REG); + iommu->ecap =3D readq(iommu->reg + DMAR_ECAP_REG); =20 if (iommu->cap =3D=3D (uint64_t)-1 && iommu->ecap =3D=3D (uint64_t)-1) { err =3D -EINVAL; @@ -1017,8 +1017,8 @@ static int map_iommu(struct intel_iommu *iommu, struc= t dmar_drhd_unit *drhd) int i; =20 for (i =3D 0; i < DMA_MAX_NUM_ECMDCAP; i++) { - iommu->ecmdcap[i] =3D dmar_readq(iommu->reg + DMAR_ECCAP_REG + - i * DMA_ECMD_REG_STEP); + iommu->ecmdcap[i] =3D readq(iommu->reg + DMAR_ECCAP_REG + + i * DMA_ECMD_REG_STEP); } } =20 @@ -1239,8 +1239,8 @@ static const char *qi_type_string(u8 type) =20 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault) { - unsigned int head =3D dmar_readl(iommu->reg + DMAR_IQH_REG); - u64 iqe_err =3D dmar_readq(iommu->reg + DMAR_IQER_REG); + unsigned int head =3D readl(iommu->reg + DMAR_IQH_REG); + u64 iqe_err =3D readq(iommu->reg + DMAR_IQER_REG); struct qi_desc *desc =3D iommu->qi->desc + head; =20 if (fault & DMA_FSTS_IQE) @@ -1321,7 +1321,7 @@ static int qi_check_fault(struct intel_iommu *iommu, = int index, int wait_index) * SID field is valid only when the ITE field is Set in FSTS_REG * see Intel VT-d spec r4.1, section 11.4.9.9 */ - iqe_err =3D dmar_readq(iommu->reg + DMAR_IQER_REG); + iqe_err =3D readq(iommu->reg + DMAR_IQER_REG); ite_sid =3D DMAR_IQER_REG_ITESID(iqe_err); =20 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); @@ -1980,8 +1980,8 @@ irqreturn_t dmar_fault(int irq, void *dev_id) source_id =3D dma_frcd_source_id(data); =20 pasid_present =3D dma_frcd_pasid_present(data); - guest_addr =3D dmar_readq(iommu->reg + reg + - fault_index * PRIMARY_FAULT_REG_LEN); + guest_addr =3D readq(iommu->reg + reg + + fault_index * PRIMARY_FAULT_REG_LEN); guest_addr =3D dma_frcd_page_addr(guest_addr); } =20 diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 26135ff3a289..4cb39000cd91 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -769,7 +769,7 @@ static void __iommu_flush_context(struct intel_iommu *i= ommu, =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, - dmar_readq, (!(val & DMA_CCMD_ICC)), val); + readq, (!(val & DMA_CCMD_ICC)), val); =20 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } @@ -811,7 +811,7 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16= did, u64 addr, =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, tlb_offset + 8, - dmar_readq, (!(val & DMA_TLB_IVT)), val); + readq, (!(val & DMA_TLB_IVT)), val); =20 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); =20 @@ -1533,7 +1533,7 @@ static int copy_translation_tables(struct intel_iommu= *iommu) int bus, ret; bool new_ext, ext; =20 - rtaddr_reg =3D dmar_readq(iommu->reg + DMAR_RTADDR_REG); + rtaddr_reg =3D readq(iommu->reg + DMAR_RTADDR_REG); ext =3D !!(rtaddr_reg & DMA_RTADDR_SMT); new_ext =3D !!sm_supported(iommu); =20 @@ -4188,7 +4188,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ec= md, u64 oa, u64 ob) =20 raw_spin_lock_irqsave(&iommu->register_lock, flags); =20 - res =3D dmar_readq(iommu->reg + DMAR_ECRSP_REG); + res =3D readq(iommu->reg + DMAR_ECRSP_REG); if (res & DMA_ECMD_ECRSP_IP) { ret =3D -EBUSY; goto err; @@ -4204,7 +4204,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ec= md, u64 oa, u64 ob) dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); =20 - IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq, + IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq, !(res & DMA_ECMD_ECRSP_IP), res); =20 if (res & DMA_ECMD_ECRSP_IP) { diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index 1cd2101610df..21e54e40a17f 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -422,7 +422,7 @@ static int iommu_load_old_irte(struct intel_iommu *iomm= u) u64 irta; =20 /* Check whether the old ir-table has the same size as ours */ - irta =3D dmar_readq(iommu->reg + DMAR_IRTA_REG); + irta =3D readq(iommu->reg + DMAR_IRTA_REG); if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) !=3D INTR_REMAP_TABLE_REG_SIZE) return -EINVAL; diff --git a/drivers/iommu/intel/perfmon.c b/drivers/iommu/intel/perfmon.c index fec51b6036b6..3f75f567f210 100644 --- a/drivers/iommu/intel/perfmon.c +++ b/drivers/iommu/intel/perfmon.c @@ -307,7 +307,7 @@ static void iommu_pmu_event_update(struct perf_event *e= vent) =20 again: prev_count =3D local64_read(&hwc->prev_count); - new_count =3D dmar_readq(iommu_event_base(iommu_pmu, hwc->idx)); + new_count =3D readq(iommu_event_base(iommu_pmu, hwc->idx)); if (local64_xchg(&hwc->prev_count, new_count) !=3D prev_count) goto again; =20 @@ -340,7 +340,7 @@ static void iommu_pmu_start(struct perf_event *event, i= nt flags) hwc->state =3D 0; =20 /* Always reprogram the period */ - count =3D dmar_readq(iommu_event_base(iommu_pmu, hwc->idx)); + count =3D readq(iommu_event_base(iommu_pmu, hwc->idx)); local64_set((&hwc->prev_count), count); =20 /* @@ -496,7 +496,7 @@ static void iommu_pmu_counter_overflow(struct iommu_pmu= *iommu_pmu) * Two counters may be overflowed very close. Always check * whether there are more to handle. */ - while ((status =3D dmar_readq(iommu_pmu->overflow))) { + while ((status =3D readq(iommu_pmu->overflow))) { for_each_set_bit(i, (unsigned long *)&status, iommu_pmu->num_cntr) { /* * Find the assigned event of the counter. @@ -518,7 +518,7 @@ static irqreturn_t iommu_pmu_irq_handler(int irq, void = *dev_id) { struct intel_iommu *iommu =3D dev_id; =20 - if (!dmar_readl(iommu->reg + DMAR_PERFINTRSTS_REG)) + if (!readl(iommu->reg + DMAR_PERFINTRSTS_REG)) return IRQ_NONE; =20 iommu_pmu_counter_overflow(iommu->pmu); @@ -555,7 +555,7 @@ static int __iommu_pmu_register(struct intel_iommu *iom= mu) static inline void __iomem * get_perf_reg_address(struct intel_iommu *iommu, u32 offset) { - u32 off =3D dmar_readl(iommu->reg + offset); + u32 off =3D readl(iommu->reg + offset); =20 return iommu->reg + off; } @@ -574,7 +574,7 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) if (!cap_ecmds(iommu->cap)) return -ENODEV; =20 - perfcap =3D dmar_readq(iommu->reg + DMAR_PERFCAP_REG); + perfcap =3D readq(iommu->reg + DMAR_PERFCAP_REG); /* The performance monitoring is not supported. */ if (!perfcap) return -ENODEV; @@ -617,8 +617,8 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) for (i =3D 0; i < iommu_pmu->num_eg; i++) { u64 pcap; =20 - pcap =3D dmar_readq(iommu->reg + DMAR_PERFEVNTCAP_REG + - i * IOMMU_PMU_CAP_REGS_STEP); + pcap =3D readq(iommu->reg + DMAR_PERFEVNTCAP_REG + + i * IOMMU_PMU_CAP_REGS_STEP); iommu_pmu->evcap[i] =3D pecap_es(pcap); } =20 @@ -651,9 +651,9 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) * Width. */ for (i =3D 0; i < iommu_pmu->num_cntr; i++) { - cap =3D dmar_readl(iommu_pmu->cfg_reg + - i * IOMMU_PMU_CFG_OFFSET + - IOMMU_PMU_CFG_CNTRCAP_OFFSET); + cap =3D readl(iommu_pmu->cfg_reg + + i * IOMMU_PMU_CFG_OFFSET + + IOMMU_PMU_CFG_CNTRCAP_OFFSET); if (!iommu_cntrcap_pcc(cap)) continue; =20 @@ -675,9 +675,9 @@ int alloc_iommu_pmu(struct intel_iommu *iommu) =20 /* Override with per-counter event capabilities */ for (j =3D 0; j < iommu_cntrcap_egcnt(cap); j++) { - cap =3D dmar_readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET + - IOMMU_PMU_CFG_CNTREVCAP_OFFSET + - (j * IOMMU_PMU_OFF_REGS_STEP)); + cap =3D readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET + + IOMMU_PMU_CFG_CNTREVCAP_OFFSET + + (j * IOMMU_PMU_OFF_REGS_STEP)); iommu_pmu->cntr_evcap[i][iommu_event_group(cap)] =3D iommu_event_select= (cap); /* * Some events may only be supported by a specific counter. diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c index ff63c228e6e1..c28fbd5c14a7 100644 --- a/drivers/iommu/intel/prq.c +++ b/drivers/iommu/intel/prq.c @@ -81,8 +81,8 @@ void intel_iommu_drain_pasid_prq(struct device *dev, u32 = pasid) */ prq_retry: reinit_completion(&iommu->prq_complete); - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; while (head !=3D tail) { struct page_req_dsc *req; =20 @@ -208,8 +208,8 @@ static irqreturn_t prq_event_thread(int irq, void *d) */ writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG); =20 - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; handled =3D (head !=3D tail); while (head !=3D tail) { req =3D &iommu->prq[head / sizeof(*req)]; @@ -268,8 +268,8 @@ static irqreturn_t prq_event_thread(int irq, void *d) if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) { pr_info_ratelimited("IOMMU: %s: PRQ overflow detected\n", iommu->name); - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; if (head =3D=3D tail) { iopf_queue_discard_partial(iommu->iopf_queue); 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X-CSE-ConnectionGUID: MsC5dIPgR024OYeo7+Xhlw== X-CSE-MsgGUID: cPZSL7PGQ0a3U1WvsPoxuA== X-IronPort-AV: E=McAfee;i="6800,10657,11746"; a="76053648" X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="76053648" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2026 00:00:24 -0700 X-CSE-ConnectionGUID: m4ZeuaxHQxilYY7rqznPGg== X-CSE-MsgGUID: //SQA9lbSoGsyO1Nrlk0Iw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="231847875" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:23 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 06/10] iommu/vt-d: Remove dmar_writel() and dmar_writeq() Date: Thu, 2 Apr 2026 14:57:29 +0800 Message-ID: <20260402065734.1687476-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bjorn Helgaas dmar_writel() and dmar_writeq() do nothing other than expand to the generic writel() and writeq(), and the dmar_write*() wrappers are used inconsistently. Remove the dmar_write*() wrappers and use writel() and writeq() directly. Signed-off-by: Bjorn Helgaas Reviewed-by: Samiullah Khawaja Link: https://lore.kernel.org/r/20260217214438.3395039-3-bhelgaas@google.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 3 --- drivers/iommu/intel/dmar.c | 2 +- drivers/iommu/intel/iommu.c | 12 ++++++------ drivers/iommu/intel/irq_remapping.c | 4 ++-- drivers/iommu/intel/perfmon.c | 22 +++++++++++----------- drivers/iommu/intel/prq.c | 14 +++++++------- 6 files changed, 27 insertions(+), 30 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index dbd8d196d154..10331364c0ef 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -148,9 +148,6 @@ =20 #define OFFSET_STRIDE (9) =20 -#define dmar_writeq(a,v) writeq(v,a) -#define dmar_writel(a, v) writel(v, a) - #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) #define DMAR_VER_MINOR(v) ((v) & 0x0f) =20 diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index ae8b5ed70f22..cd04c3f56eec 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1661,7 +1661,7 @@ static void __dmar_enable_qi(struct intel_iommu *iomm= u) /* write zero to the tail reg */ writel(0, iommu->reg + DMAR_IQT_REG); =20 - dmar_writeq(iommu->reg + DMAR_IQA_REG, val); + writeq(val, iommu->reg + DMAR_IQA_REG); =20 iommu->gcmd |=3D DMA_GCMD_QIE; writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 4cb39000cd91..297415fe726d 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -697,7 +697,7 @@ static void iommu_set_root_entry(struct intel_iommu *io= mmu) addr |=3D DMA_RTADDR_SMT; =20 raw_spin_lock_irqsave(&iommu->register_lock, flag); - dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); + writeq(addr, iommu->reg + DMAR_RTADDR_REG); =20 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); =20 @@ -765,7 +765,7 @@ static void __iommu_flush_context(struct intel_iommu *i= ommu, val |=3D DMA_CCMD_ICC; =20 raw_spin_lock_irqsave(&iommu->register_lock, flag); - dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); + writeq(val, iommu->reg + DMAR_CCMD_REG); =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, @@ -806,8 +806,8 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16= did, u64 addr, raw_spin_lock_irqsave(&iommu->register_lock, flag); /* Note: Only uses first TLB reg currently */ if (val_iva) - dmar_writeq(iommu->reg + tlb_offset, val_iva); - dmar_writeq(iommu->reg + tlb_offset + 8, val); + writeq(val_iva, iommu->reg + tlb_offset); + writeq(val, iommu->reg + tlb_offset + 8); =20 /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, tlb_offset + 8, @@ -4201,8 +4201,8 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ec= md, u64 oa, u64 ob) * - It's not invoked in any critical path. The extra MMIO * write doesn't bring any performance concerns. */ - dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); - dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); + writeq(ob, iommu->reg + DMAR_ECEO_REG); + writeq(ecmd | (oa << DMA_ECMD_OA_SHIFT), iommu->reg + DMAR_ECMD_REG); =20 IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq, !(res & DMA_ECMD_ECRSP_IP), res); diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index 21e54e40a17f..25c26f706984 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -465,8 +465,8 @@ static void iommu_set_irq_remapping(struct intel_iommu = *iommu, int mode) =20 raw_spin_lock_irqsave(&iommu->register_lock, flags); =20 - dmar_writeq(iommu->reg + DMAR_IRTA_REG, - (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); + writeq((addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE, + iommu->reg + DMAR_IRTA_REG); =20 /* Set interrupt-remapping table pointer */ writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); diff --git a/drivers/iommu/intel/perfmon.c b/drivers/iommu/intel/perfmon.c index 3f75f567f210..eb1df7a9b3c7 100644 --- a/drivers/iommu/intel/perfmon.c +++ b/drivers/iommu/intel/perfmon.c @@ -99,20 +99,20 @@ IOMMU_PMU_ATTR(filter_page_table, "config2:32-36", IOMM= U_PMU_FILTER_PAGE_TABLE); #define iommu_pmu_set_filter(_name, _config, _filter, _idx, _econfig) \ { \ if ((iommu_pmu->filter & _filter) && iommu_pmu_en_##_name(_econfig)) { \ - dmar_writel(iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ - IOMMU_PMU_CFG_SIZE + \ - (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET, \ - iommu_pmu_get_##_name(_config) | IOMMU_PMU_FILTER_EN);\ + writel(iommu_pmu_get_##_name(_config) | IOMMU_PMU_FILTER_EN, \ + iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ + IOMMU_PMU_CFG_SIZE + \ + (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET); \ } \ } =20 #define iommu_pmu_clear_filter(_filter, _idx) \ { \ if (iommu_pmu->filter & _filter) { \ - dmar_writel(iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ - IOMMU_PMU_CFG_SIZE + \ - (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET, \ - 0); \ + writel(0, \ + iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \ + IOMMU_PMU_CFG_SIZE + \ + (ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET); \ } \ } =20 @@ -411,7 +411,7 @@ static int iommu_pmu_assign_event(struct iommu_pmu *iom= mu_pmu, hwc->idx =3D idx; =20 /* config events */ - dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config); + writeq(hwc->config, iommu_config_base(iommu_pmu, idx)); =20 iommu_pmu_set_filter(requester_id, event->attr.config1, IOMMU_PMU_FILTER_REQUESTER_ID, idx, @@ -510,7 +510,7 @@ static void iommu_pmu_counter_overflow(struct iommu_pmu= *iommu_pmu) iommu_pmu_event_update(event); } =20 - dmar_writeq(iommu_pmu->overflow, status); + writeq(status, iommu_pmu->overflow); } } =20 @@ -524,7 +524,7 @@ static irqreturn_t iommu_pmu_irq_handler(int irq, void = *dev_id) iommu_pmu_counter_overflow(iommu->pmu); =20 /* Clear the status bit */ - dmar_writel(iommu->reg + DMAR_PERFINTRSTS_REG, DMA_PERFINTRSTS_PIS); + writel(DMA_PERFINTRSTS_PIS, iommu->reg + DMAR_PERFINTRSTS_REG); =20 return IRQ_HANDLED; } diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c index c28fbd5c14a7..1460b57db129 100644 --- a/drivers/iommu/intel/prq.c +++ b/drivers/iommu/intel/prq.c @@ -259,7 +259,7 @@ static irqreturn_t prq_event_thread(int irq, void *d) head =3D (head + sizeof(*req)) & PRQ_RING_MASK; } =20 - dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); + writeq(tail, iommu->reg + DMAR_PQH_REG); =20 /* * Clear the page request overflow bit and wake up all threads that @@ -325,9 +325,9 @@ int intel_iommu_enable_prq(struct intel_iommu *iommu) iommu->name); goto free_iopfq; } - dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORD= ER); + writeq(0ULL, iommu->reg + DMAR_PQH_REG); + writeq(0ULL, iommu->reg + DMAR_PQT_REG); + writeq(virt_to_phys(iommu->prq) | PRQ_ORDER, iommu->reg + DMAR_PQA_REG); =20 init_completion(&iommu->prq_complete); =20 @@ -348,9 +348,9 @@ int intel_iommu_enable_prq(struct intel_iommu *iommu) =20 int intel_iommu_finish_prq(struct intel_iommu *iommu) { - dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); 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d="scan'208";a="231847883" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:25 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 07/10] iommu/vt-d: Split piotlb invalidation into range and all Date: Thu, 2 Apr 2026 14:57:30 +0800 Message-ID: <20260402065734.1687476-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Currently these call chains are muddled up by using npages=3D-1, but only one caller has the possibility to do both options. Simplify qi_flush_piotlb() to qi_flush_piotlb_all() since all callers pass npages=3D-1. Split qi_batch_add_piotlb() into qi_batch_add_piotlb_all() and related helpers. Signed-off-by: Jason Gunthorpe Link: https://lore.kernel.org/r/1-v1-f175e27af136+11647-iommupt_inv_vtd_jgg= @nvidia.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 39 +++++++++++++++++-------------------- drivers/iommu/intel/cache.c | 20 ++++++++++++------- drivers/iommu/intel/dmar.c | 19 ++++-------------- drivers/iommu/intel/pasid.c | 6 +++--- drivers/iommu/intel/prq.c | 2 +- 5 files changed, 39 insertions(+), 47 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 10331364c0ef..9b193bbcfd58 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -1077,31 +1077,29 @@ static inline void qi_desc_dev_iotlb(u16 sid, u16 p= fsid, u16 qdep, u64 addr, desc->qw3 =3D 0; } =20 +/* PASID-selective IOTLB invalidation */ +static inline void qi_desc_piotlb_all(u16 did, u32 pasid, struct qi_desc *= desc) +{ + desc->qw0 =3D QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | + QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE; + desc->qw1 =3D 0; +} + +/* Page-selective-within-PASID IOTLB invalidation */ static inline void qi_desc_piotlb(u16 did, u32 pasid, u64 addr, unsigned long npages, bool ih, struct qi_desc *desc) { - if (npages =3D=3D -1) { - desc->qw0 =3D QI_EIOTLB_PASID(pasid) | - QI_EIOTLB_DID(did) | - QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | - QI_EIOTLB_TYPE; - desc->qw1 =3D 0; - } else { - int mask =3D ilog2(__roundup_pow_of_two(npages)); - unsigned long align =3D (1ULL << (VTD_PAGE_SHIFT + mask)); + int mask =3D ilog2(__roundup_pow_of_two(npages)); + unsigned long align =3D (1ULL << (VTD_PAGE_SHIFT + mask)); =20 - if (WARN_ON_ONCE(!IS_ALIGNED(addr, align))) - addr =3D ALIGN_DOWN(addr, align); + if (WARN_ON_ONCE(!IS_ALIGNED(addr, align))) + addr =3D ALIGN_DOWN(addr, align); =20 - desc->qw0 =3D QI_EIOTLB_PASID(pasid) | - QI_EIOTLB_DID(did) | - QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | - QI_EIOTLB_TYPE; - desc->qw1 =3D QI_EIOTLB_ADDR(addr) | - QI_EIOTLB_IH(ih) | - QI_EIOTLB_AM(mask); - } + desc->qw0 =3D QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | + QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE; + desc->qw1 =3D QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) | + QI_EIOTLB_AM(mask); } =20 static inline void qi_desc_dev_iotlb_pasid(u16 sid, u16 pfsid, u32 pasid, @@ -1163,8 +1161,7 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 di= d, u64 addr, void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, u16 qdep, u64 addr, unsigned mask); =20 -void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 ad= dr, - unsigned long npages, bool ih); +void qi_flush_piotlb_all(struct intel_iommu *iommu, u16 did, u32 pasid); =20 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsi= d, u32 pasid, u16 qdep, u64 addr, diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c index 249ab5886c73..3ae0d21ecb9f 100644 --- a/drivers/iommu/intel/cache.c +++ b/drivers/iommu/intel/cache.c @@ -330,15 +330,17 @@ static void qi_batch_add_dev_iotlb(struct intel_iommu= *iommu, u16 sid, u16 pfsid qi_batch_increment_index(iommu, batch); } =20 +static void qi_batch_add_piotlb_all(struct intel_iommu *iommu, u16 did, + u32 pasid, struct qi_batch *batch) +{ + qi_desc_piotlb_all(did, pasid, &batch->descs[batch->index]); + qi_batch_increment_index(iommu, batch); +} + static void qi_batch_add_piotlb(struct intel_iommu *iommu, u16 did, u32 pa= sid, u64 addr, unsigned long npages, bool ih, struct qi_batch *batch) { - /* - * npages =3D=3D -1 means a PASID-selective invalidation, otherwise, - * a positive value for Page-selective-within-PASID invalidation. - * 0 is not a valid input. - */ if (!npages) return; =20 @@ -378,8 +380,12 @@ static void cache_tag_flush_iotlb(struct dmar_domain *= domain, struct cache_tag * u64 type =3D DMA_TLB_PSI_FLUSH; =20 if (intel_domain_use_piotlb(domain)) { - qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid, addr, - pages, ih, domain->qi_batch); + if (pages =3D=3D -1) + qi_batch_add_piotlb_all(iommu, tag->domain_id, + tag->pasid, domain->qi_batch); + else + qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid, + addr, pages, ih, domain->qi_batch); return; } =20 diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index cd04c3f56eec..d33c119a935e 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1550,23 +1550,12 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, = u16 sid, u16 pfsid, qi_submit_sync(iommu, &desc, 1, 0); } =20 -/* PASID-based IOTLB invalidation */ -void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 ad= dr, - unsigned long npages, bool ih) +/* PASID-selective IOTLB invalidation */ +void qi_flush_piotlb_all(struct intel_iommu *iommu, u16 did, u32 pasid) { - struct qi_desc desc =3D {.qw2 =3D 0, .qw3 =3D 0}; + struct qi_desc desc =3D {}; =20 - /* - * npages =3D=3D -1 means a PASID-selective invalidation, otherwise, - * a positive value for Page-selective-within-PASID invalidation. - * 0 is not a valid input. - */ - if (WARN_ON(!npages)) { - pr_err("Invalid input npages =3D %ld\n", npages); - return; - } - - qi_desc_piotlb(did, pasid, addr, npages, ih, &desc); + qi_desc_piotlb_all(did, pasid, &desc); qi_submit_sync(iommu, &desc, 1, 0); } =20 diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 9d30015b8940..89541b74ab8c 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -282,7 +282,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *io= mmu, struct device *dev, pasid_cache_invalidation_with_pasid(iommu, did, pasid); =20 if (pgtt =3D=3D PASID_ENTRY_PGTT_PT || pgtt =3D=3D PASID_ENTRY_PGTT_FL_ON= LY) - qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); + qi_flush_piotlb_all(iommu, did, pasid); else iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); =20 @@ -308,7 +308,7 @@ static void pasid_flush_caches(struct intel_iommu *iomm= u, =20 if (cap_caching_mode(iommu->cap)) { pasid_cache_invalidation_with_pasid(iommu, did, pasid); - qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); + qi_flush_piotlb_all(iommu, did, pasid); } else { iommu_flush_write_buffer(iommu); } @@ -342,7 +342,7 @@ static void intel_pasid_flush_present(struct intel_iomm= u *iommu, * Addr[63:12]=3D0x7FFFFFFF_FFFFF) to affected functions */ pasid_cache_invalidation_with_pasid(iommu, did, pasid); - qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); + qi_flush_piotlb_all(iommu, did, pasid); =20 devtlb_invalidation_with_pasid(iommu, dev, pasid); } diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c index 1460b57db129..586055e51bb2 100644 --- a/drivers/iommu/intel/prq.c +++ b/drivers/iommu/intel/prq.c @@ -113,7 +113,7 @@ void intel_iommu_drain_pasid_prq(struct device *dev, u3= 2 pasid) qi_desc_dev_iotlb(sid, info->pfsid, info->ats_qdep, 0, MAX_AGAW_PFN_WIDTH, &desc[2]); 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d="scan'208";a="231847893" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:27 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 08/10] iommu/vt-d: Pass size_order to qi_desc_piotlb() not npages Date: Thu, 2 Apr 2026 14:57:31 +0800 Message-ID: <20260402065734.1687476-9-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe It doesn't make sense for the caller to compute mask, throw it away and then have qi_desc_piotlb() compute it again. Signed-off-by: Jason Gunthorpe Link: https://lore.kernel.org/r/2-v1-f175e27af136+11647-iommupt_inv_vtd_jgg= @nvidia.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.h | 13 +++++-------- drivers/iommu/intel/cache.c | 10 ++++------ 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 9b193bbcfd58..ef145560aa98 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -1087,19 +1087,16 @@ static inline void qi_desc_piotlb_all(u16 did, u32 = pasid, struct qi_desc *desc) =20 /* Page-selective-within-PASID IOTLB invalidation */ static inline void qi_desc_piotlb(u16 did, u32 pasid, u64 addr, - unsigned long npages, bool ih, + unsigned int size_order, bool ih, struct qi_desc *desc) { - int mask =3D ilog2(__roundup_pow_of_two(npages)); - unsigned long align =3D (1ULL << (VTD_PAGE_SHIFT + mask)); - - if (WARN_ON_ONCE(!IS_ALIGNED(addr, align))) - addr =3D ALIGN_DOWN(addr, align); - + /* + * calculate_psi_aligned_address() must be used for addr and size_order + */ desc->qw0 =3D QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE; desc->qw1 =3D QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) | - QI_EIOTLB_AM(mask); + QI_EIOTLB_AM(size_order); } =20 static inline void qi_desc_dev_iotlb_pasid(u16 sid, u16 pfsid, u32 pasid, diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c index 3ae0d21ecb9f..20df2c16475b 100644 --- a/drivers/iommu/intel/cache.c +++ b/drivers/iommu/intel/cache.c @@ -338,13 +338,11 @@ static void qi_batch_add_piotlb_all(struct intel_iomm= u *iommu, u16 did, } =20 static void qi_batch_add_piotlb(struct intel_iommu *iommu, u16 did, u32 pa= sid, - u64 addr, unsigned long npages, bool ih, + u64 addr, unsigned int size_order, bool ih, struct qi_batch *batch) { - if (!npages) - return; - - qi_desc_piotlb(did, pasid, addr, npages, ih, &batch->descs[batch->index]); + qi_desc_piotlb(did, pasid, addr, size_order, ih, + &batch->descs[batch->index]); qi_batch_increment_index(iommu, batch); } =20 @@ -385,7 +383,7 @@ static void cache_tag_flush_iotlb(struct dmar_domain *d= omain, struct cache_tag * tag->pasid, domain->qi_batch); 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02 Apr 2026 00:00:29 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 09/10] iommu/vt-d: Remove the remaining pages along the invalidation path Date: Thu, 2 Apr 2026 14:57:32 +0800 Message-ID: <20260402065734.1687476-10-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe This was only being used to signal that a flush all should be used. Use mask/size_order >=3D 52 to signal this instead. Signed-off-by: Jason Gunthorpe Link: https://lore.kernel.org/r/3-v1-f175e27af136+11647-iommupt_inv_vtd_jgg= @nvidia.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/trace.h | 18 ++++++++---------- drivers/iommu/intel/cache.c | 27 +++++++++++---------------- 2 files changed, 19 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/intel/trace.h b/drivers/iommu/intel/trace.h index 6311ba3f1691..9f0ab43539ea 100644 --- a/drivers/iommu/intel/trace.h +++ b/drivers/iommu/intel/trace.h @@ -132,8 +132,8 @@ DEFINE_EVENT(cache_tag_log, cache_tag_unassign, =20 DECLARE_EVENT_CLASS(cache_tag_flush, TP_PROTO(struct cache_tag *tag, unsigned long start, unsigned long end, - unsigned long addr, unsigned long pages, unsigned long mask), - TP_ARGS(tag, start, end, addr, pages, mask), + unsigned long addr, unsigned long mask), + TP_ARGS(tag, start, end, addr, mask), TP_STRUCT__entry( __string(iommu, tag->iommu->name) __string(dev, dev_name(tag->dev)) @@ -143,7 +143,6 @@ DECLARE_EVENT_CLASS(cache_tag_flush, __field(unsigned long, start) __field(unsigned long, end) __field(unsigned long, addr) - __field(unsigned long, pages) __field(unsigned long, mask) ), TP_fast_assign( @@ -155,10 +154,9 @@ DECLARE_EVENT_CLASS(cache_tag_flush, __entry->start =3D start; __entry->end =3D end; __entry->addr =3D addr; - __entry->pages =3D pages; __entry->mask =3D mask; ), - TP_printk("%s %s[%d] type %s did %d [0x%lx-0x%lx] addr 0x%lx pages 0x%lx = mask 0x%lx", + TP_printk("%s %s[%d] type %s did %d [0x%lx-0x%lx] addr 0x%lx mask 0x%lx", __get_str(iommu), __get_str(dev), __entry->pasid, __print_symbolic(__entry->type, { CACHE_TAG_IOTLB, "iotlb" }, @@ -166,20 +164,20 @@ DECLARE_EVENT_CLASS(cache_tag_flush, { CACHE_TAG_NESTING_IOTLB, "nesting_iotlb" }, { CACHE_TAG_NESTING_DEVTLB, "nesting_devtlb" }), __entry->domain_id, __entry->start, __entry->end, - __entry->addr, __entry->pages, __entry->mask + __entry->addr, __entry->mask ) ); =20 DEFINE_EVENT(cache_tag_flush, cache_tag_flush_range, TP_PROTO(struct cache_tag *tag, unsigned long start, unsigned long end, - unsigned long addr, unsigned long pages, unsigned long mask), - TP_ARGS(tag, start, end, addr, pages, mask) + unsigned long addr, unsigned long mask), + TP_ARGS(tag, start, end, addr, mask) ); =20 DEFINE_EVENT(cache_tag_flush, cache_tag_flush_range_np, TP_PROTO(struct cache_tag *tag, unsigned long start, unsigned long end, - unsigned long addr, unsigned long pages, unsigned long mask), - TP_ARGS(tag, start, end, addr, pages, mask) + unsigned long addr, unsigned long mask), + TP_ARGS(tag, start, end, addr, mask) ); #endif /* _TRACE_INTEL_IOMMU_H */ =20 diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c index 20df2c16475b..be8410f0e841 100644 --- a/drivers/iommu/intel/cache.c +++ b/drivers/iommu/intel/cache.c @@ -255,7 +255,6 @@ void cache_tag_unassign_domain(struct dmar_domain *doma= in, =20 static unsigned long calculate_psi_aligned_address(unsigned long start, unsigned long end, - unsigned long *_pages, unsigned long *_mask) { unsigned long pages =3D aligned_nrpages(start, end - start + 1); @@ -281,10 +280,8 @@ static unsigned long calculate_psi_aligned_address(uns= igned long start, */ shared_bits =3D ~(pfn ^ end_pfn) & ~bitmask; mask =3D shared_bits ? __ffs(shared_bits) : MAX_AGAW_PFN_WIDTH; - aligned_pages =3D 1UL << mask; } =20 - *_pages =3D aligned_pages; *_mask =3D mask; =20 return ALIGN_DOWN(start, VTD_PAGE_SIZE << mask); @@ -371,14 +368,13 @@ static bool intel_domain_use_piotlb(struct dmar_domai= n *domain) } =20 static void cache_tag_flush_iotlb(struct dmar_domain *domain, struct cache= _tag *tag, - unsigned long addr, unsigned long pages, - unsigned long mask, int ih) + unsigned long addr, unsigned long mask, int ih) { struct intel_iommu *iommu =3D tag->iommu; u64 type =3D DMA_TLB_PSI_FLUSH; =20 if (intel_domain_use_piotlb(domain)) { - if (pages =3D=3D -1) + if (mask >=3D MAX_AGAW_PFN_WIDTH) qi_batch_add_piotlb_all(iommu, tag->domain_id, tag->pasid, domain->qi_batch); else @@ -392,7 +388,7 @@ static void cache_tag_flush_iotlb(struct dmar_domain *d= omain, struct cache_tag * * is too big. */ if (!cap_pgsel_inv(iommu->cap) || - mask > cap_max_amask_val(iommu->cap) || pages =3D=3D -1) { + mask > cap_max_amask_val(iommu->cap)) { addr =3D 0; mask =3D 0; ih =3D 0; @@ -441,16 +437,15 @@ void cache_tag_flush_range(struct dmar_domain *domain= , unsigned long start, unsigned long end, int ih) { struct intel_iommu *iommu =3D NULL; - unsigned long pages, mask, addr; + unsigned long mask, addr; struct cache_tag *tag; unsigned long flags; =20 if (start =3D=3D 0 && end =3D=3D ULONG_MAX) { addr =3D 0; - pages =3D -1; mask =3D MAX_AGAW_PFN_WIDTH; } else { - addr =3D calculate_psi_aligned_address(start, end, &pages, &mask); + addr =3D calculate_psi_aligned_address(start, end, &mask); } =20 spin_lock_irqsave(&domain->cache_lock, flags); @@ -462,7 +457,7 @@ void cache_tag_flush_range(struct dmar_domain *domain, = unsigned long start, switch (tag->type) { case CACHE_TAG_IOTLB: case CACHE_TAG_NESTING_IOTLB: - cache_tag_flush_iotlb(domain, tag, addr, pages, mask, ih); + cache_tag_flush_iotlb(domain, tag, addr, mask, ih); break; case CACHE_TAG_NESTING_DEVTLB: /* @@ -480,7 +475,7 @@ void cache_tag_flush_range(struct dmar_domain *domain, = unsigned long start, break; } =20 - trace_cache_tag_flush_range(tag, start, end, addr, pages, mask); + trace_cache_tag_flush_range(tag, start, end, addr, mask); } qi_batch_flush_descs(iommu, domain->qi_batch); spin_unlock_irqrestore(&domain->cache_lock, flags); @@ -510,11 +505,11 @@ void cache_tag_flush_range_np(struct dmar_domain *dom= ain, unsigned long start, unsigned long end) { struct intel_iommu *iommu =3D NULL; - unsigned long pages, mask, addr; + unsigned long mask, addr; struct cache_tag *tag; unsigned long flags; =20 - addr =3D calculate_psi_aligned_address(start, end, &pages, &mask); + addr =3D calculate_psi_aligned_address(start, end, &mask); =20 spin_lock_irqsave(&domain->cache_lock, flags); list_for_each_entry(tag, &domain->cache_tags, node) { @@ -530,9 +525,9 @@ void cache_tag_flush_range_np(struct dmar_domain *domai= n, unsigned long start, =20 if (tag->type =3D=3D CACHE_TAG_IOTLB || tag->type =3D=3D CACHE_TAG_NESTING_IOTLB) - cache_tag_flush_iotlb(domain, tag, addr, pages, mask, 0); + cache_tag_flush_iotlb(domain, tag, addr, mask, 0); =20 - trace_cache_tag_flush_range_np(tag, start, end, addr, pages, mask); + trace_cache_tag_flush_range_np(tag, start, end, addr, mask); } qi_batch_flush_descs(iommu, domain->qi_batch); spin_unlock_irqrestore(&domain->cache_lock, flags); --=20 2.43.0 From nobody Sun Jun 14 09:53:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A5433845CE for ; Thu, 2 Apr 2026 07:00:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="76053672" X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="76053672" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2026 00:00:31 -0700 X-CSE-ConnectionGUID: eGiuhs1kQiaoaJrfZnII9Q== X-CSE-MsgGUID: TeFpf/a1TwadyTa3RcF5hQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,155,1770624000"; d="scan'208";a="231847921" Received: from allen-box.sh.intel.com ([10.239.159.52]) by orviesa005.jf.intel.com with ESMTP; 02 Apr 2026 00:00:30 -0700 From: Lu Baolu To: Joerg Roedel Cc: Zhenzhong Duan , Bjorn Helgaas , Jason Gunthorpe , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 10/10] iommu/vt-d: Simplify calculate_psi_aligned_address() Date: Thu, 2 Apr 2026 14:57:33 +0800 Message-ID: <20260402065734.1687476-11-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com> References: <20260402065734.1687476-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe This is doing far too much math for the simple task of finding a power of 2 that fully spans the given range. Use fls directly on the xor which computes the common binary prefix. Signed-off-by: Jason Gunthorpe Link: https://lore.kernel.org/r/4-v1-f175e27af136+11647-iommupt_inv_vtd_jgg= @nvidia.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/cache.c | 49 ++++++++++++------------------------- 1 file changed, 16 insertions(+), 33 deletions(-) diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c index be8410f0e841..54dd9f7323bd 100644 --- a/drivers/iommu/intel/cache.c +++ b/drivers/iommu/intel/cache.c @@ -254,37 +254,25 @@ void cache_tag_unassign_domain(struct dmar_domain *do= main, } =20 static unsigned long calculate_psi_aligned_address(unsigned long start, - unsigned long end, - unsigned long *_mask) + unsigned long last, + unsigned long *size_order) { - unsigned long pages =3D aligned_nrpages(start, end - start + 1); - unsigned long aligned_pages =3D __roundup_pow_of_two(pages); - unsigned long bitmask =3D aligned_pages - 1; - unsigned long mask =3D ilog2(aligned_pages); - unsigned long pfn =3D IOVA_PFN(start); + unsigned int sz_lg2; =20 - /* - * PSI masks the low order bits of the base address. If the - * address isn't aligned to the mask, then compute a mask value - * needed to ensure the target range is flushed. - */ - if (unlikely(bitmask & pfn)) { - unsigned long end_pfn =3D pfn + pages - 1, shared_bits; - - /* - * Since end_pfn <=3D pfn + bitmask, the only way bits - * higher than bitmask can differ in pfn and end_pfn is - * by carrying. This means after masking out bitmask, - * high bits starting with the first set bit in - * shared_bits are all equal in both pfn and end_pfn. - */ - shared_bits =3D ~(pfn ^ end_pfn) & ~bitmask; - mask =3D shared_bits ? __ffs(shared_bits) : MAX_AGAW_PFN_WIDTH; + /* Compute a sz_lg2 that spans start and last */ + start &=3D GENMASK(BITS_PER_LONG - 1, VTD_PAGE_SHIFT); + sz_lg2 =3D fls_long(start ^ last); + if (sz_lg2 <=3D 12) { + *size_order =3D 0; + return start; + } + if (unlikely(sz_lg2 >=3D MAX_AGAW_PFN_WIDTH)) { + *size_order =3D MAX_AGAW_PFN_WIDTH; + return 0; } =20 - *_mask =3D mask; - - return ALIGN_DOWN(start, VTD_PAGE_SIZE << mask); + *size_order =3D sz_lg2 - VTD_PAGE_SHIFT; + return start & GENMASK(BITS_PER_LONG - 1, sz_lg2); } =20 static void qi_batch_flush_descs(struct intel_iommu *iommu, struct qi_batc= h *batch) @@ -441,12 +429,7 @@ void cache_tag_flush_range(struct dmar_domain *domain,= unsigned long start, struct cache_tag *tag; unsigned long flags; =20 - if (start =3D=3D 0 && end =3D=3D ULONG_MAX) { - addr =3D 0; - mask =3D MAX_AGAW_PFN_WIDTH; - } else { - addr =3D calculate_psi_aligned_address(start, end, &mask); - } + addr =3D calculate_psi_aligned_address(start, end, &mask); =20 spin_lock_irqsave(&domain->cache_lock, flags); list_for_each_entry(tag, &domain->cache_tags, node) { --=20 2.43.0