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R. Silva" , linux-samsung-soc@vger.kernel.org (open list:SAMSUNG SOC CLOCK DRIVERS), linux-kernel@vger.kernel.org (open list), linux-hardening@vger.kernel.org (open list:KERNEL HARDENING (not covered by other areas):Keyword:\b__counted_by(_le|_be)?\b) Subject: [PATCH 1/3] clk: samsung: use kzalloc_flex Date: Wed, 1 Apr 2026 20:04:30 -0700 Message-ID: <20260402030432.101066-2-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260402030432.101066-1-rosenp@gmail.com> References: <20260402030432.101066-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify allocation by using kzalloc_flex with a flexible array member to combine allocations. Add __counted_by for extra runtime analysis. Move the counting variable assignment right after allocation as required ny __counted_by. Signed-off-by: Rosen Penev --- drivers/clk/samsung/clk.c | 28 ++++++---------------------- drivers/clk/samsung/clk.h | 2 +- 2 files changed, 7 insertions(+), 23 deletions(-) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 91e5cdbc79d7..12028f13e8e8 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -48,23 +48,6 @@ void samsung_clk_restore(void __iomem *base, } } =20 -struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( - const unsigned long *rdump, - unsigned long nr_rdump) -{ - struct samsung_clk_reg_dump *rd; - unsigned int i; - - rd =3D kzalloc_objs(*rd, nr_rdump); - if (!rd) - return NULL; - - for (i =3D 0; i < nr_rdump; ++i) - rd[i].offset =3D rdump[i]; - - return rd; -} - /** * samsung_clk_init() - Create and initialize a clock provider object * @dev: CMU device to enable runtime PM, or NULL if RPM is not needed @@ -430,21 +413,22 @@ void samsung_clk_extended_sleep_init(void __iomem *re= g_base, unsigned long nr_rsuspend) { struct samsung_clock_reg_cache *reg_cache; + int i; =20 - reg_cache =3D kzalloc_obj(struct samsung_clock_reg_cache); + reg_cache =3D kzalloc_flex(*reg_cache, rdump, nr_rdump); if (!reg_cache) panic("could not allocate register reg_cache.\n"); - reg_cache->rdump =3D samsung_clk_alloc_reg_dump(rdump, nr_rdump); =20 - if (!reg_cache->rdump) - panic("could not allocate register dump storage.\n"); + reg_cache->rd_num =3D nr_rdump; + + for (i =3D 0; i < nr_rdump; ++i) + reg_cache->rdump[i].offset =3D rdump[i]; =20 if (list_empty(&clock_reg_cache_list)) register_syscore(&samsung_clk_syscore); =20 reg_cache->reg_base =3D reg_base; reg_cache->sysreg =3D sysreg; - reg_cache->rd_num =3D nr_rdump; reg_cache->rsuspend =3D rsuspend; reg_cache->rsuspend_num =3D nr_rsuspend; list_add_tail(®_cache->node, &clock_reg_cache_list); diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index b1192ca03db5..098f27a6290d 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -324,10 +324,10 @@ struct samsung_clock_reg_cache { struct list_head node; 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Wed, 01 Apr 2026 20:04:52 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35dbe9379f3sm6395873a91.9.2026.04.01.20.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 20:04:52 -0700 (PDT) From: Rosen Penev To: linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Kees Cook , "Gustavo A. R. Silva" , linux-samsung-soc@vger.kernel.org (open list:SAMSUNG SOC CLOCK DRIVERS), linux-kernel@vger.kernel.org (open list), linux-hardening@vger.kernel.org (open list:KERNEL HARDENING (not covered by other areas):Keyword:\b__counted_by(_le|_be)?\b) Subject: [PATCH 2/3] clk: samsung: cpu: use kzalloc_flex Date: Wed, 1 Apr 2026 20:04:31 -0700 Message-ID: <20260402030432.101066-3-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260402030432.101066-1-rosenp@gmail.com> References: <20260402030432.101066-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use a flexible array member to combine allocations. As kmemdup_array is really kcalloc + memcpy and kzalloc_flex kzalloc + kcalloc, kzalloc and kcalloc combine leaving the memcpy. Signed-off-by: Rosen Penev --- drivers/clk/samsung/clk-cpu.c | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index ffc33e5decf5..ad08d6288baa 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -101,11 +101,11 @@ struct exynos_cpuclk { const struct clk_hw *alt_parent; void __iomem *base; spinlock_t *lock; - const struct exynos_cpuclk_cfg_data *cfg; const unsigned long num_cfgs; struct notifier_block clk_nb; unsigned long flags; const struct exynos_cpuclk_chip *chip; + struct exynos_cpuclk_cfg_data cfg[]; }; =20 /* ---- Common code ------------------------------------------------------= --- */ @@ -660,10 +660,6 @@ static int __init exynos_register_cpu_clock(struct sam= sung_clk_provider *ctx, return -EINVAL; } =20 - cpuclk =3D kzalloc_obj(*cpuclk); - if (!cpuclk) - return -ENOMEM; - parent_name =3D clk_hw_get_name(parent); =20 init.name =3D clk_data->name; @@ -672,6 +668,15 @@ static int __init exynos_register_cpu_clock(struct sam= sung_clk_provider *ctx, init.num_parents =3D 1; init.ops =3D &exynos_cpuclk_clk_ops; =20 + /* Find count of configuration rates in cfg */ + for (num_cfgs =3D 0; clk_data->cfg[num_cfgs].prate !=3D 0; ) + num_cfgs++; + + cpuclk =3D kzalloc_flex(*cpuclk, cfg, num_cfgs); + if (!cpuclk) + return -ENOMEM; + + memcpy(cpuclk->cfg, clk_data->cfg, num_cfgs * sizeof(*cpuclk->cfg)); cpuclk->alt_parent =3D alt_parent; cpuclk->hw.init =3D &init; cpuclk->base =3D ctx->reg_base + clk_data->offset; @@ -687,29 +692,16 @@ static int __init exynos_register_cpu_clock(struct sa= msung_clk_provider *ctx, goto free_cpuclk; } =20 - /* Find count of configuration rates in cfg */ - for (num_cfgs =3D 0; clk_data->cfg[num_cfgs].prate !=3D 0; ) - num_cfgs++; - - cpuclk->cfg =3D kmemdup_array(clk_data->cfg, num_cfgs, sizeof(*cpuclk->cf= g), - GFP_KERNEL); - if (!cpuclk->cfg) { - ret =3D -ENOMEM; - goto unregister_clk_nb; - } - ret =3D clk_hw_register(NULL, &cpuclk->hw); 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Wed, 01 Apr 2026 20:04:54 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35dbe9379f3sm6395873a91.9.2026.04.01.20.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 20:04:53 -0700 (PDT) From: Rosen Penev To: linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Kees Cook , "Gustavo A. R. Silva" , linux-samsung-soc@vger.kernel.org (open list:SAMSUNG SOC CLOCK DRIVERS), linux-kernel@vger.kernel.org (open list), linux-hardening@vger.kernel.org (open list:KERNEL HARDENING (not covered by other areas):Keyword:\b__counted_by(_le|_be)?\b) Subject: [PATCH 3/3] clk: samsung: pll: use kzalloc_flex Date: Wed, 1 Apr 2026 20:04:32 -0700 Message-ID: <20260402030432.101066-4-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260402030432.101066-1-rosenp@gmail.com> References: <20260402030432.101066-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify allocation by using a flexible array member to combine allocations and remove a kfree. Use __counted_by for extra runtime analysis. Assign after allocation as required by __counted_by. Since rate_table is now a flexible array member, NULL checks don't work. So use the counting variable to check allocation. Signed-off-by: Rosen Penev --- drivers/clk/samsung/clk-pll.c | 56 ++++++++++++++++------------------- 1 file changed, 26 insertions(+), 30 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index fdb84bcec912..e74552846ba3 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -28,7 +28,7 @@ struct samsung_clk_pll { unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; - const struct samsung_pll_rate_table *rate_table; + struct samsung_pll_rate_table rate_table[] __counted_by(rate_count); }; =20 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) @@ -1593,35 +1593,32 @@ static void __init _samsung_clk_register_pll(struct= samsung_clk_provider *ctx, { struct samsung_clk_pll *pll; struct clk_init_data init; - int ret, len; + unsigned int len =3D 0; + int ret; =20 - pll =3D kzalloc_obj(*pll); + if (pll_clk->rate_table) { + /* find count of rates in rate_table */ + while (pll_clk->rate_table[len].rate !=3D 0) + len++; + } + + pll =3D kzalloc_flex(*pll, rate_table, len); if (!pll) { pr_err("%s: could not allocate pll clk %s\n", __func__, pll_clk->name); return; } =20 + pll->rate_count =3D len; + if (len) + memcpy(pll->rate_table, pll_clk->rate_table, + len * sizeof(*pll->rate_table)); + init.name =3D pll_clk->name; init.flags =3D pll_clk->flags; init.parent_names =3D &pll_clk->parent_name; init.num_parents =3D 1; =20 - if (pll_clk->rate_table) { - /* find count of rates in rate_table */ - for (len =3D 0; pll_clk->rate_table[len].rate !=3D 0; ) - len++; - - pll->rate_count =3D len; - pll->rate_table =3D kmemdup_array(pll_clk->rate_table, - pll->rate_count, - sizeof(*pll->rate_table), - GFP_KERNEL); - WARN(!pll->rate_table, - "%s: could not allocate rate table for %s\n", - __func__, pll_clk->name); - } - switch (pll_clk->type) { case pll_2126: init.ops =3D &samsung_pll2126_clk_ops; @@ -1640,7 +1637,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_a9fracm: pll->enable_offs =3D PLL35XX_ENABLE_SHIFT; pll->lock_offs =3D PLL35XX_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll35xx_clk_min_ops; else init.ops =3D &samsung_pll35xx_clk_ops; @@ -1659,7 +1656,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_0732x: pll->enable_offs =3D PLL0822X_ENABLE_SHIFT; pll->lock_offs =3D PLL0822X_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll0822x_clk_min_ops; else init.ops =3D &samsung_pll0822x_clk_ops; @@ -1669,7 +1666,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, break; case pll_4502: case pll_4508: - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll45xx_clk_min_ops; else init.ops =3D &samsung_pll45xx_clk_ops; @@ -1679,7 +1676,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_2650: pll->enable_offs =3D PLL36XX_ENABLE_SHIFT; pll->lock_offs =3D PLL36XX_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll36xx_clk_min_ops; else init.ops =3D &samsung_pll36xx_clk_ops; @@ -1687,7 +1684,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_0831x: pll->enable_offs =3D PLL0831X_ENABLE_SHIFT; pll->lock_offs =3D PLL0831X_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll0831x_clk_min_ops; else init.ops =3D &samsung_pll0831x_clk_ops; @@ -1703,7 +1700,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_4650: case pll_4650c: case pll_1460x: - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll46xx_clk_min_ops; else init.ops =3D &samsung_pll46xx_clk_ops; @@ -1712,19 +1709,19 @@ static void __init _samsung_clk_register_pll(struct= samsung_clk_provider *ctx, init.ops =3D &samsung_pll2550x_clk_ops; break; case pll_2550xx: - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll2550xx_clk_min_ops; else init.ops =3D &samsung_pll2550xx_clk_ops; break; case pll_2650x: - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll2650x_clk_min_ops; else init.ops =3D &samsung_pll2650x_clk_ops; break; case pll_2650xx: - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll2650xx_clk_min_ops; else init.ops =3D &samsung_pll2650xx_clk_ops; @@ -1734,7 +1731,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, init.ops =3D &samsung_pll531x_clk_ops; break; case pll_1031x: - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_pll1031x_clk_min_ops; else init.ops =3D &samsung_pll1031x_clk_ops; @@ -1742,7 +1739,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_a9fraco: pll->enable_offs =3D PLLA9FRACO_ENABLE_SHIFT; pll->lock_offs =3D PLLA9FRACO_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops =3D &samsung_a9fraco_clk_min_ops; else init.ops =3D &samsung_a9fraco_clk_ops; @@ -1761,7 +1758,6 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, if (ret) { pr_err("%s: failed to register pll clock %s : %d\n", __func__, pll_clk->name, ret); - kfree(pll->rate_table); kfree(pll); return; } --=20 2.53.0