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[81.108.45.148]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4888a65635fsm31433565e9.6.2026.04.01.17.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 17:31:10 -0700 (PDT) From: Prathamesh Deshpande To: prathameshdeshpande7@gmail.com Cc: leon@kernel.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org, mbloch@nvidia.com, netdev@vger.kernel.org, richardcochran@gmail.com, saeedm@nvidia.com, tariqt@nvidia.com Subject: [PATCH v2] net/mlx5: Fix OOB access and stack information leak in PTP event handling Date: Thu, 2 Apr 2026 01:30:47 +0100 Message-ID: <20260402003047.24684-1-prathameshdeshpande7@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331153152.16766-1-prathameshdeshpande7@gmail.com> References: <20260331153152.16766-1-prathameshdeshpande7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In mlx5_pps_event(), several critical issues were identified during review by Sashiko: 1. The 'pin' index from the hardware event was used without bounds checking to index 'pin_config' and 'pps_info->start', leading to potential out-of-bounds memory access. 2. 'ptp_event' was not zero-initialized. Since it contains a union, assigning a timestamp partially leaves the 'ts_raw' field with uninitialized stack memory, which can leak kernel data or corrupt time sync logic in hardpps(). 3. A NULL 'pin_config' could be dereferenced if initialization failed. 4. 'clock->ptp' could be NULL if ptp_clock_register() failed. Fix these by zero-initializing the event struct, adding a bounds check against MAX_PIN_NUM, and adding appropriate NULL guards. Fixes: 7c39afb394c7 ("net/mlx5: PTP code migration to driver core section") Signed-off-by: Prathamesh Deshpande --- v2: - Zero-initialize ptp_event to prevent stack information leak [Sashiko]. - Add bounds check for hardware pin index to prevent OOB access [Sashiko]. - Add NULL guard for pin_config to handle initialization failures [Sashiko]. - Add NULL check for clock->ptp as originally intended. drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/= net/ethernet/mellanox/mlx5/core/lib/clock.c index bd4e042077af..a4d8c5c39abc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -1164,12 +1164,18 @@ static int mlx5_pps_event(struct notifier_block *nb, pps_nb); struct mlx5_core_dev *mdev =3D clock_state->mdev; struct mlx5_clock *clock =3D mdev->clock; - struct ptp_clock_event ptp_event; + struct ptp_clock_event ptp_event =3D {}; struct mlx5_eqe *eqe =3D data; int pin =3D eqe->data.pps.pin; unsigned long flags; u64 ns; =20 + if (!clock->ptp_info.pin_config) + return NOTIFY_OK; + + if (pin < 0 || pin >=3D MAX_PIN_NUM) + return NOTIFY_OK; + switch (clock->ptp_info.pin_config[pin].func) { case PTP_PF_EXTTS: ptp_event.index =3D pin; @@ -1185,8 +1191,8 @@ static int mlx5_pps_event(struct notifier_block *nb, } else { ptp_event.type =3D PTP_CLOCK_EXTTS; } - /* TODOL clock->ptp can be NULL if ptp_clock_register fails */ - ptp_clock_event(clock->ptp, &ptp_event); + if (clock->ptp) + ptp_clock_event(clock->ptp, &ptp_event); break; case PTP_PF_PEROUT: if (clock->shared) { --=20 2.43.0