From nobody Sun Jun 14 11:27:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4008336607D; Thu, 2 Apr 2026 14:27:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775140078; cv=none; b=cmHS8w9gdAUbOKP9+ZKnWhV2zPHtpWKMplYzK0PMQChgPd8qsjJo2/ZNgqz3GtbB4RDbpfJq4hxaeN6uo1R1d0iRkE2iQYXKLS18s07m+2KlxDaxfGZh9ccwniBilcXbFmB6Go5yHgfbMImitHwainzz0BVIu0/rJafVXVzBeUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775140078; c=relaxed/simple; bh=NAByKfU/ZjEewVQnAkmCy1V2fy4PZYtDqNWOg10g8F4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MTyzwIwbyJqx3IBqVZ/eGENR2q3GmQ6MKirba2LFd8/iMZp3NjqemLST2LEg2OI04UcrPRBDTVwJUYFqTdgxP/YBd5DnCZT8WYVt3q3Ou9YYqoLStHGhrcsXsU9mlM3PoVFJx93jxlJGphFbf0lw0jWNlIBqYkrzsphSW9oIDkY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Np8hZNYt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Np8hZNYt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46B4EC2BCB3; Thu, 2 Apr 2026 14:27:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775140077; bh=NAByKfU/ZjEewVQnAkmCy1V2fy4PZYtDqNWOg10g8F4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Np8hZNYtGt5gbuN6MvaRAeCqJ3F1oqjeR011UgZKWdilMm1NWwEoLJsrop9vEKEKJ CayjbD65CgAq6kxmTN8/ZMRp6UbYRXHlvyQOrz43iT1i9DhBkbE6llfzKbHqVGbHqF dsl60/acNLsak+orkqezhAvI3XmmvonG/75gxEvZG1O2auyx6FUxOJM7Vty8iOE2kI +21b6K4dPmLpZGAKuwA2BVZ0XHXDUr6qAf6eXd18c8zJtGEZocRpqAI+pDz1Wpvh4w Ank1UlBk7SRIQT8kGQQsNqqE0Z42e2gjIlq4NqcgLJQkmzABy5cDqtHaNKQxYaML1Q 7ur41gY0vsfyQ== From: Thierry Reding Date: Thu, 02 Apr 2026 16:27:35 +0200 Subject: [PATCH v4 1/4] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260402-tegra264-pcie-v4-1-21e2e19987e8@nvidia.com> References: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> In-Reply-To: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6863; i=treding@nvidia.com; h=from:subject:message-id; bh=OWl+kwHniIJmn2xT8tkW6mFB/fgovQVw1CKdkoUXhPs=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBpznznvY0VyUIk/fnSv3MCEw9J6m6PLKgotKsZu ORvzT4pPzeJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCac585wAKCRDdI6zXfz6z oTzCD/0V1hNnSNbAiKMSLVeNsPoLZy4RnVdQ7bR1WzYlNd042sabyfuzOnLelO99DMyrlbVoNge YdmBgNaAuoBJCQcTUxkKLp7IIiNNQlBAxxUNCnnfutVal7IKePDgcf2ZiclzO7Urlyi7tuL+GEB jBf6gAP8758J9KRcy7IUTSIsbeicTMhafg5Rvg5YaIISl6oAzNj99creo068Ke43pd+hc5ArT8Z GZGpql1IiB5exxe2Y5dsjMKF7kE+ZRiqiNDwFwTc+CenCx/yXUtw6WNvTgXDHF6qbvTzKHAk7G4 tgYDg7JH7+Tvp8Ii2y5A7hc1EKBNvizKuCTtOoX1RcXn2CXBn/+gWIA+N6zB78liX0Vi9GcWvbn 9J0NtyC7yyyKnR2pJTdRI2eRBSJAazoGEZv5MtFp8D5s2G56CeUKHw6Nqp9C8W5ntGu5TTM1Sqe nhbvFbFHE8cLwJ5AFyVlGv874nEYCpsZbdNwCLfJd4wRUJzDYxbFrlGq8kBRHaTi4xwHiZDBO5G S5pM1aYKbrKG6V8SsDuVhPWIGSApZHau1ecXEjmiDCp2lcb6wBAikX0XOMVDpwq7Rv4kJmsgLDA k71lZkvIfSmXawWjf72LlCjpsznvyeA/K3ux9QNVqFxvbxm+JxGnlGjJoLhnnb+SsEWB8Q1uo20 tv/SMhE1jXe5wwg== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The six PCIe controllers found on Tegra264 are of two types: one is used for the internal GPU and therefore is not connected to a UPHY and the remaining five controllers are typically routed to a PCI slot and have additional controls for the physical link. While these controllers can be switched into endpoint mode, this binding describes the root complex mode only. Signed-off-by: Thierry Reding --- Changes in v4: - ECAM is outside of the controller's region, so it cannot be the first reg entry, otherwise we get warnings because it doesn't match the unit-address, so revert back to oneOf construct Changes in v2: - move ECAM region first and unify C0 vs. C1-C5 - move unevaluatedProperties to right before the examples - add description to clarify the two types of controllers - add examples for C0 and C1-C5 --- .../bindings/pci/nvidia,tegra264-pcie.yaml | 174 +++++++++++++++++= ++++ 1 file changed, 174 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml new file mode 100644 index 000000000000..acb677d477fb --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 PCIe controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + Of the six PCIe controllers found on Tegra264, one (C0) is used for the + internal GPU and the other five (C1-C5) are routed to connectors such as + PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 + through C5, but not for C0. + +properties: + compatible: + const: nvidia,tegra264-pcie + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + maxItems: 5 + + interrupts: + minItems: 1 + maxItems: 4 + + dma-coherent: true + + nvidia,bpmp: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Must contain a pair of phandle (to the BPMP controller node) and + controller ID. The following are the controller IDs for each control= ler: + + 0: C0 + 1: C1 + 2: C2 + 3: C3 + 4: C4 + 5: C5 + items: + - items: + - description: phandle to the BPMP controller node + - description: PCIe controller ID + maximum: 5 + +required: + - interrupt-map + - interrupt-map-mask + - iommu-map + - msi-map + - nvidia,bpmp + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - oneOf: + - description: C0 controller (no UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: ecam + + - description: C1-C5 controllers (with UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: data link/physical layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: xpl + - const: ecam + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pci@c000000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x0c000000 0x0 0x00004000>, + <0x00 0x0c004000 0x0 0x00001000>, + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x00>; + #interrupt-cells =3D <0x1>; + + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>; + + iommu-map =3D <0x0 &smmu2 0x10000 0x10000>; + msi-map =3D <0x0 &its 0x210000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x0020= 0000>, + <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x080000= 00>, + <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc00000= 00>; + bus-range =3D <0x0 0xff>; + + nvidia,bpmp =3D <&bpmp 0>; + }; + }; + + - | + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pci@8400000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x08400000 0x0 0x00004000>, + <0x00 0x08404000 0x0 0x00001000>, + <0x00 0x08405000 0x0 0x00001000>, + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x01>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>; + + iommu-map =3D <0x0 &smmu1 0x10000 0x10000>; + msi-map =3D <0x0 &its 0x110000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x0020= 0000>, + <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x080000= 00>, + <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc00000= 00>; + bus-range =3D <0x00 0xff>; + + nvidia,bpmp =3D <&bpmp 1>; + }; + }; --=20 2.52.0 From nobody Sun Jun 14 11:27:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 786E93EE1EC; Thu, 2 Apr 2026 14:28:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775140081; cv=none; b=cLRJEgeG6FxRHOv86zBCHNY3M8VHwGsxo0x5OFbsGVIrUfnzLsz/vfbVyiPQ5Hfn4EyGGnaHCFfPXA7g6N/cnfQL1ahh2WGEzJHiUQNnAG5fG5TQRShH1o+GdrhgqWDjYjSjVZdH4Pbhyx1HC5dywYwvuGURSqjmY40/1Jd+4f8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775140081; c=relaxed/simple; bh=KAMIzOzCbbIkdN4+h9mLaBbmQnop0xd9spJhdw58o5c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260402-tegra264-pcie-v4-2-21e2e19987e8@nvidia.com> References: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> In-Reply-To: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=7887; i=treding@nvidia.com; h=from:subject:message-id; bh=oVBJHFwB+gdNI7W/8nXEvJ4Aw93e6oLvRNS3XbChGUY=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBpznzo0GCVjwX6st8+h0v682ZUEPkxIqGzROXu5 Nfbq+SWm8GJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCac586AAKCRDdI6zXfz6z oWyWD/9KqFx3AWLsen71eImhEUWi5Vbr2EBrypY2+xZH9iKEKVVlJX6zH8ICwWXLq/9S1CoF7BI gyYELvWzJEiM6ESCDHKhPNtvGAoFCET+VjruIN+kzkv3g9g0n3yijseZDE3XYLW2n+fCQgrc/ue gv7U+JfI6npA9oOfh3rsk9jciSVRay4VjYG+IzF7kvWZFsIhDS1ComrThVZMJVXgYFHJ/EMm/1J uSZ2vSSneNVSp637VzbNkj4uxxHJBj9TZ81Qq3faJk7BNQOrSKbcJfZzbffZYxDYLBesi8fwKny oRsfmO86HYyG18GpqzHW4l3UEU+1EkO3H6Z0BN0j4rX1ZAGhe/RtzbZcoQBhvyla3/5OotxSGWp 1zlZCz//YAA3VgdBTNI3ob5gd+3rQI6tXRCuRiO1zWmr9z/LBsOOJf47m7Fkcbm9vomT59v1azx XRgTCgolqoI1+LSMXlS7/hF8VU4otMyvnROWai7BSFtLOOKgUU7nuF74TwbSCTo9IYbVJkNR3n8 serEUq/fObYix+yblw+nJqup+1zMA1nRuEa6KAU+7VqR//N/0kC8N7jx+0LXv67NjShXyH1UxCz cyxfUhS7mCo/PdAMIw7ttGQOksFOKFNN1cGiYY8IOqqDHc0ljMdVuOC4PY2DYYgAgwXgaFrLxOo drF5PgjYPbDmGyA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Instead of defining the wait values for each driver, use common values defined in the core pci.h header file. Note that most drivers don't use the millisecond waits, but rather usleep_range(), so add these commonly used values to the header so that all drivers can use them. Signed-off-by: Thierry Reding --- Changes in v2: - fix build for Cadence --- drivers/pci/controller/cadence/pcie-cadence-host-common.c | 6 ++++-- drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 ----- drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++-- drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 ----- drivers/pci/controller/pci-aardvark.c | 7 ++----- drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++------- drivers/pci/controller/plda/pcie-starfive.c | 9 ++------- drivers/pci/pci.h | 2 ++ 8 files changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c index 2b0211870f02..72b36c70f389 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -15,6 +15,8 @@ #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" =20 +#include "../../pci.h" + #define LINK_RETRAIN_TIMEOUT HZ =20 u64 bar_max_size[] =3D { @@ -53,12 +55,12 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, int retries; =20 /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (pcie_link_up(pcie)) { dev_info(dev, "Link up\n"); return 0; } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h index 857b2140c5d2..15dc4fcaf45d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -10,11 +10,6 @@ =20 #include =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - /* Local Management Registers */ #define CDNS_PCIE_LM_BASE 0x00100000 =20 diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/= controller/mobiveil/pcie-mobiveil.c index 62ecbaeb0a60..cc102032c1e6 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c @@ -218,11 +218,11 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (mobiveil_pcie_link_up(pcie)) return 0; =20 - usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); + usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX); } =20 dev_err(&pcie->pdev->dev, "link never came up\n"); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index 7246de6a7176..11010a99e27c 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -122,11 +122,6 @@ #define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) #define MAX_PIO_WINDOWS 8 =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_MIN 90000 -#define LINK_WAIT_MAX 100000 - #define PAGED_ADDR_BNDRY 0xc00 #define OFFSET_TO_PAGE_ADDR(off) \ ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller= /pci-aardvark.c index e34bea1ff0ac..506323a6c72b 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -255,9 +255,6 @@ enum { #define PIO_RETRY_CNT 750000 /* 1.5 s */ #define PIO_RETRY_DELAY 2 /* 2 us*/ =20 -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 #define RETRAIN_WAIT_MAX_RETRIES 10 #define RETRAIN_WAIT_USLEEP_US 2000 =20 @@ -349,11 +346,11 @@ static int advk_pcie_wait_for_link(struct advk_pcie *= pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (advk_pcie_link_up(pcie)) return 0; =20 - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/control= ler/pcie-xilinx-nwl.c index 7db2c96c6cec..fc65e9fdddb3 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -140,11 +140,6 @@ #define PCIE_PHY_LINKUP_BIT BIT(0) #define PHY_RDY_LINKUP_BIT BIT(1) =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct nwl_msi { /* MSI information */ DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR); struct irq_domain *dev_domain; @@ -203,10 +198,10 @@ static int nwl_wait_for_link(struct nwl_pcie *pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (nwl_phy_link_up(pcie)) return 0; - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX); } =20 dev_err(dev, "PHY link never came up\n"); diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/cont= roller/plda/pcie-starfive.c index 298036c3e7f9..542a751b6f4d 100644 --- a/drivers/pci/controller/plda/pcie-starfive.c +++ b/drivers/pci/controller/plda/pcie-starfive.c @@ -45,11 +45,6 @@ #define STG_SYSCON_LNKSTA_OFFSET 0x170 #define DATA_LINK_ACTIVE BIT(5) =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct starfive_jh7110_pcie { struct plda_pcie_rp plda; struct reset_control *resets; @@ -217,12 +212,12 @@ static int starfive_pcie_host_wait_for_link(struct st= arfive_jh7110_pcie *pcie) int retries; =20 /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (starfive_pcie_link_up(&pcie->plda)) { dev_info(pcie->plda.dev, "port link up\n"); return 0; } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce..f47ed96d8ef2 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -63,6 +63,8 @@ struct pcie_tlp_log; /* Parameters for the waiting for link up routine */ #define PCIE_LINK_WAIT_MAX_RETRIES 10 #define PCIE_LINK_WAIT_SLEEP_MS 90 +#define PCIE_LINK_WAIT_US_MIN 90000 +#define PCIE_LINK_WAIT_US_MAX 100000 =20 /* Format of TLP; PCIe r7.0, sec 2.2.1 */ #define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */ --=20 2.52.0 From nobody Sun Jun 14 11:27:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 458703F660A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260402-tegra264-pcie-v4-3-21e2e19987e8@nvidia.com> References: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> In-Reply-To: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding , Manikanta Maddireddy X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=17760; i=treding@nvidia.com; h=from:subject:message-id; bh=XAv6ON8Tk23dt9XBaJ6T+ZZ8de7q2/yRx/rtD4s2sTI=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBpznzo41g7HE0MxM71XG3nHCqxM+ivApYZSocqM VXHPKjSVlSJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCac586AAKCRDdI6zXfz6z ofW8D/9DnArq+QPTRtevH7Nb7fBjJMLqeMZ2yjBwT/SCwwPYwQ6u/gVAiHHW2sXhC8igkqD+b9h T4QWWp1aydFr2e1O0i7AaXzbuJr4ExiXiJpmtSXb+f/Qq70bWt50SID+ResKO20EoG4C7Vl7lKf T8elXEZ+dwUvI+d5wdRuiIewGYl24+VeDmH1yEwDYKNn2XW2iY7lnGV04PhxIp7W/Cr50wynbg7 IatzTKb92JCtibYCV6smBIu0EdblysepWJrkVh5BzcbWEAUzRN9RVPLcgKwb5NnFMutIndprmGe Bcj6b6BhsMeb8C2jtJDFGZZ9wEq+n53XIT4h1MaYwdPESfE14YK4xuK28MplCN1VZtCCKyXB1UM 8yLP2DiVxSa2GX3e+UEVeDOa1B86GvpGk/eQdJEvdWb9wsOlioXfUjRVIDtaVZgObm7FvPmP5qU I9CkqVBf2dtY6xJpwwTBHlxvPTQucDXjlDCVl3EbRuUEu4v4+Z1w6eCQW5hjpB8P5xLGkz6FmXU 61r4rb75ZOWKS63MydMX/Zgdui3+DmzF+fJ8Lo/o8XHLDfpE4xcfFzl4wrBIBFY4wnO9Z+ztCdr EQwogY+JDRfZH/pfb5Ctrfu13xIUQpNkSC3Aas37/4dd5f6AOnpZQvBang6L3r3dfdSvtgKldK0 j34y0bSQVxEUYUA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The driver is very small, with its main purpose being to set up the address translation registers and then creating a standard PCI host using ECAM. Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- Changes in v2: - specify generations applicable for PCI_TEGRA driver to avoid confusion - drop SPDX-FileCopyrightText tag - rename link_state to link_up to clarify meaning - replace memset() by an empty initializer - sanity-check only enable BAR regions - bring PCI link out of reset in case firmware didn't - use common wait times instead of defining our own - use core helpers to parse and print PCI link speed - fix multi-line comment - use dev_err_probe() more ubiquitously - fix probe sequence and error cleanup - use DEFINE_NOIRQ_DEV_PM_OPS() to avoid warnings for !PM_SUSPEND - reuse more standard registers and remove unused register definitions - use %pe and ERR_PTR() to print symbolic errors - add signed-off-by from Manikanta as the original author - add myself as author after significantly modifying the driver --- drivers/pci/controller/Kconfig | 10 +- drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-tegra264.c | 527 +++++++++++++++++++++++++++++= ++++ 3 files changed, 537 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5aaed8ac6e44..6ead04f7bd6e 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -254,7 +254,15 @@ config PCI_TEGRA select IRQ_MSI_LIB help Say Y here if you want support for the PCIe host controller found - on NVIDIA Tegra SoCs. + on NVIDIA Tegra SoCs (Tegra20 through Tegra186). + +config PCIE_TEGRA264 + bool "NVIDIA Tegra264 PCIe controller" + depends on ARCH_TEGRA || COMPILE_TEST + depends on PCI_MSI + help + Say Y here if you want support for the PCIe host controller found + on NVIDIA Tegra264 SoCs. =20 config PCIE_RCAR_HOST bool "Renesas R-Car PCIe controller (host mode)" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makef= ile index ac8db283f0fe..d478743b5142 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_HYPERV_INTERFACE) +=3D pci-hyperv-intf.o obj-$(CONFIG_PCI_MVEBU) +=3D pci-mvebu.o obj-$(CONFIG_PCI_AARDVARK) +=3D pci-aardvark.o obj-$(CONFIG_PCI_TEGRA) +=3D pci-tegra.o +obj-$(CONFIG_PCIE_TEGRA264) +=3D pcie-tegra264.o obj-$(CONFIG_PCI_RCAR_GEN2) +=3D pci-rcar-gen2.o obj-$(CONFIG_PCIE_RCAR_HOST) +=3D pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCIE_RCAR_EP) +=3D pcie-rcar.o pcie-rcar-ep.o diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controlle= r/pcie-tegra264.c new file mode 100644 index 000000000000..3ce1ad971bdb --- /dev/null +++ b/drivers/pci/controller/pcie-tegra264.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe host controller driver for Tegra264 SoC + * + * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../pci.h" + +/* XAL registers */ +#define XAL_RC_ECAM_BASE_HI 0x00 +#define XAL_RC_ECAM_BASE_LO 0x04 +#define XAL_RC_ECAM_BUSMASK 0x08 +#define XAL_RC_IO_BASE_HI 0x0c +#define XAL_RC_IO_BASE_LO 0x10 +#define XAL_RC_IO_LIMIT_HI 0x14 +#define XAL_RC_IO_LIMIT_LO 0x18 +#define XAL_RC_MEM_32BIT_BASE_HI 0x1c +#define XAL_RC_MEM_32BIT_BASE_LO 0x20 +#define XAL_RC_MEM_32BIT_LIMIT_HI 0x24 +#define XAL_RC_MEM_32BIT_LIMIT_LO 0x28 +#define XAL_RC_MEM_64BIT_BASE_HI 0x2c +#define XAL_RC_MEM_64BIT_BASE_LO 0x30 +#define XAL_RC_MEM_64BIT_LIMIT_HI 0x34 +#define XAL_RC_MEM_64BIT_LIMIT_LO 0x38 +#define XAL_RC_BAR_CNTL_STANDARD 0x40 +#define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN BIT(0) +#define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN BIT(1) +#define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN BIT(2) + +/* XTL registers */ +#define XTL_RC_PCIE_CFG_LINK_STATUS 0x5a + +#define XTL_RC_MGMT_PERST_CONTROL 0x218 +#define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N BIT(0) + +#define XTL_RC_MGMT_CLOCK_CONTROL 0x47c +#define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT BIT= (9) + +struct tegra264_pcie { + struct device *dev; + bool link_up; + + /* I/O memory */ + void __iomem *xal; + void __iomem *xtl; + void __iomem *ecam; + + /* bridge configuration */ + struct pci_config_window *cfg; + struct pci_host_bridge *bridge; + + /* wake IRQ */ + struct gpio_desc *wake_gpio; + unsigned int wake_irq; + + /* BPMP and bandwidth management */ + struct icc_path *icc_path; + struct tegra_bpmp *bpmp; + u32 ctl_id; +}; + +static int tegra264_pcie_parse_dt(struct tegra264_pcie *pcie) +{ + int err; + + pcie->wake_gpio =3D devm_gpiod_get_optional(pcie->dev, "nvidia,pex-wake", + GPIOD_IN); + if (IS_ERR(pcie->wake_gpio)) + return PTR_ERR(pcie->wake_gpio); + + if (pcie->wake_gpio) { + device_init_wakeup(pcie->dev, true); + + err =3D gpiod_to_irq(pcie->wake_gpio); + if (err < 0) { + dev_err(pcie->dev, "failed to get wake IRQ: %pe\n", + ERR_PTR(err)); + return err; + } + + pcie->wake_irq =3D (unsigned int)err; + } + + return 0; +} + +static void tegra264_pcie_bpmp_set_rp_state(struct tegra264_pcie *pcie) +{ + struct tegra_bpmp_message msg =3D {}; + struct mrq_pcie_request req =3D {}; + int err; + + req.cmd =3D CMD_PCIE_RP_CONTROLLER_OFF; + req.rp_ctrlr_off.rp_controller =3D pcie->ctl_id; + + msg.mrq =3D MRQ_PCIE; + msg.tx.data =3D &req; + msg.tx.size =3D sizeof(req); + + err =3D tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + dev_info(pcie->dev, "failed to turn off PCIe #%u: %pe\n", + pcie->ctl_id, ERR_PTR(err)); + + if (msg.rx.ret) + dev_info(pcie->dev, "failed to turn off PCIe #%u: %d\n", + pcie->ctl_id, msg.rx.ret); +} + +static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie) +{ + u32 value, speed, width, bw; + int err; + + value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, value); + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, value); + + bw =3D width * (PCIE_SPEED2MBS_ENC(speed) / BITS_PER_BYTE); + value =3D MBps_to_icc(bw); + + err =3D icc_set_bw(pcie->icc_path, bw, bw); + if (err < 0) + dev_err(pcie->dev, + "failed to request bandwidth (%u MBps): %pe\n", + bw, ERR_PTR(err)); +} + +/* + * The various memory regions used by the controller (I/O, memory, ECAM) a= re + * set up during early boot and have hardware-level protections in place. = If + * the DT ranges don't match what's been setup, the controller won't be ab= le + * to write the address endpoints properly, so make sure to validate that = DT + * and firmware programming agree on these ranges. + */ +static bool tegra264_pcie_check_ranges(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + struct device_node *np =3D pcie->dev->of_node; + struct of_pci_range_parser parser; + phys_addr_t phys, limit, hi, lo; + struct of_pci_range range; + struct resource *res; + bool status =3D true; + u32 value; + int err; + + err =3D of_pci_range_parser_init(&parser, np); + if (err < 0) + return false; + + for_each_of_pci_range(&parser, &range) { + unsigned int addr_hi, addr_lo, limit_hi, limit_lo, enable; + unsigned long type =3D range.flags & IORESOURCE_TYPE_BITS; + phys_addr_t start, end, mask; + const char *region =3D NULL; + + end =3D range.cpu_addr + range.size - 1; + start =3D range.cpu_addr; + + switch (type) { + case IORESOURCE_IO: + addr_hi =3D XAL_RC_IO_BASE_HI; + addr_lo =3D XAL_RC_IO_BASE_LO; + limit_hi =3D XAL_RC_IO_LIMIT_HI; + limit_lo =3D XAL_RC_IO_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN; + mask =3D SZ_64K - 1; + region =3D "I/O"; + break; + + case IORESOURCE_MEM: + if (range.flags & IORESOURCE_PREFETCH) { + addr_hi =3D XAL_RC_MEM_64BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_64BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_64BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_64BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN; + region =3D "prefetchable memory"; + } else { + addr_hi =3D XAL_RC_MEM_32BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_32BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_32BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_32BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN; + region =3D "memory"; + } + + mask =3D SZ_1M - 1; + break; + } + + /* not interested in anything that's not I/O or memory */ + if (!region) + continue; + + /* don't check regions that haven't been enabled */ + value =3D readl(pcie->xal + XAL_RC_BAR_CNTL_STANDARD); + if ((value & enable) =3D=3D 0) + continue; + + hi =3D readl(pcie->xal + addr_hi); + lo =3D readl(pcie->xal + addr_lo); + phys =3D hi << 32 | lo; + + hi =3D readl(pcie->xal + limit_hi); + lo =3D readl(pcie->xal + limit_lo); + limit =3D hi << 32 | lo | mask; + + if (phys !=3D start || limit !=3D end) { + dev_err(pcie->dev, + "%s region mismatch: %pap-%pap -> %pap-%pap\n", + region, &phys, &limit, &start, &end); + status =3D false; + } + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return false; + + hi =3D readl(pcie->xal + XAL_RC_ECAM_BASE_HI); + lo =3D readl(pcie->xal + XAL_RC_ECAM_BASE_LO); + phys =3D hi << 32 | lo; + + value =3D readl(pcie->xal + XAL_RC_ECAM_BUSMASK); + limit =3D phys + ((value + 1) << 20) - 1; + + if (phys !=3D res->start || limit !=3D res->end) { + dev_err(pcie->dev, + "ECAM region mismatch: %pap-%pap -> %pap-%pap\n", + &phys, &limit, &res->start, &res->end); + status =3D false; + } + + return status; +} + +static bool tegra264_pcie_link_up(struct tegra264_pcie *pcie, + enum pci_bus_speed *speed) +{ + u16 value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + + if (value & PCI_EXP_LNKSTA_DLLLA) { + if (speed) + *speed =3D pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, + value)]; + + return true; + } + + return false; +} + +static void tegra264_pcie_init(struct tegra264_pcie *pcie) +{ + enum pci_bus_speed speed; + unsigned int i; + u32 value; + + /* bring the link out of reset */ + value =3D readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + value |=3D XTL_RC_MGMT_PERST_CONTROL_PERST_O_N; + writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + + if (!tegra_is_silicon()) { + dev_info(pcie->dev, + "skipping link state for PCIe #%u in simulation\n", + pcie->ctl_id); + pcie->link_up =3D true; + return; + } + + for (i =3D 0; i < PCIE_LINK_WAIT_MAX_RETRIES; i++) { + if (tegra264_pcie_link_up(pcie, NULL)) + break; + + usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX); + } + + if (tegra264_pcie_link_up(pcie, &speed)) { + /* Per PCIe r5.0, 6.6.1 wait for 100ms after DLL up */ + msleep(PCIE_RESET_CONFIG_WAIT_MS); + + dev_info(pcie->dev, "PCIe #%u link is up (speed: %s)\n", + pcie->ctl_id, pci_speed_string(speed)); + tegra264_pcie_icc_set(pcie); + pcie->link_up =3D true; + } else { + dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id); + + value =3D readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL); + + /* + * Set link state only when link fails and no hot-plug feature + * is present. + */ + if ((value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PR= SNT) =3D=3D 0) { + dev_info(pcie->dev, + "PCIe #%u link is down and not hotplug-capable, turning off\n", + pcie->ctl_id); + tegra264_pcie_bpmp_set_rp_state(pcie); + pcie->link_up =3D false; + } else { + pcie->link_up =3D true; + } + } +} + +static int tegra264_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct tegra264_pcie *pcie; + struct resource_entry *bus; + struct resource *res; + int err; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie)); + if (!bridge) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate host bridge\n"); + + pcie =3D pci_host_bridge_priv(bridge); + platform_set_drvdata(pdev, pcie); + pcie->bridge =3D bridge; + pcie->dev =3D dev; + + err =3D pinctrl_pm_select_default_state(dev); + if (err < 0) + return dev_err_probe(dev, err, + "failed to configure sideband pins\n"); + + err =3D tegra264_pcie_parse_dt(pcie); + if (err < 0) + return dev_err_probe(dev, err, "failed to parse device tree"); + + pcie->xal =3D devm_platform_ioremap_resource_byname(pdev, "xal"); + if (IS_ERR(pcie->xal)) + return dev_err_probe(dev, PTR_ERR(pcie->xal), + "failed to map XAL memory\n"); + + pcie->xtl =3D devm_platform_ioremap_resource_byname(pdev, "xtl-pri"); + if (IS_ERR(pcie->xtl)) + return dev_err_probe(dev, PTR_ERR(pcie->xtl), + "failed to map XTL-PRI memory\n"); + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return dev_err_probe(dev, -ENODEV, + "failed to get bus resources\n"); + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return dev_err_probe(dev, -ENXIO, + "failed to get ECAM resource\n"); + + pcie->icc_path =3D devm_of_icc_get(&pdev->dev, "write"); + if (IS_ERR(pcie->icc_path)) + return dev_err_probe(&pdev->dev, PTR_ERR(pcie->icc_path), + "failed to get ICC"); + + /* + * Parse BPMP property only for silicon, as interaction with BPMP is + * not needed for other platforms. + */ + if (tegra_is_silicon()) { + pcie->bpmp =3D tegra_bpmp_get_with_id(dev, &pcie->ctl_id); + if (IS_ERR(pcie->bpmp)) + return dev_err_probe(dev, PTR_ERR(pcie->bpmp), + "failed to get BPMP\n"); + } + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + /* sanity check that programmed ranges match what's in DT */ + if (!tegra264_pcie_check_ranges(pdev)) { + err =3D -EINVAL; + goto put_pm; + } + + pcie->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) { + err =3D dev_err_probe(dev, PTR_ERR(pcie->cfg), + "failed to create ECAM\n"); + goto put_pm; + } + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + bridge->sysdata =3D pcie->cfg; + pcie->ecam =3D pcie->cfg->win; + + tegra264_pcie_init(pcie); + + if (!pcie->link_up) + goto free; + + err =3D pci_host_probe(bridge); + if (err < 0) { + dev_err(dev, "failed to register host: %pe\n", ERR_PTR(err)); + goto free; + } + + return err; + +free: + pci_ecam_free(pcie->cfg); +put_pm: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + + if (tegra_is_silicon()) + tegra_bpmp_put(pcie->bpmp); + + return err; +} + +static void tegra264_pcie_remove(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + + /* + * If we undo tegra264_pcie_init() then link goes down and need + * controller reset to bring up the link again. Remove intention is + * to clean up the root bridge and re-enumerate during bind. + */ + pci_lock_rescan_remove(); + pci_stop_root_bus(pcie->bridge->bus); + pci_remove_root_bus(pcie->bridge->bus); + pci_unlock_rescan_remove(); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + if (tegra_is_silicon()) + tegra_bpmp_put(pcie->bpmp); + + pci_ecam_free(pcie->cfg); +} + +static int tegra264_pcie_suspend_noirq(struct device *dev) +{ + struct tegra264_pcie *pcie =3D dev_get_drvdata(dev); + int err; + + if (pcie->wake_gpio && device_may_wakeup(dev)) { + err =3D enable_irq_wake(pcie->wake_irq); + if (err < 0) + dev_err(dev, "failed to enable wake IRQ: %pe\n", + ERR_PTR(err)); + } + + return 0; +} + +static int tegra264_pcie_resume_noirq(struct device *dev) +{ + struct tegra264_pcie *pcie =3D dev_get_drvdata(dev); + int err; + + if (pcie->wake_gpio && device_may_wakeup(dev)) { + err =3D disable_irq_wake(pcie->wake_irq); + if (err < 0) + dev_err(dev, "failed to disable wake IRQ: %pe\n", + ERR_PTR(err)); + } + + if (pcie->link_up =3D=3D false) + return 0; + + tegra264_pcie_init(pcie); + + return 0; +} + +static DEFINE_NOIRQ_DEV_PM_OPS(tegra264_pcie_pm_ops, + tegra264_pcie_suspend_noirq, + tegra264_pcie_resume_noirq); + +static const struct of_device_id tegra264_pcie_of_match[] =3D { + { + .compatible =3D "nvidia,tegra264-pcie", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match); + +static struct platform_driver tegra264_pcie_driver =3D { + .probe =3D tegra264_pcie_probe, + .remove =3D tegra264_pcie_remove, + .driver =3D { + .name =3D "tegra264-pcie", + .pm =3D &tegra264_pcie_pm_ops, + .of_match_table =3D tegra264_pcie_of_match, + }, +}; +module_platform_driver(tegra264_pcie_driver); + +MODULE_AUTHOR("Manikanta Maddireddy "); +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver"); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sun Jun 14 11:27:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B785D3EF659; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i2swjqI+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFAD1C116C6; Thu, 2 Apr 2026 14:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775140086; bh=jYBBKg3Y7KpHmnh21GneYr3GYiLyKe3yBAWQm4Vwwh0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i2swjqI+h0T5bux1CJM2467rAsYnpRwolgzO20v4Ry76ARm4rRpzWX1/k4JwE4Hkq MPGxX+IMihKdoVomu5SE0m/2gtxq9SbuHTpt6M1QUCupBM2mggcre1haFgEJEkmhy6 cCAFDMG/cBYvAG+2cfePj8hRcD4wdL+DiK5aM0JKnOHiuAEi6AItuQ9SMN6RTNqyBL exXrnVjm1ViPv7p5oJxDI4sK02+F3Y01irTt/Tepqvkj5J+SU27lt5Mt6hc2u9Mik/ /avhc4jhZhMlmwh0PvmJQej12tIGKRGiLVn/+gFrgDy8DxbHibmlPmidjyd6VhDgr5 2BO+OU4Uru2OQ== From: Thierry Reding Date: Thu, 02 Apr 2026 16:27:38 +0200 Subject: [PATCH v4 4/4] arm64: tegra: Add PCI controllers on Tegra264 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260402-tegra264-pcie-v4-4-21e2e19987e8@nvidia.com> References: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> In-Reply-To: <20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=13747; i=treding@nvidia.com; h=from:subject:message-id; bh=SwZu0xB6YZN1HWZcXx7U3cnqXXmQ8x5xiYLkorAgNhA=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBpznzo0esIf0137W0PrUfR2DWoc9RKd6WxH4QWU f5XqIWskFyJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCac586AAKCRDdI6zXfz6z oZGpD/9eJqcLW33/a4/u/eh01FMyrDhy6zijl5Y4Y7kgSZ54hK8RTmdAeHhn8GjGfxHIVx8he/3 f6GMz0uUSu/Wah0nj/CkMm9Bhux4oX5mBNrscnZPWumaVGPcPrAmcST77JPtF3Rqm5UNBE0QMuH SULG03M7dmMScC1R9Oquo7Tjxi4Iiu3B3v7xIIgG/Ss/Dx1wKPw58Wh4YFPUjBKNayIXsC/F7I+ fb8E8DyJfdZTMqxVlYNg4HpjIDQGgRBfVqFmr/tMrVJcYzwndZ9e2FdRrf3iGfnR9uRdrxVZVPQ Y8XLG/rITu7YW1BDcv+Bkw2webram3gmn0v6QdlehuX4gaPSH3gYCNpGq8pPIK9zaUrZocrMYyu zHdRLEf9ojpx2MRcnP8Vx8UNq4QFp+5eo9c61jDlipner9O8JhaDsPmhCmn9n+RMpiIpKY5TH+q HfC1qlpIYsAlOCKkwqpYxRMnLXjWoO0mR7NDB7zrkmziYIXxUEIhRhx2jHews403D0mprJfLSAt kSbXiLT96qWjhe8DEsJjrglmWoBujxHhAFDo1Kw1GSexubEvhiOYbhTvlS1CbLiELlpix9LpUaW UAVMj5Az8m7TelGMkb+ZiBtfmCS1Z+Ufen9bDcUWCcb+T7KQhiEh7PrkmMcBSXSwt2J2DB+fviz ijO7h7LIAmJ5LFw== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding A total of six PCIe controllers can be found on Tegra264. One of them is used internally for the integrated GPU while the other five can go to a variety of connectors like full PCIe slots or M.2. Signed-off-by: Thierry Reding --- Changes in v4: - revert ECAM "reg" entry order Changes in v2: - order ECAM "reg" entry before others --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 248 +++++++++++++++++++++++++++= ---- 1 file changed, 221 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 7644a41d5f72..1bf5a2368afe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -32,7 +32,7 @@ bus@0 { #address-cells =3D <2>; #size-cells =3D <2>; =20 - ranges =3D <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>; + ranges =3D <0x00 0x00000000 0x00 0x00000000 0x00 0x20000000>; /* MMIO (5= 12 MiB) */ =20 misc@100000 { compatible =3D "nvidia,tegra234-misc"; @@ -3356,9 +3356,10 @@ bus@8100000000 { #address-cells =3D <2>; #size-cells =3D <2>; =20 - ranges =3D <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */ - <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable= memory (32-bit) */ - <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchab= le memory, I/O */ + ranges =3D <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (5= 12 MiB) */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable= memory (32-bit, 512 MiB) */ + <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */ + <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefe= tchable memory (64-bit) */ =20 smmu1: iommu@5000000 { compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; @@ -3402,23 +3403,23 @@ cmdqv2: cmdqv@6200000 { =20 mc: memory-controller@8020000 { compatible =3D "nvidia,tegra264-mc"; - reg =3D <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */ - <0x00 0x8040000 0x0 0x20000>, /* MC 0 */ - <0x00 0x8060000 0x0 0x20000>, /* MC 1 */ - <0x00 0x8080000 0x0 0x20000>, /* MC 2 */ - <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */ - <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */ - <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */ - <0x00 0x8100000 0x0 0x20000>, /* MC 6 */ - <0x00 0x8120000 0x0 0x20000>, /* MC 7 */ - <0x00 0x8140000 0x0 0x20000>, /* MC 8 */ - <0x00 0x8160000 0x0 0x20000>, /* MC 9 */ - <0x00 0x8180000 0x0 0x20000>, /* MC 10 */ - <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */ - <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */ - <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */ - <0x00 0x8200000 0x0 0x20000>, /* MC 14 */ - <0x00 0x8220000 0x0 0x20000>; /* MC 15 */ + reg =3D <0x000 0x8020000 0x0 0x20000>, /* MC broadcast */ + <0x000 0x8040000 0x0 0x20000>, /* MC 0 */ + <0x000 0x8060000 0x0 0x20000>, /* MC 1 */ + <0x000 0x8080000 0x0 0x20000>, /* MC 2 */ + <0x000 0x80a0000 0x0 0x20000>, /* MC 3 */ + <0x000 0x80c0000 0x0 0x20000>, /* MC 4 */ + <0x000 0x80e0000 0x0 0x20000>, /* MC 5 */ + <0x000 0x8100000 0x0 0x20000>, /* MC 6 */ + <0x000 0x8120000 0x0 0x20000>, /* MC 7 */ + <0x000 0x8140000 0x0 0x20000>, /* MC 8 */ + <0x000 0x8160000 0x0 0x20000>, /* MC 9 */ + <0x000 0x8180000 0x0 0x20000>, /* MC 10 */ + <0x000 0x81a0000 0x0 0x20000>, /* MC 11 */ + <0x000 0x81c0000 0x0 0x20000>, /* MC 12 */ + <0x000 0x81e0000 0x0 0x20000>, /* MC 13 */ + <0x000 0x8200000 0x0 0x20000>, /* MC 14 */ + <0x000 0x8220000 0x0 0x20000>; /* MC 15 */ reg-names =3D "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", @@ -3437,12 +3438,12 @@ mc: memory-controller@8020000 { #size-cells =3D <2>; =20 /* limit the DMA range for memory clients to [39:0] */ - dma-ranges =3D <0x0 0x0 0x0 0x0 0x100 0x0>; + dma-ranges =3D <0x000 0x0 0x000 0x0 0x100 0x0>; =20 emc: external-memory-controller@8800000 { compatible =3D "nvidia,tegra264-emc"; - reg =3D <0x00 0x8800000 0x0 0x20000>, - <0x00 0x8890000 0x0 0x20000>; + reg =3D <0x000 0x8800000 0x0 0x20000>, + <0x000 0x8890000 0x0 0x20000>; interrupts =3D ; clocks =3D <&bpmp TEGRA264_CLK_EMC>, <&bpmp TEGRA264_CLK_DBB_UPHY0>; @@ -3493,6 +3494,38 @@ cmdqv4: cmdqv@b200000 { status =3D "disabled"; }; =20 + pci@c000000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x0c000000 0x0 0x00004000>, + <0x00 0x0c004000 0x0 0x00001000>, + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x00>; + #interrupt-cells =3D <0x1>; + + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 IRQ_TYPE_LEVEL_= HIGH>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map =3D <0x0 &smmu2 0x10000 0x10000>; + msi-map =3D <0x0 &its 0x210000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>= , /* I/O */ + <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-= prefetchable memory (128 MiB) */ + <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ + bus-range =3D <0x0 0xff>; + + nvidia,bpmp =3D <&bpmp 0>; + status =3D "disabled"; + }; + i2c14: i2c@c410000 { compatible =3D "nvidia,tegra264-i2c"; reg =3D <0x00 0x0c410000 0x0 0x10000>; @@ -3720,7 +3753,7 @@ bus@8800000000 { #address-cells =3D <2>; #size-cells =3D <2>; =20 - ranges =3D <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; + ranges =3D <0x00 0x00000000 0x88 0x00000000 0x00 0x20000000>; /* MMIO (5= 12 MiB) */ =20 smmu3: iommu@6000000 { compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; @@ -3765,8 +3798,169 @@ bus@a800000000 { #address-cells =3D <2>; #size-cells =3D <2>; =20 - ranges =3D <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, E= CAM, prefetchable memory, I/O */ - <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable= memory (32-bit) */ + ranges =3D <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (5= 12 MiB) */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable= memory (32-bit, 1536 GiB) */ + <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefe= tchable memory (64-bit) */ + + pci@8400000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x08400000 0x0 0x00004000>, + <0x00 0x08404000 0x0 0x00001000>, + <0x00 0x08405000 0x0 0x00001000>, + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x01>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 IRQ_TYPE_LEVEL_= HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map =3D <0x0 &smmu1 0x10000 0x10000>; + msi-map =3D <0x0 &its 0x110000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>= , /* I/O */ + <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-= prefetchable memory */ + <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ + bus-range =3D <0x00 0xff>; + + nvidia,bpmp =3D <&bpmp 1>; + status =3D "disabled"; + }; + + pci@8420000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x08420000 0x0 0x00004000>, + <0x00 0x08424000 0x0 0x00001000>, + <0x00 0x08425000 0x0 0x00001000>, + <0x00 0x08430000 0x0 0x00010000>, + <0xb0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x02>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 917 IRQ_TYPE_LEVEL_= HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 918 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 919 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 920 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map =3D <0x0 &smmu1 0x20000 0x10000>; + msi-map =3D <0x0 &its 0x120000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>= , /* I/O */ + <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-= prefetchable memory */ + <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ + bus-range =3D <0x00 0xff>; + + nvidia,bpmp =3D <&bpmp 2>; + status =3D "disabled"; + }; + + pci@8440000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x08440000 0x0 0x00004000>, + <0x00 0x08444000 0x0 0x00001000>, + <0x00 0x08445000 0x0 0x00001000>, + <0x00 0x08450000 0x0 0x00010000>, + <0xb8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x03>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 926 IRQ_TYPE_LEVEL_= HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 927 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 928 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 929 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map =3D <0x0 &smmu1 0x30000 0x10000>; + msi-map =3D <0x0 &its 0x130000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>= , /* I/O */ + <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-= prefetchable memory */ + <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ + bus-range =3D <0x00 0xff>; + + nvidia,bpmp =3D <&bpmp 3>; + status =3D "disabled"; + }; + + pci@8460000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x08460000 0x0 0x00004000>, + <0x00 0x08464000 0x0 0x00001000>, + <0x00 0x08465000 0x0 0x00001000>, + <0x00 0x08470000 0x0 0x00010000>, + <0xc0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x04>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 935 IRQ_TYPE_LEVEL_= HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 936 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 937 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 938 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map =3D <0x0 &smmu1 0x40000 0x10000>; + msi-map =3D <0x0 &its 0x140000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>= , /* I/O */ + <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-= prefetchable memory */ + <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ + bus-range =3D <0x00 0xff>; + + nvidia,bpmp =3D <&bpmp 4>; + status =3D "disabled"; + }; + + pci@8480000 { + compatible =3D "nvidia,tegra264-pcie"; + reg =3D <0x00 0x08480000 0x0 0x00004000>, + <0x00 0x08484000 0x0 0x00001000>, + <0x00 0x08485000 0x0 0x00001000>, + <0x00 0x08490000 0x0 0x00010000>, + <0xc8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + linux,pci-domain =3D <0x05>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 944 IRQ_TYPE_LEVEL_= HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 945 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 946 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 947 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map =3D <0x0 &smmu1 0x50000 0x10000>; + msi-map =3D <0x0 &its 0x150000 0x10000>; + dma-coherent; + + ranges =3D <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>= , /* I/O */ + <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-= prefetchable memory */ + <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ + bus-range =3D <0x00 0xff>; + + nvidia,bpmp =3D <&bpmp 5>; + status =3D "disabled"; + }; }; =20 cpus { --=20 2.52.0