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Wed, 01 Apr 2026 19:20:26 -0700 (PDT) From: Alexey Klimov Date: Thu, 02 Apr 2026 03:20:15 +0100 Subject: [PATCH v2 2/3] mailbox: exynos: Add support for Exynos850 mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260402-exynos850-ap2apm-mailbox-v2-2-ca5ffdff99d4@linaro.org> References: <20260402-exynos850-ap2apm-mailbox-v2-0-ca5ffdff99d4@linaro.org> In-Reply-To: <20260402-exynos850-ap2apm-mailbox-v2-0-ca5ffdff99d4@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Sam Protsenko , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tudor Ambarus , Jassi Brar Cc: Krzysztof Kozlowski , Peter Griffin , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 Exynos850-based platforms support ACPM and has similar workflow of communicating with ACPM via mailbox, however mailbox controller registers are located at different offsets and writes/reads could be different. To distinguish between such different behaviours, the registers offsets for Exynos850 and the platform-specific data structs are introduced and configuration is described in such structs for gs101 and exynos850 based SoCs. Probe routine now selects the corresponding platform-specific data via device_get_match_data(). Signed-off-by: Alexey Klimov Reviewed-by: Krzysztof Kozlowski --- drivers/mailbox/exynos-mailbox.c | 67 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mail= box.c index d2355b128ba4..f9c59c07558a 100644 --- a/drivers/mailbox/exynos-mailbox.c +++ b/drivers/mailbox/exynos-mailbox.c @@ -31,14 +31,61 @@ =20 #define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK) =20 +#define EXYNOS850_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */ +#define EXYNOS850_MBOX_INTGR0 0x8 /* Interrupt Generation Register 0 */ +#define EXYNOS850_MBOX_INTCR0 0x0C /* Interrupt Clear Register 0 */ +#define EXYNOS850_MBOX_INTMR0 0x10 /* Interrupt Mask Register 0 */ +#define EXYNOS850_MBOX_INTSR0 0x14 /* Interrupt Status Register 0 */ +#define EXYNOS850_MBOX_INTMSR0 0x18 /* Interrupt Mask Status Register 0 */ +#define EXYNOS850_MBOX_INTGR1 0x1C /* Interrupt Generation Register 1 */ +#define EXYNOS850_MBOX_INTMR1 0x24 /* Interrupt Mask Register 1 */ +#define EXYNOS850_MBOX_INTSR1 0x28 /* Interrupt Status Register 1 */ +#define EXYNOS850_MBOX_INTMSR1 0x2C /* Interrupt Mask Status Register 1 */ +#define EXYNOS850_MBOX_VERSION 0x70 + +#define EXYNOS850_MBOX_INTMR1_MASK GENMASK(15, 0) + +/** + * struct exynos_mbox_driver_data - platform-specific mailbox configuratio= n. + * @irq_doorbell_offset: offset to the IRQ generation register, doorbell + * to APM co-processor. + * @irq_doorbell_shift: shift to apply to the value written to IRQ + * generation register. + * @irq_mask_offset: offset to the IRQ mask register. + * @irq_mask_value: value to right to the mask register to mask out + * all interrupts. + */ +struct exynos_mbox_driver_data { + u16 irq_doorbell_offset; + u16 irq_doorbell_shift; + u16 irq_mask_offset; + u16 irq_mask_value; +}; + /** * struct exynos_mbox - driver's private data. * @regs: mailbox registers base address. * @mbox: pointer to the mailbox controller. + * @data: pointer to driver platform-specific data. */ struct exynos_mbox { void __iomem *regs; struct mbox_controller *mbox; + const struct exynos_mbox_driver_data *data; +}; + +static const struct exynos_mbox_driver_data exynos850_mbox_data =3D { + .irq_doorbell_offset =3D EXYNOS850_MBOX_INTGR0, + .irq_doorbell_shift =3D 16, + .irq_mask_offset =3D EXYNOS850_MBOX_INTMR1, + .irq_mask_value =3D EXYNOS850_MBOX_INTMR1_MASK, +}; + +static const struct exynos_mbox_driver_data exynos_gs101_mbox_data =3D { + .irq_doorbell_offset =3D EXYNOS_MBOX_INTGR1, + .irq_doorbell_shift =3D 0, + .irq_mask_offset =3D EXYNOS_MBOX_INTMR0, + .irq_mask_value =3D EXYNOS_MBOX_INTMR0_MASK, }; =20 static int exynos_mbox_send_data(struct mbox_chan *chan, void *data) @@ -57,7 +104,8 @@ static int exynos_mbox_send_data(struct mbox_chan *chan,= void *data) return -EINVAL; } =20 - writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1); + writel(BIT(msg->chan_id) << exynos_mbox->data->irq_doorbell_shift, + exynos_mbox->regs + exynos_mbox->data->irq_doorbell_offset); =20 return 0; } @@ -87,13 +135,21 @@ static struct mbox_chan *exynos_mbox_of_xlate(struct m= box_controller *mbox, } =20 static const struct of_device_id exynos_mbox_match[] =3D { - { .compatible =3D "google,gs101-mbox" }, + { + .compatible =3D "google,gs101-mbox", + .data =3D &exynos_gs101_mbox_data + }, + { + .compatible =3D "samsung,exynos850-mbox", + .data =3D &exynos850_mbox_data + }, {}, }; MODULE_DEVICE_TABLE(of, exynos_mbox_match); =20 static int exynos_mbox_probe(struct platform_device *pdev) { + const struct exynos_mbox_driver_data *data; struct device *dev =3D &pdev->dev; struct exynos_mbox *exynos_mbox; struct mbox_controller *mbox; @@ -122,6 +178,11 @@ static int exynos_mbox_probe(struct platform_device *p= dev) return dev_err_probe(dev, PTR_ERR(pclk), "Failed to enable clock.\n"); =20 + data =3D device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + + exynos_mbox->data =3D data; mbox->num_chans =3D EXYNOS_MBOX_CHAN_COUNT; mbox->chans =3D chans; mbox->dev =3D dev; @@ -133,7 +194,7 @@ static int exynos_mbox_probe(struct platform_device *pd= ev) platform_set_drvdata(pdev, exynos_mbox); =20 /* Mask out all interrupts. We support just polling channels for now. */ - writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0); + writel(data->irq_mask_value, exynos_mbox->regs + data->irq_mask_offset); =20 return devm_mbox_controller_register(dev, mbox); } --=20 2.51.0