From nobody Sun Apr 5 19:50:06 2026 Received: from mail-43101.protonmail.ch (mail-43101.protonmail.ch [185.70.43.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A9E33CAE6A for ; Thu, 2 Apr 2026 23:09:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775171380; cv=none; b=lG+aYT5hZ17pAj8fEqCYfNBCCM/4v/UM5z5u/97m8mBpsbOcROjLAd7r0crWgLQO65YnWW6316t/x7o+SbBIFM7B8CbXWOYY7HX9VSydB87RG5sXVaWSnWSZlb9wbQRy5OrHKy/OYyEi+b2MiYAgtGRbAzSA8JkenVsMeJoMUGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775171380; c=relaxed/simple; bh=sjTb348AHUewwGk80X2mbrV7aXERcHAbGOkvX3abnHk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j8dCve4L8/qqeNLWxDAwV5qnjNlp2BVG6N+LE7JM5Z9+s9k8e1SCkaT/ylkvyl8gh76NN/O9dbyagbZKzqACx73DwJmHz/6GDIW+B2TPRTxD7aIrTjbw/sULq85d7pRHpqdBdBXg4BiTnWxPL1L7DkC6Mf7EatKu5xzYoY4F0Jk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=OXP1FSyt; arc=none smtp.client-ip=185.70.43.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="OXP1FSyt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775171377; x=1775430577; bh=sjTb348AHUewwGk80X2mbrV7aXERcHAbGOkvX3abnHk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=OXP1FSytZr2lVqzBVwut/DZqHEuUY8BolFD8t+2wIa0aKrAFMTWOhmJYQT+02szT6 l2VujR0UU+kXhbMoA0cYCQt+qB5ZOVpgXAFQ/JkPaw6AwBYIE8I2DKpP8bkv5BUL4M 0YEvdoeTOF/WQBqe9TNGKKtWuN50ya4LXCb7h1tEYFjXFUBzSFWjIQwxNuCp9doTJu 0rS62ZvsfewuODCd3VREMveMbv3injRnwW/HkTQeb9zc148fy0BX0VDSJGrsScYoVp zDondzzufj/AFXcpBgNovr6PL/QcVn6SHeQUO5k2efqgKSMTommW0iROYIAYcV7Hm1 9bvG5vofKLN8g== Date: Thu, 02 Apr 2026 23:09:32 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v2 4/6] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature Message-ID: <20260402-adreno-810-v2-4-ce337ca87a9e@pm.me> In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> References: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: b8def7380ff3b80ea1b49ff0111db2fc670cb38b Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 8b4b022d9a6b..102d5e751536 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -252,11 +252,12 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) } =20 /* - * Last span feature is only supported on PIPE specific register. - * So update those here + * Last span setting is only being applied to the last pipe specific + * register. Hence duplicate the last span from protect reg into the + * BR and BV protect reg pipe 15. */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); - a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); =20 a8xx_aperture_clear(gpu); } --=20 2.53.0