From nobody Sun Apr 5 19:50:05 2026 Received: from mail-244122.protonmail.ch (mail-244122.protonmail.ch [109.224.244.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3C07388374 for ; Thu, 2 Apr 2026 23:09:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.122 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775171377; cv=none; b=ahD4DwnbkqQDQhz14Jpyp2DZozRssPl5tHHovlkEFHDgy6rSovZTRBNawZKGZtkBy0BRDkyShdXu6Z1h8PvnNp9Rx6n2PqHtGvGWzUq8pJjZ4HdiyS7gTQaPepeoGA5jW53vXOV2Jsv0NiwwTXuIfRe6a+u+nCNrxSsj790K19A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775171377; c=relaxed/simple; bh=RlRxXYvppzZ7bfcFYOsZIhZMx/pbVhFUDd7ZxUpM630=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lJZAg1uD1ePSFHx6G0KKYaopqNF1/l2vxS4W3EXVKWke2qfP19P3D8D0Qt9/3awMLyFvnvvHJ2znCrevepPZtav2zQBnGDlCSX73kcaA31mh/5us2/SSF+Xl2CEmtTuA/KXgFz70E3kYT+/DBKxNeky6uDs3yXkcoPcByxyXFjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=JoyHTrVk; arc=none smtp.client-ip=109.224.244.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="JoyHTrVk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775171370; x=1775430570; bh=RlRxXYvppzZ7bfcFYOsZIhZMx/pbVhFUDd7ZxUpM630=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=JoyHTrVkwrzjxR3KbpaDI2/WX7U+KXlgCMBInfBTcgsxlwrAl03lR1NIJgAf/Hop/ hs3k2ooGDVJHxpS5Tu5is6xpAFsJm1vl52dU/u7NoRs1IVK8PHakZOX58uIJHBCest fy0ZOZAfIfxDJyev0K2ig1jfwIFe9HmXS0jxIyZKTIUU4VMmg79Vax9Yt24wdKdJwd c1EfcZ75zDF8oorrbaZNzyi/1orc8+tF7/mNB+W+ulWE11GvbxBH6YmR2uGWxrNXGP M7rI9azwcBj41VAuPxub1vWxyp/zSb7onf0nhIfKMgvQ/XWejv0+mSTu0KyCxfju6X 6KXRXK613I7PA== Date: Thu, 02 Apr 2026 23:09:24 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v2 3/6] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Message-ID: <20260402-adreno-810-v2-3-ce337ca87a9e@pm.me> In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> References: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 86696d82bda1591138d3e8a6205702be2b36a3fb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++---------------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 9847f83b92af..d691ad1f88b3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu= *a6xx_gpu) static void a6xx_llc_slices_init(struct platform_device *pdev, struct a6xx_gpu *a6xx_gpu, bool is_a7xx) { - struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) return; =20 - /* - * There is a different programming path for A6xx targets with an - * mmu500 attached, so detect if that is the case - */ - phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); - a6xx_gpu->have_mmu500 =3D (phandle && - of_device_is_compatible(phandle, "arm,mmu-500")); - of_node_put(phandle); - - if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); - else - a6xx_gpu->cx_misc_mmio =3D NULL; - a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); - - if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; const struct adreno_info *info =3D config->info; + struct device_node *phandle; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; @@ -2656,6 +2638,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 + /* + * There is a different programming path for A6xx targets with an + * mmu500 attached, so detect if that is the case + */ + phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); + a6xx_gpu->have_mmu500 =3D (phandle && + of_device_is_compatible(phandle, "arm,mmu-500")); + of_node_put(phandle); + + if (is_a7xx || !a6xx_gpu->have_mmu500) + a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); + else + a6xx_gpu->cx_misc_mmio =3D NULL; + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); --=20 2.53.0