From nobody Sun Apr 5 19:44:41 2026 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28CC33DD533; Thu, 2 Apr 2026 23:09:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775171360; cv=none; b=uQC0NJQo2UrvIHij9pMOUEAxDp94X2Z5GGxO+3CHJXyXlQr/64kUMjK6M6nohWQhQWcGtBQbeFl5m51TW1GLmlpFq/fGjy0T7cUeNgJEAMhV4IGRErnq9PXa8281NxdwQmr4Fp4jdE+V2i1jwsp5Tga16bssHd4GgOoMJ53LPT0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775171360; c=relaxed/simple; bh=r9NvQ+tTvtHR3vW1GmGFpBvoLnLsxwoOUA/zJ303pqQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Lr1peIZi8QYnGAnGlxzlzGVdGzuhABAo9Co51wM2kEQPoreiqG7jaC7ND8mB6PUSjVWK6KbMoD51Ihq7q+NKv1WiGQb3HHk649u60OP/DBtqq60YUGXnWEFgbmbFhz7Uk6wST7jGzW2Ster3JrvfpT7OQQhelZHdUdiuYYlqQ6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=ZBjSbFm3; arc=none smtp.client-ip=185.70.43.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="ZBjSbFm3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775171356; x=1775430556; bh=UmDpm+W7FVeu8x9a4pmc9IkUVg7Oepx1EmXNMUY6JxA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=ZBjSbFm3JVgN5tlkNFayJmQ0kma+8hzpSW7xFTqDoCLfdKooYnYSdjYHK5J3wOisX +xA2JGcgUvcOxbdBqUxpYd5Og3FKdjjJDsfmErz9evalTINJnB7pBS3KLQgiNoOOmE /cPk7gjoX5TOyVEi9V/yFZgE0BqUDBBTUamzR2T1PTEI92q1M3Nw/6RM1JnL1HW1Ek IsHOWTa2iHX+zC35BdDrhRv0YQWXzXhpxw6FDhaqiVpFXwldxRjQJWt+IMVfdG8NDa 8UUYTHYlJL93hrISA8jjN0wAe0BuCrENuXvFWPs6aLuNwdDLNPvL1lva95BsykB1fi yya+IPOOyfRsw== Date: Thu, 02 Apr 2026 23:09:13 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH RFC v2 2/6] drm/msm/adreno: rename llc_mmio to cx_misc_mmio Message-ID: <20260402-adreno-810-v2-2-ce337ca87a9e@pm.me> In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> References: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 114c91f44a0c387f33fd35904343927ed9746455 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This region is used for more than just LLCC, it also provides access to software fuse values (raytracing, etc). Rename relevant symbols from _llc to _cx_misc for use in a follow up change that decouples this from LLCC. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++-------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +++++++------- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 916c5d99c4d1..23e5b3a22ea5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsi= gned int state) =20 /* Turn on TCM (Tightly Coupled Memory) retention */ if (adreno_is_a7xx(adreno_gpu)) - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); + a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); else if (!adreno_is_a8xx(adreno_gpu)) gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); =20 @@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) if (!qcom_scm_is_available()) { dev_warn_once(gpu->dev->dev, "SCM is not available, poking fuse register\n"); - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); @@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) * firmware, find out whether that's the case. The scm call * above sets the fuse register. */ - fuse_val =3D a6xx_llc_read(a6xx_gpu, + fuse_val =3D a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); adreno_gpu->has_ray_tracing =3D !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); @@ -1299,7 +1299,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) =20 /* Check to see if we are doing a cold or warm boot */ if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { - status =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D= 1 ? + status =3D a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) = =3D=3D 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; } else if (gmu->legacy) { status =3D gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) =3D=3D 1 ? diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e1eae6cb1e40..9847f83b92af 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_misc_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2078,14 +2078,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx= _gpu) * pagetables */ if (!a6xx_gpu->have_mmu500) { - a6xx_llc_write(a6xx_gpu, + a6xx_cx_misc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); =20 /* * Program cacheability overrides to not allocate cache * lines on a write miss */ - a6xx_llc_rmw(a6xx_gpu, + a6xx_cx_misc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); return; } @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_misc_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2151,15 +2151,15 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, of_node_put(phandle); =20 if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->llc_mmio =3D msm_ioremap(pdev, "cx_mem"); + a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); else - a6xx_gpu->llc_mmio =3D NULL; + a6xx_gpu->cx_misc_mmio =3D NULL; =20 a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); =20 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); + a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2560,7 +2560,7 @@ static int a6xx_read_speedbin(struct device *dev, str= uct a6xx_gpu *a6xx_gpu, return ret; =20 if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { - *speedbin =3D a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMI= T_STATUS); + *speedbin =3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_= LIMIT_STATUS); *speedbin =3D A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*spe= edbin); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eb431e5e00b1..648608c1c98e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -102,7 +102,7 @@ struct a6xx_gpu { =20 bool has_whereami; =20 - void __iomem *llc_mmio; + void __iomem *cx_misc_mmio; void *llc_slice; void *htw_llc_slice; bool have_mmu500; @@ -240,19 +240,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *g= pu) return true; } =20 -static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 ma= sk, u32 or) +static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u3= 2 mask, u32 or) { - return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); + return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or); } =20 -static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) { - return readl(a6xx_gpu->llc_mmio + (reg << 2)); + return readl(a6xx_gpu->cx_misc_mmio + (reg << 2)); } =20 -static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 = value) +static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, = u32 value) { - writel(value, a6xx_gpu->llc_mmio + (reg << 2)); + writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2)); } =20 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 9e6f2ed69247..8b4b022d9a6b 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -103,7 +103,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) return; } =20 - slice_mask &=3D a6xx_llc_read(a6xx_gpu, + slice_mask &=3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL); =20 a6xx_gpu->slice_mask =3D slice_mask; --=20 2.53.0