From nobody Tue Apr 7 01:16:27 2026 Received: from mail-dl1-f41.google.com (mail-dl1-f41.google.com [74.125.82.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F3CE317162 for ; Wed, 1 Apr 2026 22:07:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775081224; cv=none; b=pRkOoSHYvWtsI4z29BdoWg28uHKKMXxoaPnecsnhw+GdRQJGzI0GCeHpdC9pL7rXZwMZsRD70Me5nJRd5lCxRcX4kFJaa2Y+/+AlBImGdSGZ52/FaAyZetik8jZe7W8/+jXk/EjZpLuQ4IXwh/42OXz/xrWXDx/zBV1zOO8PLGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775081224; c=relaxed/simple; bh=4isAXu8GsEMTQ84+cb9goVx2QJXHy/pHRFXm2xfgkYA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=gqCOv6Iu2uZv7mjg4lYn7P2Nmo5Lq42r67KVkkcWgQC8ghkfPKs1rFkn05iEboY7JAjI6J14iq95O0CvD2aipQ0ahr6sLRnFiKELy47ooN63T2atyjxzxidc6e539pQR/Y28crY0ltnj0sVAdE+pd64B5vTmlBce1vc555bvEug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SD09SWne; arc=none smtp.client-ip=74.125.82.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SD09SWne" Received: by mail-dl1-f41.google.com with SMTP id a92af1059eb24-128b9b7e3edso790649c88.0 for ; Wed, 01 Apr 2026 15:07:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775081222; x=1775686022; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=rRronI06lIok0fDejOYVVuN665UjtkDK5qK1tzC967Q=; b=SD09SWneYcrJ80k1idCFzG/Vv270DRTdPP37rUKtxF1VlkSMLQF/LyCpCMWl292W3T ySXAmkqJx03qZ0jvZdays/2WxgWIRwekCqS18dBOZIslhz8gSgcgm5CrdIwvYrU79XFQ xDweVnVdjuMmpsZqVe68hdq9LWo1hxhxaURE/TuWuiUNwGDI2k+S9fSj3TcgToGu9a6y 2HWeWGnqe2BUXAef7Rw88sSG+/hW81Bjvs0Lkiq4Lr+1xokxdiHqImsWL6wpJ/hq+Avr A1ieubT1sgQuujNXBBmSkG2m1YDuiWKpArK+aBfYVCw+Xx6vawmmHQAxy75etWWE3jMn iuzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775081222; x=1775686022; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=rRronI06lIok0fDejOYVVuN665UjtkDK5qK1tzC967Q=; b=nGPhK5h/qo9BBAtJ32Rp/m5E/rKkD55+PVjQXDMs5V45cOVkxH7kxo5b4sXd7cBfuY ntqPfObh2YNtpout4nNduzzRMyKqqAS3s0ovQC3nuhw4qkzS1rPQuLf/4XPIjVTqw/Pg QGhBV9GGlTA+tgcc0pvdFBoCeOp5K7Q5DMoFtIPd3+jkSoa6KIF/a9AIT/VbvkLJeNjP 1665tZk3EKTSYqjvNxajtz8zqK5RZsB6/2ZMOEQDj9kVr7JlIdKY6JGIcW6RLe971EKH na56XlEBOfGBP6jjTR2EBLFsJ//DonSetqt1saJrqgjojWs2Nm5dMMwUpNUDHLf8bAw+ hhVg== X-Forwarded-Encrypted: i=1; AJvYcCUAywF6aXi2HOVq7bmydwe3J7DRFAYbBn4WnDtly69S31+APZ8fUBSSbZ3GZq1u3oaN95OLB2FjRtJccCY=@vger.kernel.org X-Gm-Message-State: AOJu0Yyuk8fsCND9NMjtND/T3271e6KGD4ORZV3qzMYJ3yQFmKEXxm4F EdDsrTNRHn4C1r0sMJ6g6q9+FjSsev48ORbZMNx313MvUc9xMF9bnUT3 X-Gm-Gg: ATEYQzzMIK+ZpFDie9EExvsheUx+CtVzFX8hrvokfwXvIvmSSfIL5qAmhvs2MwK0cf2 InOfpG/1RthormSh4ec6/qvCorysX0oFDWc7Tg5wiAj4MjdxCHyPSR/Ayf2Y/FbbFlxfiMfxmbr MgwQI14WZspuCbeavsVJXn0T1GD3tup3njkhg/eGmQTU/MpkqnQK3KmFUqpziXI6bzviLGbt9WP RgWUX+V2Q2qNHJqfNK4bpQuT4M0DaxpJw0Xtv623G8LU7jLN3NqGf2SzwuWuMa14S2rhIzYK+CO /OCc8Y3oKcvKG6aKzx47Givjd4KqqaSo8WyjapDLYvtPOw4xQG03Cn9RQvvOKViKWDm7h+00HzC ld9o9brYghOu3Mtu6xwfD1vxSvsjXvxpppWX4KTRSDwSjy8AJh4PoocmEFS55s5mq0ePGvQsKqN sOv4y+oer/M3JzjVBtSmtzDizNwmTK9pdKQkEXvOu/WPsa/5TU5eVX/9GbzwHhrbTvHg== X-Received: by 2002:a05:7022:698b:b0:12a:7165:7405 with SMTP id a92af1059eb24-12be640d75amr3359834c88.8.1775081221588; Wed, 01 Apr 2026 15:07:01 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12bede54ba8sm1605984c88.10.2026.04.01.15.07.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 15:07:01 -0700 (PDT) From: Rosen Penev To: linux-arm-msm@vger.kernel.org Cc: Jeff Hugo , Carl Vanderlip , Oded Gabbay , Kees Cook , "Gustavo A. R. Silva" , dri-devel@lists.freedesktop.org (open list:QUALCOMM CLOUD AI (QAIC) DRIVER), linux-kernel@vger.kernel.org (open list), linux-hardening@vger.kernel.org (open list:KERNEL HARDENING (not covered by other areas):Keyword:\b__counted_by(_le|_be)?\b) Subject: [PATCHv2] accel/qaic: kcalloc + kzalloc to kzalloc Date: Wed, 1 Apr 2026 15:06:43 -0700 Message-ID: <20260401220643.12802-1-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Consolidate the two-element allocation into a single allocation using a flexible array member. This reduces memory fragmentation and simplifies the error path by eliminating the need to check for allocation failure between the two allocations. Add __counted_by for runtime bounds checking. Signed-off-by: Rosen Penev --- v2: use macro for number of elements. reword commit message. drivers/accel/qaic/qaic.h | 4 ++-- drivers/accel/qaic/qaic_drv.c | 8 +++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/accel/qaic/qaic.h b/drivers/accel/qaic/qaic.h index fa7a8155658c..e237020f6aa9 100644 --- a/drivers/accel/qaic/qaic.h +++ b/drivers/accel/qaic/qaic.h @@ -152,8 +152,6 @@ struct qaic_device { struct list_head cntl_xfer_list; /* Synchronizes MHI control device transactions and its xfer list */ struct mutex cntl_mutex; - /* Array of DBC struct of this device */ - struct dma_bridge_chan *dbc; /* Work queue for tasks related to MHI control device */ struct workqueue_struct *cntl_wq; /* Synchronizes all the users of device during cleanup */ @@ -206,6 +204,8 @@ struct qaic_device { void *ssr_mhi_buf; /* DBC which is under SSR. Sentinel U32_MAX would mean that no SSR in pro= gress */ u32 ssr_dbc; + /* Array of DBC struct of this device */ + struct dma_bridge_chan dbc[] __counted_by(num_dbc); }; struct qaic_drm_device { diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c index 63fb8c7b4abc..1dda8dfea5a4 100644 --- a/drivers/accel/qaic/qaic_drv.c +++ b/drivers/accel/qaic/qaic_drv.c @@ -43,6 +43,7 @@ MODULE_IMPORT_NS("DMA_BUF"); #define QAIC_DESC "Qualcomm Cloud AI Accelerators" #define CNTL_MAJOR 5 #define CNTL_MINOR 0 +#define DBC_NUM 16 struct qaic_device_config { /* Indicates the AIC family the device belongs to */ @@ -405,15 +406,12 @@ static struct qaic_device *create_qdev(struct pci_dev= *pdev, struct drm_device *drm; int i, ret; - qdev =3D devm_kzalloc(dev, sizeof(*qdev), GFP_KERNEL); + qdev =3D devm_kzalloc(dev, struct_size(qdev, dbc, DBC_NUM), GFP_KERNEL); if (!qdev) return NULL; + qdev->num_dbc =3D DBC_NUM; qdev->dev_state =3D QAIC_OFFLINE; - qdev->num_dbc =3D 16; - qdev->dbc =3D devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KE= RNEL); - if (!qdev->dbc) - return NULL; qddev =3D devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_= drm_device, drm); if (IS_ERR(qddev)) -- 2.53.0