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charset="utf-8" Add timestamp provider support for the Tegra264 in devicetree bindings. Tegra264 has two generic timestamping engines (GTE) which are the always-on GTE (AON) and legacy interrupt controller (LIC) GTE. Signed-off-by: Suneel Garapati --- .../devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-ht= e.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.ya= ml index 456797967adc..210200421a38 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -25,6 +25,8 @@ properties: - nvidia,tegra194-gte-lic - nvidia,tegra234-gte-aon - nvidia,tegra234-gte-lic + - nvidia,tegra264-gte-aon + - nvidia,tegra264-gte-lic =20 reg: maxItems: 1 @@ -112,6 +114,7 @@ allOf: contains: enum: - nvidia,tegra234-gte-aon + - nvidia,tegra264-gte-aon then: required: - nvidia,gpio-controller --=20 2.34.1 From nobody Sun Jun 14 08:18:31 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010052.outbound.protection.outlook.com [52.101.85.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 223B026299; 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charset="utf-8" Add AON-GTE mapping and LIC GTE instance support for the Tegra264. Move TSC clock parameters from macros to members of SoC data as values differ for Tegra264 chip. Signed-off-by: Suneel Garapati --- drivers/hte/hte-tegra194.c | 133 +++++++++++++++++++++++++++++++++++-- 1 file changed, 128 insertions(+), 5 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 690eb9be30fb..4a7702b32b24 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -20,10 +20,11 @@ =20 #define HTE_SUSPEND 0 =20 -/* HTE source clock TSC is 31.25MHz */ +/* HTE source clock TSC is 1GHz for T264 and 31.25MHz for others */ #define HTE_TS_CLK_RATE_HZ 31250000ULL +#define HTE_TS_CLK_RATE_1G 1000000000ULL #define HTE_CLK_RATE_NS 32 -#define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS) +#define HTE_CLK_RATE_NS_1G 1 =20 #define NV_AON_SLICE_INVALID -1 #define NV_LINES_IN_SLICE 32 @@ -120,6 +121,8 @@ struct tegra_hte_data { u32 slices; u32 map_sz; u32 sec_map_sz; + u64 tsc_clkrate_hz; + u32 tsc_clkrate_ns; const struct tegra_hte_line_mapped *map; const struct tegra_hte_line_mapped *sec_map; }; @@ -317,6 +320,94 @@ static const struct tegra_hte_line_mapped tegra234_aon= _gpio_sec_map[] =3D { [40] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, }; =20 +static const struct tegra_hte_line_mapped tegra264_aon_gpio_map[] =3D { + /* gpio, slice, bit_index */ + /* AA port */ + [0] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [1] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [2] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [3] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [4] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [5] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + [6] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, + [7] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + /* BB port */ + [8] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [9] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + /* CC port */ + [10] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [11] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [12] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [13] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [14] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + [15] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [16] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [17] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* DD port */ + [18] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [19] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [20] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [21] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [22] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [23] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [24] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [25] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* EE port */ + [26] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [27] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [28] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [29] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, +}; + +static const struct tegra_hte_line_mapped tegra264_aon_gpio_sec_map[] =3D { + /* gpio, slice, bit_index */ + /* AA port */ + [0] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [1] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [2] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [3] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [4] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [5] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + [6] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, + [7] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + /* BB port */ + [8] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [9] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [10] =3D {NV_AON_SLICE_INVALID, 0}, + [11] =3D {NV_AON_SLICE_INVALID, 0}, + [12] =3D {NV_AON_SLICE_INVALID, 0}, + [13] =3D {NV_AON_SLICE_INVALID, 0}, + [14] =3D {NV_AON_SLICE_INVALID, 0}, + [15] =3D {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [17] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [18] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [19] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [20] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + [21] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [22] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [23] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* DD port */ + [24] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [25] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [26] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [27] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [28] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [29] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [30] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [31] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* EE port */ + [32] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [33] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [34] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [35] =3D {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [36] =3D {NV_AON_SLICE_INVALID, 0}, + [37] =3D {NV_AON_SLICE_INVALID, 0}, + [38] =3D {NV_AON_SLICE_INVALID, 0}, + [39] =3D {NV_AON_SLICE_INVALID, 0}, +}; + static const struct tegra_hte_data t194_aon_hte =3D { .map_sz =3D ARRAY_SIZE(tegra194_aon_gpio_map), .map =3D tegra194_aon_gpio_map, @@ -324,6 +415,8 @@ static const struct tegra_hte_data t194_aon_hte =3D { .sec_map =3D tegra194_aon_gpio_sec_map, .type =3D HTE_TEGRA_TYPE_GPIO, .slices =3D 3, + .tsc_clkrate_hz =3D HTE_TS_CLK_RATE_HZ, + .tsc_clkrate_ns =3D HTE_CLK_RATE_NS, }; =20 static const struct tegra_hte_data t234_aon_hte =3D { @@ -333,6 +426,19 @@ static const struct tegra_hte_data t234_aon_hte =3D { .sec_map =3D tegra234_aon_gpio_sec_map, .type =3D HTE_TEGRA_TYPE_GPIO, .slices =3D 3, + .tsc_clkrate_hz =3D HTE_TS_CLK_RATE_HZ, + .tsc_clkrate_ns =3D HTE_CLK_RATE_NS, +}; + +static const struct tegra_hte_data t264_aon_hte =3D { + .map_sz =3D ARRAY_SIZE(tegra264_aon_gpio_map), + .map =3D tegra264_aon_gpio_map, + .sec_map_sz =3D ARRAY_SIZE(tegra264_aon_gpio_sec_map), + .sec_map =3D tegra264_aon_gpio_sec_map, + .type =3D HTE_TEGRA_TYPE_GPIO, + .slices =3D 4, + .tsc_clkrate_hz =3D HTE_TS_CLK_RATE_1G, + .tsc_clkrate_ns =3D HTE_CLK_RATE_NS_1G, }; =20 static const struct tegra_hte_data t194_lic_hte =3D { @@ -340,6 +446,8 @@ static const struct tegra_hte_data t194_lic_hte =3D { .map =3D NULL, .type =3D HTE_TEGRA_TYPE_LIC, .slices =3D 11, + .tsc_clkrate_hz =3D HTE_TS_CLK_RATE_HZ, + .tsc_clkrate_ns =3D HTE_CLK_RATE_NS, }; =20 static const struct tegra_hte_data t234_lic_hte =3D { @@ -347,6 +455,17 @@ static const struct tegra_hte_data t234_lic_hte =3D { .map =3D NULL, .type =3D HTE_TEGRA_TYPE_LIC, .slices =3D 17, + .tsc_clkrate_hz =3D HTE_TS_CLK_RATE_HZ, + .tsc_clkrate_ns =3D HTE_CLK_RATE_NS, +}; + +static const struct tegra_hte_data t264_lic_hte =3D { + .map_sz =3D 0, + .map =3D NULL, + .type =3D HTE_TEGRA_TYPE_LIC, + .slices =3D 10, + .tsc_clkrate_hz =3D HTE_TS_CLK_RATE_1G, + .tsc_clkrate_ns =3D HTE_CLK_RATE_NS_1G, }; =20 static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -574,12 +693,12 @@ static int tegra_hte_release(struct hte_chip *chip, s= truct hte_ts_desc *desc, static int tegra_hte_clk_src_info(struct hte_chip *chip, struct hte_clk_info *ci) { - (void)chip; + struct tegra_hte_soc *hte_dev =3D chip->data; =20 if (!ci) return -EINVAL; =20 - ci->hz =3D HTE_TS_CLK_RATE_HZ; + ci->hz =3D hte_dev->prov_data->tsc_clkrate_hz; ci->type =3D CLOCK_MONOTONIC; =20 return 0; @@ -602,8 +721,10 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *= gs) { u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; u64 tsc; + u8 tsc_ns_shift; struct hte_ts_data el; =20 + tsc_ns_shift =3D __builtin_ctz(gs->prov_data->tsc_clkrate_ns); while ((tegra_hte_readl(gs, HTE_TESTATUS) >> HTE_TESTATUS_OCCUPANCY_SHIFT) & HTE_TESTATUS_OCCUPANCY_MASK) { @@ -621,7 +742,7 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *g= s) while (acv) { bit_index =3D __builtin_ctz(acv); line_id =3D bit_index + (slice << 5); - el.tsc =3D tsc << HTE_TS_NS_SHIFT; + el.tsc =3D tsc << tsc_ns_shift; el.raw_level =3D tegra_hte_get_level(gs, line_id); hte_push_ts_ns(gs->chip, line_id, &el); acv &=3D ~BIT(bit_index); @@ -656,6 +777,8 @@ static const struct of_device_id tegra_hte_of_match[] = =3D { { .compatible =3D "nvidia,tegra194-gte-aon", .data =3D &t194_aon_hte}, { .compatible =3D "nvidia,tegra234-gte-lic", .data =3D &t234_lic_hte}, { .compatible =3D "nvidia,tegra234-gte-aon", .data =3D &t234_aon_hte}, + { .compatible =3D "nvidia,tegra264-gte-lic", .data =3D &t264_lic_hte}, + { .compatible =3D "nvidia,tegra264-gte-aon", .data =3D &t264_aon_hte}, { } }; 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Wed, 1 Apr 2026 14:39:02 -0700 From: Suneel Garapati To: , , , , , , , , , , , , , CC: Suneel Garapati Subject: [PATCH 3/3] arm64: tegra: Add GTE nodes for Tegra264 Date: Wed, 1 Apr 2026 21:38:31 +0000 Message-ID: <20260401213831.187569-4-suneelg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260401213831.187569-1-suneelg@nvidia.com> References: <20260401213831.187569-1-suneelg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|SN7PR12MB7787:EE_ X-MS-Office365-Filtering-Correlation-Id: ec806936-81d4-45b2-5fd8-08de9037227d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|921020|18002099003|22082099003|56012099003; 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charset="utf-8" Add AON GPIO and system LIC GTE instances for Tegra264. Signed-off-by: Suneel Garapati --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 06d8357bdf52..c6630733d5e3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3207,6 +3207,15 @@ agic_page5: interrupt-controller@99b0000 { }; }; =20 + hte_lic: hardware-timestamp@8380000 { + compatible =3D "nvidia,tegra264-gte-lic"; + reg =3D <0x0 0x08380000 0x0 0x10000>; + interrupts =3D ; + nvidia,int-threshold =3D <1>; + #timestamp-cells =3D <1>; + status =3D "disabled"; + }; + gpcdma: dma-controller@8400000 { compatible =3D "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; reg =3D <0x0 0x08400000 0x0 0x210000>; @@ -3267,6 +3276,16 @@ hsp_top: hsp@8800000 { #mbox-cells =3D <2>; }; =20 + hte_aon: hardware-timestamp@c2b0000 { + compatible =3D "nvidia,tegra264-gte-aon"; + reg =3D <0x0 0x0c2b0000 0x0 0x10000>; + interrupts =3D ; + nvidia,int-threshold =3D <1>; + #timestamp-cells =3D <1>; + nvidia,gpio-controller =3D <&gpio_aon>; + status =3D "disabled"; + }; + rtc: rtc@c2c0000 { compatible =3D "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; reg =3D <0x0 0x0c2c0000 0x0 0x10000>; --=20 2.34.1