From nobody Wed Apr 1 20:37:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DBC7407117; Wed, 1 Apr 2026 12:26:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775046419; cv=none; b=bpmZ648hYgkEcu6VBiLjlhtr78Nh8KkOBHoNYFjIKcMUcQl3PO0CwAhRsKVLyHGoi9Z7xPQQKHahuG/Hf9aT6Z7f1mLThODA3OEFmPayVYi22zbLIp3VmVzUOHLf06erv/rH4gB3yfYwyBlmMe/yA3Lpld7r2mgQpGhFVCahGIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775046419; c=relaxed/simple; bh=hhR0AwqlgiWjVsLul/aIrHyC7IkMxpfWMhYMiXXBX1s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TyoDdw6slKQgjGior/qvDMnO9WsmkFGzKDRBfYdURlx1FwKVYuE9D+QwVmZl3j6d1Tt02N4qoevbDVUnIA7Ga6h17MP4rAW7+YtgbPneHkCpKAUNtbPt03FPsprt2WH7Z9P1nIrZg83Vaxflyf9V+x3ufrVZ+hYAPW+4sJzLO6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=egpfurwG; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="egpfurwG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775046417; x=1806582417; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hhR0AwqlgiWjVsLul/aIrHyC7IkMxpfWMhYMiXXBX1s=; b=egpfurwGiblTsW71SG1zcuanhw7GoIOdFK6O8Dd0qA3a2Ksu5uXDhwXv TaEE/T/Ppo6ZImyN54y79SAJ5qFclWRwjaISAr4Ea/NTkVxlYOJb9eD8x rWm4Ep7pnT2lPCSV62wyntjfqB96IOsA/aLRomyziJwrnqYiTMOa95Thv s0qYbvqEpWNT+aurfFp/OUjegSlQgSD/iOBP460oENkJi8aTG18MgZIEM HAxs9J8vYB84GXEDQ9w1xNz82o0c4GDyXxKuBLuuqTWnzauaNLO7ESHHd W2yfPD0Az4+I3tq8Ks9LQKLlt1SbProE/B9ordQArSj8CZNF30jd0p/De Q==; X-CSE-ConnectionGUID: qDNLWZJcQm2yy+u0K7VCuw== X-CSE-MsgGUID: lvYrhd0NQwGFNDAKztxuqw== X-IronPort-AV: E=McAfee;i="6800,10657,11745"; a="79936878" X-IronPort-AV: E=Sophos;i="6.23,153,1770624000"; d="scan'208";a="79936878" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2026 05:26:57 -0700 X-CSE-ConnectionGUID: xDcrzh2xRZ2vHBea7B/Elw== X-CSE-MsgGUID: UOWRTasVRJOch/mQxDWMuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,153,1770624000"; d="scan'208";a="249698780" Received: from intel-nuc8i7beh.iind.intel.com ([10.223.163.35]) by fmviesa002.fm.intel.com with ESMTP; 01 Apr 2026 05:26:54 -0700 From: Arun T To: arun.t@intel.com, johannes.goede@oss.qualcomm.com Cc: sakari.ailus@linux.intel.com, arec.kao@intel.com, ilpo.jarvinen@linux.intel.com, dan.scally@ideasonboard.com, platform-driver-x86@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, mehdi.djait@intel.com Subject: [PATCH v7 1/2] platform/x86: int3472: Add TPS68470 board data for Intel nvl Date: Wed, 1 Apr 2026 17:50:29 +0530 Message-ID: <20260401122030.3955499-2-arun.t@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260401122030.3955499-1-arun.t@intel.com> References: <20260401122030.3955499-1-arun.t@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel NVL platform uses IPU8 is powered by a TPS68470 PMIC,requiring bo= ard data to configure the GPIOs and regulators for proper camera sensor operati= on. Signed-off-by: Arun T Reviewed-by: Daniel Scally Reviewed-by: Sakari Ailus Reviewed-by: Hans de Goede --- .../x86/intel/int3472/tps68470_board_data.c | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/platform/x86/intel/int3472/tps68470_board_data.c b/dri= vers/platform/x86/intel/int3472/tps68470_board_data.c index 6bec5a910396..bfec0f1af065 100644 --- a/drivers/platform/x86/intel/int3472/tps68470_board_data.c +++ b/drivers/platform/x86/intel/int3472/tps68470_board_data.c @@ -144,6 +144,24 @@ static struct regulator_consumer_supply int3479_aux2_c= onsumer_supplies[] =3D { REGULATOR_SUPPLY("dovdd", "i2c-INT3479:00"), }; =20 +/* Settings for Intel NVL platform */ + +static struct regulator_consumer_supply ovti13b1_core_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("dvdd", "i2c-OVTI13B1:01"), +}; + +static struct regulator_consumer_supply ovti13b1_ana_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("avdd", "i2c-OVTI13B1:01"), +}; + +static struct regulator_consumer_supply ovti13b1_vcm_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("vcc", "i2c-OVTI13B1:01-VCM"), +}; + +static struct regulator_consumer_supply ovti13b1_vsio_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("dovdd", "i2c-OVTI13B1:01"), +}; + static const struct regulator_init_data dell_7212_tps68470_core_reg_init_d= ata =3D { .constraints =3D { .min_uV =3D 1200000, @@ -221,6 +239,61 @@ static const struct regulator_init_data dell_7212_tps6= 8470_aux2_reg_init_data =3D .consumer_supplies =3D int3479_aux2_consumer_supplies, }; =20 +static const struct regulator_init_data intel_nvl_tps68470_core_reg_init_d= ata =3D { + .constraints =3D { + .min_uV =3D 1200000, + .max_uV =3D 1200000, + .apply_uV =3D true, + .valid_ops_mask =3D REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies =3D ARRAY_SIZE(ovti13b1_core_consumer_supplies), + .consumer_supplies =3D ovti13b1_core_consumer_supplies, +}; + +static const struct regulator_init_data intel_nvl_tps68470_ana_reg_init_da= ta =3D { + .constraints =3D { + .min_uV =3D 2815200, + .max_uV =3D 2815200, + .apply_uV =3D true, + .valid_ops_mask =3D REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies =3D ARRAY_SIZE(ovti13b1_ana_consumer_supplies), + .consumer_supplies =3D ovti13b1_ana_consumer_supplies, +}; + +static const struct regulator_init_data intel_nvl_tps68470_vcm_reg_init_da= ta =3D { + .constraints =3D { + .min_uV =3D 2815200, + .max_uV =3D 2815200, + .apply_uV =3D true, + .valid_ops_mask =3D REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies =3D ARRAY_SIZE(ovti13b1_vcm_consumer_supplies), + .consumer_supplies =3D ovti13b1_vcm_consumer_supplies, +}; + +/* Ensure the always-on VIO regulator has the same voltage as VSIO */ +static const struct regulator_init_data intel_nvl_tps68470_vio_reg_init_da= ta =3D { + .constraints =3D { + .min_uV =3D 1800600, + .max_uV =3D 1800600, + .apply_uV =3D true, + .always_on =3D true, + }, +}; + +static const struct regulator_init_data intel_nvl_tps68470_vsio_reg_init_d= ata =3D { + .constraints =3D { + .min_uV =3D 1800600, + .max_uV =3D 1800600, + .apply_uV =3D true, + .valid_ops_mask =3D REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies =3D ARRAY_SIZE(ovti13b1_vsio_consumer_supplies), + .consumer_supplies =3D ovti13b1_vsio_consumer_supplies, +}; + + static const struct tps68470_regulator_platform_data dell_7212_tps68470_pd= ata =3D { .reg_init_data =3D { [TPS68470_CORE] =3D &dell_7212_tps68470_core_reg_init_data, @@ -297,6 +370,16 @@ static const struct tps68470_regulator_platform_data m= si_p14_ai_evo_tps68470_pda }, }; =20 +static const struct tps68470_regulator_platform_data intel_nvl_tps68470_pd= ata =3D { + .reg_init_data =3D { + [TPS68470_CORE] =3D &intel_nvl_tps68470_core_reg_init_data, + [TPS68470_ANA] =3D &intel_nvl_tps68470_ana_reg_init_data, + [TPS68470_VCM] =3D &intel_nvl_tps68470_vcm_reg_init_data, + [TPS68470_VIO] =3D &intel_nvl_tps68470_vio_reg_init_data, + [TPS68470_VSIO] =3D &intel_nvl_tps68470_vsio_reg_init_data, + }, +}; + static struct gpiod_lookup_table surface_go_int347a_gpios =3D { .dev_id =3D "i2c-INT347A:00", .table =3D { @@ -340,6 +423,14 @@ static const struct software_node msi_p14_ai_evo_tps68= 470_gpio_swnode =3D { .properties =3D msi_p14_ai_evo_gpio_props, }; =20 +static struct gpiod_lookup_table intel_nvl_tps68470_gpios =3D { + .dev_id =3D "i2c-OVTI13B1:01", + .table =3D { + GPIO_LOOKUP("tps68470-gpio", 9, "reset", GPIO_ACTIVE_LOW), + { } + } +}; + static const struct int3472_tps68470_board_data surface_go_tps68470_board_= data =3D { .dev_name =3D "i2c-INT3472:05", .tps68470_regulator_pdata =3D &surface_go_tps68470_pdata, @@ -379,6 +470,15 @@ static const struct int3472_tps68470_board_data msi_p1= 4_ai_evo_tps68470_board_da }, }; =20 +static const struct int3472_tps68470_board_data intel_nvl_tps68470_board_d= ata =3D { + .dev_name =3D "i2c-INT3472:04", + .tps68470_regulator_pdata =3D &intel_nvl_tps68470_pdata, + .n_gpiod_lookups =3D 1, + .tps68470_gpio_lookup_tables =3D { + &intel_nvl_tps68470_gpios, + }, +}; + static const struct dmi_system_id int3472_tps68470_board_data_table[] =3D { { .matches =3D { @@ -415,6 +515,14 @@ static const struct dmi_system_id int3472_tps68470_boa= rd_data_table[] =3D { }, .driver_data =3D (void *)&msi_p14_ai_evo_tps68470_board_data, }, + { + .matches =3D { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Nova Lake Client Platform"), + }, + .driver_data =3D (void *)&intel_nvl_tps68470_board_data, + }, + { } }; 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X-CSE-ConnectionGUID: p6yrF4KDQBiuAzFvniYD0Q== X-CSE-MsgGUID: LObQCt7IQYWpnrlxSGpKkw== X-IronPort-AV: E=McAfee;i="6800,10657,11745"; a="79936882" X-IronPort-AV: E=Sophos;i="6.23,153,1770624000"; d="scan'208";a="79936882" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2026 05:27:01 -0700 X-CSE-ConnectionGUID: 7BJoRhusR8CZ7IuqAt0b8g== X-CSE-MsgGUID: b6bcucmiR7KUR77KHstcwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,153,1770624000"; d="scan'208";a="249698784" Received: from intel-nuc8i7beh.iind.intel.com ([10.223.163.35]) by fmviesa002.fm.intel.com with ESMTP; 01 Apr 2026 05:26:58 -0700 From: Arun T To: arun.t@intel.com, johannes.goede@oss.qualcomm.com Cc: sakari.ailus@linux.intel.com, arec.kao@intel.com, ilpo.jarvinen@linux.intel.com, dan.scally@ideasonboard.com, platform-driver-x86@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, mehdi.djait@intel.com Subject: [PATCH v7 2/2] media: ov13b10: Support multiple regulators Date: Wed, 1 Apr 2026 17:50:30 +0530 Message-ID: <20260401122030.3955499-3-arun.t@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260401122030.3955499-1-arun.t@intel.com> References: <20260401122030.3955499-1-arun.t@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The OV13B10 sensor driver currently handles a single regulator called avdd, however the sensor can be supplied by up to three regulators. Update the driver to handle all of them together using the regulator bulk API. Signed-off-by: Arun T Reviewed-by: Daniel Scally Reviewed-by: Sakari Ailus Reviewed-by: Hans de Goede #include #include +#include #include #include #include @@ -699,6 +700,12 @@ static const struct ov13b10_mode supported_2_lanes_mod= es[] =3D { }, }; =20 +static const char * const ov13b10_supply_names[] =3D { + "dovdd", /* Digital I/O power */ + "avdd", /* Analog power */ + "dvdd", /* Digital core power */ +}; + struct ov13b10 { struct device *dev; =20 @@ -708,7 +715,7 @@ struct ov13b10 { struct v4l2_ctrl_handler ctrl_handler; =20 struct clk *img_clk; - struct regulator *avdd; + struct regulator_bulk_data supplies[ARRAY_SIZE(ov13b10_supply_names)]; struct gpio_desc *reset; =20 /* V4L2 Controls */ @@ -1194,9 +1201,8 @@ static int ov13b10_power_off(struct device *dev) struct ov13b10 *ov13b10 =3D to_ov13b10(sd); =20 gpiod_set_value_cansleep(ov13b10->reset, 1); - - if (ov13b10->avdd) - regulator_disable(ov13b10->avdd); + regulator_bulk_disable(ARRAY_SIZE(ov13b10_supply_names), + ov13b10->supplies); =20 clk_disable_unprepare(ov13b10->img_clk); =20 @@ -1214,14 +1220,12 @@ static int ov13b10_power_on(struct device *dev) dev_err(dev, "failed to enable imaging clock: %d", ret); return ret; } - - if (ov13b10->avdd) { - ret =3D regulator_enable(ov13b10->avdd); - if (ret < 0) { - dev_err(dev, "failed to enable avdd: %d", ret); - clk_disable_unprepare(ov13b10->img_clk); - return ret; - } + ret =3D regulator_bulk_enable(ARRAY_SIZE(ov13b10_supply_names), + ov13b10->supplies); + if (ret < 0) { + dev_err(dev, "failed to enable regulators\n"); + clk_disable_unprepare(ov13b10->img_clk); + return ret; } =20 gpiod_set_value_cansleep(ov13b10->reset, 0); @@ -1475,7 +1479,8 @@ static int ov13b10_get_pm_resources(struct ov13b10 *o= v13b) unsigned long freq; int ret; =20 - ov13b->reset =3D devm_gpiod_get_optional(ov13b->dev, "reset", GPIOD_OUT_L= OW); + ov13b->reset =3D devm_gpiod_get_optional(ov13b->dev, "reset", + GPIOD_OUT_LOW); if (IS_ERR(ov13b->reset)) return dev_err_probe(ov13b->dev, PTR_ERR(ov13b->reset), "failed to get reset gpio\n"); @@ -1491,15 +1496,15 @@ static int ov13b10_get_pm_resources(struct ov13b10 = *ov13b) "external clock %lu is not supported\n", freq); =20 - ov13b->avdd =3D devm_regulator_get_optional(ov13b->dev, "avdd"); - if (IS_ERR(ov13b->avdd)) { - ret =3D PTR_ERR(ov13b->avdd); - ov13b->avdd =3D NULL; - if (ret !=3D -ENODEV) - return dev_err_probe(ov13b->dev, ret, - "failed to get avdd regulator\n"); - } + for (unsigned int i =3D 0; i < ARRAY_SIZE(ov13b10_supply_names); i++) + ov13b->supplies[i].supply =3D ov13b10_supply_names[i]; =20 + ret =3D devm_regulator_bulk_get(ov13b->dev, + ARRAY_SIZE(ov13b10_supply_names), + ov13b->supplies); + if (ret) + return dev_err_probe(ov13b->dev, ret, + "failed to get regulators\n"); return 0; } =20 --=20 2.43.0