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Tue, 31 Mar 2026 17:39:40 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 07/10] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15% Date: Tue, 31 Mar 2026 17:39:05 -0700 Message-ID: <20260401003908.3438-8-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 1ae45b5d4f371af8ae51a3827d0ec9fe27eeb867 ] Adjust the nominal (and performance) clocks for DCE 8-10, and set them to 625 MHz, which is the value used by the legacy display code in amdgpu_atombios_get_clock_info. This was tested with Hawaii, Tonga and Fiji. These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz. The extra 15% clock was added as a workaround for a Polaris issue which uses DCE 11, and should not have been used on DCE 8-10 which are already hardcoded to the highest possible display clock. Unfortunately, the extra 15% was mistakenly copied and kept even on code paths which don't affect Polaris. This commit fixes that and also adds a check to make sure not to exceed the maximum DCE 8-10 display clock. Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") Signed-off-by: Timur Krist=C3=B3f Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 5dbe89d9b72d..6131ede2db7a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks= _by_state[] =3D { /* ClocksStateLow */ { .display_clk_khz =3D 352000, .pixel_clk_khz =3D 330000}, /* ClocksStateNominal */ -{ .display_clk_khz =3D 600000, .pixel_clk_khz =3D 400000 }, +{ .display_clk_khz =3D 625000, .pixel_clk_khz =3D 400000 }, /* ClocksStatePerformance */ -{ .display_clk_khz =3D 600000, .pixel_clk_khz =3D 400000 } }; +{ .display_clk_khz =3D 625000, .pixel_clk_khz =3D 400000 } }; =20 int dentist_get_divider_from_did(int did) { @@ -403,11 +403,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_= base, { struct clk_mgr_internal *clk_mgr_dce =3D TO_CLK_MGR_INTERNAL(clk_mgr_base= ); struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk =3D context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk =3D patched_disp_clk * 115 / 100; + const int max_disp_clk =3D + clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_c= lk_khz; + int patched_disp_clk =3D MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk= _khz); =20 level_change_req.power_level =3D dce_get_required_clocks_state(clk_mgr_ba= se, context); /* get max clock state from PPLIB */ --=20 2.53.0