From nobody Wed Apr 1 10:26:58 2026 Received: from mail-dy1-f178.google.com (mail-dy1-f178.google.com [74.125.82.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E81F1DE4E0 for ; Wed, 1 Apr 2026 00:39:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775003978; cv=none; b=IZtRGfA3an73ORu7JaCcOMd8+cXgymODp3Ew+YzIuKdXLYB6OQD9bCzAmKvET6v3fcFXX3aAkVYPEKy3gY1QaEQzcwDpGLRIBMVXfga0KnGXNh0s1fd4bHwUnXBKN9q3a2Dd2/B7D8Dk/K6z9sc9lcFYybygyyshaNO6p9AT9jE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775003978; c=relaxed/simple; bh=KDqNex0SrS190A1ilN+y9+8TCpjpm9vndDHmyB+HvwU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KLFJG11GL1HEnlfUHA9qRjwRnjfKeNk2sURESDo71Zz088X0jbaWMZx21+FO9G5zDpdeDkUcj5tSO/iA2TJtaol4AMrRVt9OCByFFyhi3AlXFoj5Qoup9p8HQMtiJ6TNCF6Xum5MNCFu3Gx2QFAD11zniO6IjaaRXfmwXs45CXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WuHYvza4; arc=none smtp.client-ip=74.125.82.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WuHYvza4" Received: by mail-dy1-f178.google.com with SMTP id 5a478bee46e88-2bd9a485bd6so12339473eec.1 for ; Tue, 31 Mar 2026 17:39:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775003976; x=1775608776; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fYskpQzDXhxM4+9VM9RgZDo2+o/dM3+zNnNFKoGgds4=; b=WuHYvza4RotaY3Pq3Sh4dZjS4UrkvwiZHbZqPVHQ5ow0t0V54IV5lP1Qom2k7XIWzw dwlu729N/SdK3J6ByO4NWQb/nuTtUCOhE7ywyWBLcoUr1DvH32ntEjEvyevsmGAvxqfj IH09/URmAIgH5MtG3qYaWhtQwkWamXB+Zjx12r9hNtrM2v0+TdLUHuIBQHho+SnH9TTn hhwrDTZwbyQUYM73RPcxhirPjG/nyPZy1WNabaP3+xt6S8l78zPmt1TGRe/3gcvvxA+K xlAwlpuC7A7LrQFYcH2HW0mgkxiEg2zv4PQfiR+fLq3LiQ+tarcwlSlCg0eixPdR9OSG 8/qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775003976; x=1775608776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fYskpQzDXhxM4+9VM9RgZDo2+o/dM3+zNnNFKoGgds4=; b=HyDyMVjyy5G8rvjFR5IgtzR6kjWAeQKpYuxG1Is0RPF8YXxpAk+AsAfMYeUwiYSqCk i2yvpFBFVCduV6lJjM4w5HQJXEDLp+xlEdC00RJt1/Hw/pypeSksWM6xIq0ZAoLSA6wN vXGj5WJKX2QNd15/r8OaJ+jAlwugPFweW0rYnxuRoxJwx1vRCYa6SQTjjfnxkPlix7yP kUlymyqJSGUJ68MNfSkdWprmRyDwO3NZBNGPkt8WImDP9uZBiNAJpokmaSlEvXJxOahV 0HIEGfM/iphteC0v1NfQKE/EdDkX7NdCR3dG/R+S010bOIGLd946R6P85WRcfBc9ce4R ZGkg== X-Forwarded-Encrypted: i=1; AJvYcCWtBsdDs340bCQ3ahqMoP5hZYXbwkjwRyaDKMktG2wR2I1uZnDZVlufJdSx1ZjrOoxmaz6QFj5M9W2JRT4=@vger.kernel.org X-Gm-Message-State: AOJu0Yya8m6q2bGU5X92HfG9GuYHS0Yqlt9kkjC5yAZ7REkMZFpQk9lc omh9erPS0uTnjMwW98aSjWEWiNcV951q915Cw1+jY/qQg2IlmjZ/Al9c X-Gm-Gg: ATEYQzyphvnSnO6d6hrEjC5WS3GxhTKAoCscWiJu9lswPltuLuNn+wjdsIu4E0UYelo yCAsEBsGfS6STlj+k7M8WgeVVn2OX9kmkHcTQ6OskCZAlS0z4JcFciOeOKd0DVsGFJmMTWuBjKv /l97+Hg5nNe+cqydlzacnqAPsUG1HfcX2ABPEiizsMVzu/jUjAVlFL/OBHpZpOATv8QbUhq4elJ g2RCXIn22NPrgVzB3gMAtQr2N1rYCitjOwEFvUJ7ScTsjlVMq2O5qBVPKGfpM8YWd+9mWULKMUF I8F38w+O+SAQBaZKKX/y8KxxOl/IQM1uvfkjNq/onH7oPnHmv+MH3pigS3+KSsjrClDo3Yp3mY6 bfig2dIdWDqmLxudag7cm46mpdIVC7qVtrAbDUpwuXnVnG+mcnhkqdaHFDz4i4Jh5YikH+6bC82 d4H3PWBgSfaEVbh3leewd35UehxX+2pdVzoecjdcRUedAzHCeuz8DdV/Y= X-Received: by 2002:a05:7300:ed0e:b0:2b9:80c1:bb5 with SMTP id 5a478bee46e88-2c9337a0ef3mr1033986eec.33.1775003975796; Tue, 31 Mar 2026 17:39:35 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c3bd9894sm11543019eec.4.2026.03.31.17.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 17:39:35 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 04/10] drm/amd/display: Reject modes with too high pixel clock on DCE6-10 Date: Tue, 31 Mar 2026 17:39:02 -0700 Message-ID: <20260401003908.3438-5-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 118800b0797a046adaa2a8e9dee9b971b78802a7 ] Reject modes with a pixel clock higher than the maximum display clock. Use 400 MHz as a fallback value when the maximum display clock is not known. Pixel clocks that are higher than the display clock just won't work and are not supported. With the addition of the YUV422 fallback, DC can now accidentally select a mode requiring higher pixel clock than actually supported when the DP version supports the required bandwidth but the clock is otherwise too high for the display engine. DCE 6-10 don't support these modes but they don't have a bandwidth calculation to reject them properly. Fixes: db291ed1732e ("drm/amd/display: Add fallback path for YCBCR422") Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 3 +++ .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 10 +++++++++- .../amd/display/dc/resource/dce100/dce100_resource.c | 10 +++++++++- .../drm/amd/display/dc/resource/dce80/dce80_resource.c | 10 +++++++++- 5 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index b268c367c27c..a2e100aa3cba 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -460,6 +460,9 @@ void dce_clk_mgr_construct( clk_mgr->max_clks_state =3D DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr->cur_min_clks_state =3D DM_PP_CLOCKS_STATE_INVALID; =20 + base->clks.max_supported_dispclk_khz =3D + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_k= hz; + dce_clock_read_integrated_info(clk_mgr); dce_clock_read_ss_info(clk_mgr); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b= /drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index a39641a0ff09..69dd80d9f738 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -147,6 +147,8 @@ void dce60_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) { + struct clk_mgr *base =3D &clk_mgr->base; + dce_clk_mgr_construct(ctx, clk_mgr); =20 memcpy(clk_mgr->max_clks_by_state, @@ -157,5 +159,8 @@ void dce60_clk_mgr_construct( clk_mgr->clk_mgr_shift =3D &disp_clk_shift; clk_mgr->clk_mgr_mask =3D &disp_clk_mask; clk_mgr->base.funcs =3D &dce60_funcs; + + base->clks.max_supported_dispclk_khz =3D + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_k= hz; } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 8db9f7514466..7886a2a55caf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -34,6 +34,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce60/irq_service_dce60.h" #include "dce110/dce110_timing_generator.h" @@ -870,10 +871,17 @@ static bool dce60_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource= .c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 53a5f4cb648c..6717ed84a032 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -29,6 +29,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" @@ -843,10 +844,17 @@ static bool dce100_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c= b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index a73d3c6ef425..af4a45718c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -32,6 +32,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce80/irq_service_dce80.h" #include "dce110/dce110_timing_generator.h" @@ -876,10 +877,17 @@ static bool dce80_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { --=20 2.53.0