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Tue, 31 Mar 2026 17:39:29 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 01/10] drm/amd/amdgpu: decouple ASPM with pcie dpm Date: Tue, 31 Mar 2026 17:38:59 -0700 Message-ID: <20260401003908.3438-2-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kenneth Feng [ Upstream commit df0e722fbdbedb6f2b682dc2fad9e0c221e3622d ] ASPM doesn't need to be disabled if pcie dpm is disabled. So ASPM can be independantly enabled. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index d5e6d5ec69c8..dbee43c58741 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1782,8 +1782,6 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_devi= ce *adev) } if (adev->flags & AMD_IS_APU) return false; - if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) - return false; return pcie_aspm_enabled(adev->pdev); } =20 --=20 2.53.0 From nobody Wed Apr 1 09:00:07 2026 Received: from mail-dy1-f178.google.com (mail-dy1-f178.google.com [74.125.82.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30AA81A9F87 for ; Wed, 1 Apr 2026 00:39:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Kenneth Feng [ Upstream commit c770ef19673fb1defcbde2ee2b91c3c89bfcf164 ] disable ASPM with some ASICs on some specific platforms. required from PCIe controller owner. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index dbee43c58741..eb3c6bfe2e6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -84,6 +84,7 @@ =20 #if IS_ENABLED(CONFIG_X86) #include +#include #endif =20 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); @@ -1758,6 +1759,35 @@ static bool amdgpu_device_pcie_dynamic_switching_sup= ported(struct amdgpu_device return true; } =20 +static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev) +{ +#if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c =3D &cpu_data(0); + + if (!(amdgpu_ip_version(adev, GC_HWIP, 0) =3D=3D IP_VERSION(12, 0, 0) || + amdgpu_ip_version(adev, GC_HWIP, 0) =3D=3D IP_VERSION(12, 0, 1))) + return false; + + if (c->x86 =3D=3D 6 && + adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) { + switch (c->x86_model) { + case VFM_MODEL(INTEL_ALDERLAKE): + case VFM_MODEL(INTEL_ALDERLAKE_L): + case VFM_MODEL(INTEL_RAPTORLAKE): + case VFM_MODEL(INTEL_RAPTORLAKE_P): + case VFM_MODEL(INTEL_RAPTORLAKE_S): + return true; + default: + return false; + } + } else { + return false; + } +#else + return false; +#endif +} + /** * amdgpu_device_should_use_aspm - check if the device should program ASPM * @@ -1782,6 +1812,8 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_devi= ce *adev) } if (adev->flags & AMD_IS_APU) return false; + if (amdgpu_device_aspm_support_quirk(adev)) + return false; return pcie_aspm_enabled(adev->pdev); } =20 --=20 2.53.0 From nobody Wed Apr 1 09:00:07 2026 Received: from mail-dy1-f170.google.com (mail-dy1-f170.google.com [74.125.82.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2A9E1E7C12 for ; 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Tue, 31 Mar 2026 17:39:33 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c3bd9894sm11543019eec.4.2026.03.31.17.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 17:39:33 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 03/10] drm/amd/display: Disable fastboot on DCE 6 too Date: Tue, 31 Mar 2026 17:39:01 -0700 Message-ID: <20260401003908.3438-4-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 7495962cbceb967e095233a5673ea71f3bcdee7e ] It already didn't work on DCE 8, so there is no reason to assume it would on DCE 6. Signed-off-by: Timur Krist=C3=B3f Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/dr= ivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index df69e0cebf78..7dc99c85b8ea 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1910,10 +1910,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, s= truct dc_state *context) =20 get_edp_streams(context, edp_streams, &edp_stream_num); =20 - // Check fastboot support, disable on DCE8 because of blank screens - if (edp_num && edp_stream_num && dc->ctx->dce_version !=3D DCE_VERSION_8_= 0 && - dc->ctx->dce_version !=3D DCE_VERSION_8_1 && - dc->ctx->dce_version !=3D DCE_VERSION_8_3) { + /* Check fastboot support, disable on DCE 6-8 because of blank screens */ + if (edp_num && edp_stream_num && dc->ctx->dce_version < DCE_VERSION_10_0)= { for (i =3D 0; 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Tue, 31 Mar 2026 17:39:35 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 04/10] drm/amd/display: Reject modes with too high pixel clock on DCE6-10 Date: Tue, 31 Mar 2026 17:39:02 -0700 Message-ID: <20260401003908.3438-5-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 118800b0797a046adaa2a8e9dee9b971b78802a7 ] Reject modes with a pixel clock higher than the maximum display clock. Use 400 MHz as a fallback value when the maximum display clock is not known. Pixel clocks that are higher than the display clock just won't work and are not supported. With the addition of the YUV422 fallback, DC can now accidentally select a mode requiring higher pixel clock than actually supported when the DP version supports the required bandwidth but the clock is otherwise too high for the display engine. DCE 6-10 don't support these modes but they don't have a bandwidth calculation to reject them properly. Fixes: db291ed1732e ("drm/amd/display: Add fallback path for YCBCR422") Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 3 +++ .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 10 +++++++++- .../amd/display/dc/resource/dce100/dce100_resource.c | 10 +++++++++- .../drm/amd/display/dc/resource/dce80/dce80_resource.c | 10 +++++++++- 5 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index b268c367c27c..a2e100aa3cba 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -460,6 +460,9 @@ void dce_clk_mgr_construct( clk_mgr->max_clks_state =3D DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr->cur_min_clks_state =3D DM_PP_CLOCKS_STATE_INVALID; =20 + base->clks.max_supported_dispclk_khz =3D + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_k= hz; + dce_clock_read_integrated_info(clk_mgr); dce_clock_read_ss_info(clk_mgr); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b= /drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index a39641a0ff09..69dd80d9f738 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -147,6 +147,8 @@ void dce60_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) { + struct clk_mgr *base =3D &clk_mgr->base; + dce_clk_mgr_construct(ctx, clk_mgr); =20 memcpy(clk_mgr->max_clks_by_state, @@ -157,5 +159,8 @@ void dce60_clk_mgr_construct( clk_mgr->clk_mgr_shift =3D &disp_clk_shift; clk_mgr->clk_mgr_mask =3D &disp_clk_mask; clk_mgr->base.funcs =3D &dce60_funcs; + + base->clks.max_supported_dispclk_khz =3D + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_k= hz; } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 8db9f7514466..7886a2a55caf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -34,6 +34,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce60/irq_service_dce60.h" #include "dce110/dce110_timing_generator.h" @@ -870,10 +871,17 @@ static bool dce60_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource= .c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 53a5f4cb648c..6717ed84a032 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -29,6 +29,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" @@ -843,10 +844,17 @@ static bool dce100_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c= b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index a73d3c6ef425..af4a45718c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -32,6 +32,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce80/irq_service_dce80.h" #include "dce110/dce110_timing_generator.h" @@ -876,10 +877,17 @@ static bool dce80_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; 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Tue, 31 Mar 2026 17:39:37 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 05/10] drm/amd/display: Keep PLL0 running on DCE 6.0 and 6.4 Date: Tue, 31 Mar 2026 17:39:03 -0700 Message-ID: <20260401003908.3438-6-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 0449726b58ea64ec96b95f95944f0a3650204059 ] DC can turn off the display clock when no displays are connected or when all displays are off, for reference see: - dce*_validate_bandwidth DC also assumes that the DP clock is always on and never powers it down, for reference see: - dce110_clock_source_power_down In case of DCE 6.0 and 6.4, PLL0 is the clock source for both the engine clock and DP clock, for reference see: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Therefore, PLL0 should be always kept running on DCE 6.0 and 6.4. This commit achieves that by ensuring that by setting the display clock to the corresponding value in low power state instead of zero. This fixes a page flip timeout on SI with DC which happens when all connected displays are blanked. Signed-off-by: Timur Krist=C3=B3f Reviewed-by: Alex Deucher Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 7886a2a55caf..c4d7fa60d654 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -889,7 +889,16 @@ static bool dce60_validate_bandwidth( context->bw_ctx.bw.dce.dispclk_khz =3D 681000; context->bw_ctx.bw.dce.yclk_khz =3D 250000 * MEMORY_TYPE_MULTIPLIER_CZ; } else { - context->bw_ctx.bw.dce.dispclk_khz =3D 0; + /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and + * the DP clock, and shouldn't be turned off. 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Tue, 31 Mar 2026 17:39:39 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c3bd9894sm11543019eec.4.2026.03.31.17.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 17:39:38 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 06/10] drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming. Date: Tue, 31 Mar 2026 17:39:04 -0700 Message-ID: <20260401003908.3438-7-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 35222b5934ec8d762473592ece98659baf6bc48e ] Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only be used for DP. Make sure to initialize the correct amount of PLLs in DC for these DCE versions and use PLL0 only for DP. Also, on DCE 6.0 and 6.4, the PLL0 needs to be powered on at initialization as opposed to DCE 6.1 and 7.x which use a different clock source for DFS. The following functions were used as reference from the old radeon driver implementation of DCE 6.x: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 5 +++ .../drm/amd/display/dc/dce60/dce60_resource.c | 34 +++++++++++-------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index a2e100aa3cba..5dbe89d9b72d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -245,6 +245,11 @@ int dce_set_clock( pxl_clk_params.target_pixel_clock_100hz =3D requested_clk_khz * 10; pxl_clk_params.pll_id =3D CLOCK_SOURCE_ID_DFS; =20 + /* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */ + if (clk_mgr_base->ctx->dce_version =3D=3D DCE_VERSION_6_0 || + clk_mgr_base->ctx->dce_version =3D=3D DCE_VERSION_6_4) + pxl_clk_params.pll_id =3D CLOCK_SOURCE_ID_PLL0; + if (clk_mgr_dce->dfs_bypass_active) pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS =3D true; =20 diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index c4d7fa60d654..978c024c97ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -374,7 +374,7 @@ static const struct resource_caps res_cap =3D { .num_timing_generator =3D 6, .num_audio =3D 6, .num_stream_encoder =3D 6, - .num_pll =3D 2, + .num_pll =3D 3, .num_ddc =3D 6, }; =20 @@ -390,7 +390,7 @@ static const struct resource_caps res_cap_64 =3D { .num_timing_generator =3D 2, .num_audio =3D 2, .num_stream_encoder =3D 2, - .num_pll =3D 2, + .num_pll =3D 3, .num_ddc =3D 2, }; =20 @@ -990,21 +990,24 @@ static bool dce60_construct( =20 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_= dp !=3D 0) { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, tru= e); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true= ); =20 + /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it h= ere. */ pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs= [0], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); pool->base.clock_sources[1] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [1], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); pool->base.clk_src_count =3D 2; =20 } else { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs= [0], true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[= 0], true); =20 pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [1], false); - pool->base.clk_src_count =3D 1; + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); + pool->base.clock_sources[1] =3D + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); + pool->base.clk_src_count =3D 2; } =20 if (pool->base.dp_clock_source =3D=3D NULL) { @@ -1382,21 +1385,24 @@ static bool dce64_construct( =20 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_= dp !=3D 0) { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, tru= e); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true= ); =20 + /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it h= ere. */ pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [0], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); pool->base.clock_sources[1] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs= [1], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); pool->base.clk_src_count =3D 2; =20 } else { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [0], true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[= 0], true); =20 pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs= [1], false); - pool->base.clk_src_count =3D 1; + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); + pool->base.clock_sources[1] =3D + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); 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Tue, 31 Mar 2026 17:39:40 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 07/10] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15% Date: Tue, 31 Mar 2026 17:39:05 -0700 Message-ID: <20260401003908.3438-8-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 1ae45b5d4f371af8ae51a3827d0ec9fe27eeb867 ] Adjust the nominal (and performance) clocks for DCE 8-10, and set them to 625 MHz, which is the value used by the legacy display code in amdgpu_atombios_get_clock_info. This was tested with Hawaii, Tonga and Fiji. These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz. The extra 15% clock was added as a workaround for a Polaris issue which uses DCE 11, and should not have been used on DCE 8-10 which are already hardcoded to the highest possible display clock. Unfortunately, the extra 15% was mistakenly copied and kept even on code paths which don't affect Polaris. This commit fixes that and also adds a check to make sure not to exceed the maximum DCE 8-10 display clock. Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") Signed-off-by: Timur Krist=C3=B3f Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 5dbe89d9b72d..6131ede2db7a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks= _by_state[] =3D { /* ClocksStateLow */ { .display_clk_khz =3D 352000, .pixel_clk_khz =3D 330000}, /* ClocksStateNominal */ -{ .display_clk_khz =3D 600000, .pixel_clk_khz =3D 400000 }, +{ .display_clk_khz =3D 625000, .pixel_clk_khz =3D 400000 }, /* ClocksStatePerformance */ -{ .display_clk_khz =3D 600000, .pixel_clk_khz =3D 400000 } }; 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Tue, 31 Mar 2026 17:39:42 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c3bd9894sm11543019eec.4.2026.03.31.17.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 17:39:42 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 08/10] drm/amd/display: Disable scaling on DCE6 for now Date: Tue, 31 Mar 2026 17:39:06 -0700 Message-ID: <20260401003908.3438-9-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 0e190a0446ec517666dab4691b296a9b758e590f ] Scaling doesn't work on DCE6 at the moment, the current register programming produces incorrect output when using fractional scaling (between 100-200%) on resolutions higher than 1080p. Disable it until we figure out how to program it properly. Fixes: 7c15fd86aaec ("drm/amd/display: dc/dce: add initial DCE6 support (v1= 0)") Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 978c024c97ba..3f9ea4fdc7d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -404,13 +404,13 @@ static const struct dc_plane_cap plane_cap =3D { }, =20 .max_upscale_factor =3D { - .argb8888 =3D 16000, + .argb8888 =3D 1, .nv12 =3D 1, .fp16 =3D 1 }, =20 .max_downscale_factor =3D { - .argb8888 =3D 250, + .argb8888 =3D 1, .nv12 =3D 1, .fp16 =3D 1 } --=20 2.53.0 From nobody Wed Apr 1 09:00:07 2026 Received: from mail-dl1-f46.google.com (mail-dl1-f46.google.com [74.125.82.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B38E51EBFE0 for ; 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Tue, 31 Mar 2026 17:39:44 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c3bd9894sm11543019eec.4.2026.03.31.17.39.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 17:39:44 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 09/10] drm/amd: Disable ASPM on SI Date: Tue, 31 Mar 2026 17:39:07 -0700 Message-ID: <20260401003908.3438-10-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 7bdd91abf0cb3ea78160e2e78fb58b12f6a38d55 ] Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. It's unclear if this is a platform-specific or GPU-specific issue. Disable ASPM on SI for the time being. Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index eb3c6bfe2e6c..12d7e45a4245 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1761,6 +1761,13 @@ static bool amdgpu_device_pcie_dynamic_switching_sup= ported(struct amdgpu_device =20 static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev) { + /* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. + * It's unclear if this is a platform-specific or GPU-specific issue. + * Disable ASPM on SI for the time being. + */ + if (adev->family =3D=3D AMDGPU_FAMILY_SI) + return true; + #if IS_ENABLED(CONFIG_X86) struct cpuinfo_x86 *c =3D &cpu_data(0); =20 --=20 2.53.0 From nobody Wed Apr 1 09:00:07 2026 Received: from mail-dy1-f180.google.com (mail-dy1-f180.google.com [74.125.82.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 444D91D8E01 for ; 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Tue, 31 Mar 2026 17:39:46 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c3bd9894sm11543019eec.4.2026.03.31.17.39.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 17:39:45 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Ray Wu , Wayne Lin , Mario Limonciello , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 for 6.12 10/10] drm/amd/display: Correct logic check error for fastboot Date: Tue, 31 Mar 2026 17:39:08 -0700 Message-ID: <20260401003908.3438-11-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260401003908.3438-1-rosenp@gmail.com> References: <20260401003908.3438-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Charlene Liu [ Upstream commit b6a65009e7ce3f0cc72da18f186adb60717b51a0 ] [Why] Fix fastboot broken in driver. This is caused by an open source backport change 7495962c. from the comment, the intended check is to disable fastboot for pre-DCN10. but the logic check is reversed, and causes fastboot to be disabled on all DCN10 and after. fastboot is for driver trying to pick up bios used hw setting and bypass reprogramming the hw if dc_validate_boot_timing() condition meets. Fixes: 7495962cbceb ("drm/amd/display: Disable fastboot on DCE 6 too") Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello Reviewed-by: Ovidiu Bunea Signed-off-by: Charlene Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/dr= ivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 7dc99c85b8ea..551638d9ff61 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1910,8 +1910,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, st= ruct dc_state *context) =20 get_edp_streams(context, edp_streams, &edp_stream_num); =20 - /* Check fastboot support, disable on DCE 6-8 because of blank screens */ - if (edp_num && edp_stream_num && dc->ctx->dce_version < DCE_VERSION_10_0)= { + /* Check fastboot support, disable on DCE 6-8-10 because of blank screens= */ + if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0)= { for (i =3D 0; i < edp_num; i++) { edp_link =3D edp_links[i]; if (edp_link !=3D edp_streams[0]->link) --=20 2.53.0