From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39A4E3CF051; Wed, 1 Apr 2026 09:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.37.255.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775035917; cv=none; b=OM/9KZpHFjkBqHWUE/qyxOMU4ZmnJ1k90+mOL+/KGUebL6KEyjtTazBvQbcvHCoS1sSmEeW+qLu020k+a3mhbCJqnusKi//n1JF5heDYCjgP05yS2RVC2Lw0xGYLRifp9ifSeeBfaMs0iB4ReElxsQdZqt85UKvNng/jLH6AiM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775035917; c=relaxed/simple; bh=TNKQcUOxp3IEx4/KXd1OG59UNOtH64WRIf6g/vY5agA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:Cc; b=cBn89uN6DocMG+diaH9Ux12ib2rCVJoMef/iObFJbXeB+ZrfQGHaGVTFIS4ZjyL466F4hmGswJDCfDxKeUM+CVmJ3qTuhRvJUd9SZmKa7hoyG1JP/v68dijiNtYXecIoCC0F8KNUjHaY/uJ0yM/mGz0ucsF1nTFN7QS08KVcY+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de; spf=pass smtp.mailfrom=dev.tdt.de; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b=qQA2uXvN; arc=none smtp.client-ip=194.37.255.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b="qQA2uXvN" Received: from [194.37.255.9] (helo=mxout.expurgate.net) by relay.expurgate.net with smtp (Exim 4.92) (envelope-from ) id 1w7rvM-001Sya-B7; Wed, 01 Apr 2026 11:31:44 +0200 Received: from [195.243.126.94] (helo=securemail.tdt.de) by relay.expurgate.net with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w7rvL-005aF8-PG; Wed, 01 Apr 2026 11:31:43 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de; s=z1-selector1; t=1775035903; bh=E2ZTfUj86mp0drWTHwRl8zkHJBvXCjXQAwVjq3aAu94=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qQA2uXvNovtshODBkmvHejw6K4NByuX/Q+J5ZJw4XrY1c4GLjcIFeCqmL/qB3f0WU Ai57eZFlJeqdjc6fK7147xyW1v/kIT9v3N9fp7GkK/JFu83QtZ77/yjI7FKiFbzVYe Eaed17IDZKufJxLABj/+BNMVKqdBnIt5aycuegC3RrG+KuWal353xbvfMG6eZiYQxu JPBVjvntst1nzk39ApWoCM/okLuvP0UTgyU0DaNaRpv/ga2K3kNxLLCVNrvu9c/Iau 31j27QFVsURANzrAkl4l6MrbZeookchz6epEbxIpyQd8MVcW8zILmtmtq5u3KAi3nf huqI8c0W4zk1g== Received: from securemail.tdt.de (localhost [127.0.0.1]) by securemail.tdt.de (Postfix) with ESMTP id 4FBE0240042; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 4311D240036; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id AF3A623C7E; Wed, 1 Apr 2026 11:31:42 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:37 +0200 Subject: [PATCH v3 1/7] MAINTAINERS: Remove bouncing intel-gw maintainer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260401-pcie-intel-gw-v3-1-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=809; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=TNKQcUOxp3IEx4/KXd1OG59UNOtH64WRIf6g/vY5agA=; b=IMH0r/M4bsdWwt18oZCR5ztzVwjNcLpySPx/xMZk+tPmSJOeeHtuYuxrv9kyuo0fN02eIO+hM +BpnFuKjz6WCcKgsqAUbhPGkPXz5+kP/ak7jTWFhbVuOgpZz56QBjPQ X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-ID: 151534::1775035904-4A7C8233-03B41B9E/0/0 X-purgate: clean X-purgate-type: clean The maintainer's email address has been bouncing for months. Mark the PCI intel-gw driver as orphaned. Signed-off-by: Florian Eckert --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 96ea84948d76aff5e07579911d0f370ae13f481b..26f3b2e192fa9ef2e1c89d2310b= ebaa0a67dff00 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20505,9 +20505,8 @@ F: Documentation/devicetree/bindings/pci/intel,keem= bay-pcie* F: drivers/pci/controller/dwc/pcie-keembay.c =20 PCIE DRIVER FOR INTEL LGM GW SOC -M: Chuanhua Lei L: linux-pci@vger.kernel.org -S: Maintained +S: Orphan F: Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml F: drivers/pci/controller/dwc/pcie-intel-gw.c =20 --=20 2.47.3 From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C8AF3C73EE; Wed, 1 Apr 2026 09:31:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 5B4A5240046; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 4015C23C6F; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:38 +0200 Subject: [PATCH v3 2/7] PCI: intel-gw: Remove unused define Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260401-pcie-intel-gw-v3-2-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=814; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=xn9R5Y4c2FVuxWGJ+XDVZ0hhgrzdWZnr3TAJrrkBg1E=; b=2n6rYRrtMwOwx81lCIFQ0W2AWhvf3q4RacIeQ4eSmakSA57Y2RYgnsiphTqpojqcAeFN3gi3T JGZYtQgwfUoDaf4VGLIa+WWV3ceULfJ8VyJ9cHLk1AEy2JkPiyVooCT X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-type: clean X-purgate: clean X-purgate-ID: 151534::1775035904-4AFC9233-062AD981/0/0 The C preprocessor define 'PCIE_APP_INTX_OFST' is not used in the sources and can therefore be deleted. Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index c21906eced61896c8a8307dbd6b72d229f9a5c5f..80d1607c46cbbb1e274b37a0bb9= 377a877678f5d 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -47,7 +47,6 @@ #define PCIE_APP_IRN_INTD BIT(16) #define PCIE_APP_IRN_MSG_LTR BIT(18) #define PCIE_APP_IRN_SYS_ERR_RC BIT(29) -#define PCIE_APP_INTX_OFST 12 =20 #define PCIE_APP_IRN_INT \ (PCIE_APP_IRN_AER_REPORT | PCIE_APP_IRN_PME | \ --=20 2.47.3 From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C9F33CA4AA; Wed, 1 Apr 2026 09:31:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 7AFD1240041; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 5853C23C7E; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:39 +0200 Subject: [PATCH v3 3/7] PCI: intel-gw: Move interrupt enable to own function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260401-pcie-intel-gw-v3-3-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=2285; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=lb6QCw9gymNGaU3gwgLeUyGUNWDhF66pmRRGTrBntko=; b=rQwgFl4Y3u/zaLO2KM+VswviHpotzPnuC+xI0b58CHgFIm11ys7/5UjGdP05TPMsmXWNUhOLt QKS4JTQYyIkBDPaDMZxphq0t5C1D5yxeQvJqqSmaI3rQF9Y3L6AB48m X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate-ID: 151534::1775035904-3CFC5233-7AC93786/0/0 X-purgate: clean X-purgate-type: clean To improve the readability of the code, move the interrupt enable instructions to a separate function. That is already done for the disable interrupt instruction. In addtion, all pending interrupts are cleared and disabled, just as this is done in the disable function 'intel_pcie_core_irq_disable()'. After that, all relevant interrupts are enabled again. The 'PCIE_APP_IRNEN' definition contains all the relevant interrupts that are of interest. This change is also done in the Maxlinear SDK [1]. As I unfortunately don=E2=80=99t have any documentation for this IP core, I suspect that the intention is to set the IP core for interrupt handling to a specific state. Perhaps the problem was that the IP core did not reinitialize the interrupt register properly after a power cycle. In my view, it can=E2=80=99t do any harm to switch the interrupt off and th= en on again to set them to a specific state. [1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/control= ler/dwc/pcie-intel-gw.c#L431 Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index 80d1607c46cbbb1e274b37a0bb9377a877678f5d..e88b8243cc41c607c39e4d58c4d= cd8c8c082e8b0 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -195,6 +195,13 @@ static void intel_pcie_device_rst_deassert(struct inte= l_pcie *pcie) gpiod_set_value_cansleep(pcie->reset_gpio, 0); } =20 +static void intel_pcie_core_irq_enable(struct intel_pcie *pcie) +{ + pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); + pcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT); + pcie_app_wr(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT); +} + static void intel_pcie_core_irq_disable(struct intel_pcie *pcie) { pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); @@ -316,9 +323,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) if (ret) goto app_init_err; =20 - /* Enable integrated interrupts */ - pcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT, - PCIE_APP_IRN_INT); + intel_pcie_core_irq_enable(pcie); =20 return 0; =20 --=20 2.47.3 From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 394683CEBAD; Wed, 1 Apr 2026 09:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.37.255.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775035917; cv=none; b=c1pLKo51VtYTblEziJennBIfSJcPFZFyfUVf0TAK9irNFEO7Y5dlxnCYFg/52ox0QdOA8mv7a6OU4uT9MMmCxWiJC/M+aMWEYET60ybM6InXDjcvK0NMSp1dAOmnEuYpFhEKO1d1mPFoS3hcgQUpqAMYa6HESiNkp5LSM3mX4dg= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 792D023C6F; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:40 +0200 Subject: [PATCH v3 4/7] PCI: intel-gw: Enable clock before phy init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260401-pcie-intel-gw-v3-4-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=2080; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=coHmsdtqcsW+dKyhuAd7vn7jGgDFbg9jYRqHLyenC9w=; b=upmlMIqhxzzCBzYMxjiufaXeChhcEK6DMbp8eW3nyfpQ7M1+fzt4eU9xZ55SaDbLFN01wVifK 9ljfiAJ+60WDY/2pEJ2kFQYvV3VVXGr3Yh4tS/9zZvC+foq3A8n9Hzb X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-ID: 151534::1775035904-3D7CA233-2D4E2C4D/0/0 X-purgate: clean X-purgate-type: clean To ensure that the boot sequence is correct, the dwc pcie core clock must be switched on before phy init call [1]. This changes are based on patched kernel sources of the MaxLinear SDK. [1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/control= ler/dwc/pcie-intel-gw.c#L544 Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0..6d9499d954674a26a74bff56b7f= b5759767424c0 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -291,13 +291,9 @@ static int intel_pcie_host_setup(struct intel_pcie *pc= ie) =20 intel_pcie_core_rst_assert(pcie); intel_pcie_device_rst_assert(pcie); - - ret =3D phy_init(pcie->phy); - if (ret) - return ret; - intel_pcie_core_rst_deassert(pcie); =20 + /* Controller clock must be provided earlier than PHY */ ret =3D clk_prepare_enable(pcie->core_clk); if (ret) { dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret); @@ -306,13 +302,17 @@ static int intel_pcie_host_setup(struct intel_pcie *p= cie) =20 pci->atu_base =3D pci->dbi_base + 0xC0000; =20 + ret =3D phy_init(pcie->phy); + if (ret) + goto phy_err; + intel_pcie_ltssm_disable(pcie); intel_pcie_link_setup(pcie); intel_pcie_init_n_fts(pci); =20 ret =3D dw_pcie_setup_rc(&pci->pp); if (ret) - goto app_init_err; + goto err; =20 dw_pcie_upconfig_setup(pci); =20 @@ -321,17 +321,18 @@ static int intel_pcie_host_setup(struct intel_pcie *p= cie) =20 ret =3D dw_pcie_wait_for_link(pci); if (ret) - goto app_init_err; + goto err; =20 intel_pcie_core_irq_enable(pcie); =20 return 0; =20 -app_init_err: +err: + phy_exit(pcie->phy); +phy_err: clk_disable_unprepare(pcie->core_clk); clk_err: intel_pcie_core_rst_assert(pcie); - phy_exit(pcie->phy); =20 return ret; } --=20 2.47.3 From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 399093CF046; Wed, 1 Apr 2026 09:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id BB256240041; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 956B123C7E; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:41 +0200 Subject: [PATCH v3 5/7] PCI: intel-gw: Add start_link callback function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260401-pcie-intel-gw-v3-5-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=3153; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=1QhwwO0tMMhb5/PF/9cK8bvzkNyUt/Wf2sydrtsZXUc=; b=R0SlFWwKBmTvsj+uWe29f0bFOcUZ3aaui1f4slpL69Yzhec/iV1C5JcYguj/tAZlOBzsHgrGw 7AuOwZbgUEwDlrkbIPmFBCUa9PP2Xb0GGRi17WpPBktl8qKpFNldbfH X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-type: clean X-purgate: clean X-purgate-ID: 151534::1775035904-4B7CE233-00E17F81/0/0 The pcie-intel-gw driver has no start_link callback function. This commit adds the missing callback function so that the driver works again and does not abort with the following error messages during probing. [ 2.512015] intel-gw-pcie d1000000.pcie: host bridge /soc/pcie@d1000000 = ranges: [ 2.517868] intel-gw-pcie d1000000.pcie: MEM 0x00dc000000..0x00ddff= ffff -> 0x00dc000000 [ 2.528450] intel-combo-phy d0c00000.combo-phy: Set combo mode: combophy= [1]: mode: PCIe single lane mode [ 2.551619] intel-gw-pcie d1000000.pcie: No outbound iATU found [ 2.556060] intel-gw-pcie d1000000.pcie: Cannot initialize host [ 2.561901] intel-gw-pcie d1000000.pcie: probe with driver intel-gw-pcie= failed with error -22 [ 2.571041] intel-gw-pcie c1100000.pcie: host bridge /soc/pcie@c1100000 = ranges: [ 2.577736] intel-gw-pcie c1100000.pcie: MEM 0x00ce000000..0x00cfff= ffff -> 0x00ce000000 [ 2.588299] intel-combo-phy c0c00000.combo-phy: Set combo mode: combophy= [3]: mode: PCIe single lane mode [ 2.611471] intel-gw-pcie c1100000.pcie: No outbound iATU found [ 2.615934] intel-gw-pcie c1100000.pcie: Cannot initialize host [ 2.621759] intel-gw-pcie c1100000.pcie: probe with driver intel-gw-pcie= failed with error -22 Fixes: c5097b9869a1 ("Revert "PCI: dwc: Wait for link up only if link is st= arted"") Fixes: da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started") Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index 6d9499d954674a26a74bff56b7fb5759767424c0..afd933050c92ee31c477e0b1738= ab1136bdcfbf6 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -284,6 +284,16 @@ static void intel_pcie_turn_off(struct intel_pcie *pci= e) pcie_rc_cfg_wr_mask(pcie, PCI_COMMAND, PCI_COMMAND_MEMORY, 0); } =20 +static int intel_pcie_start_link(struct dw_pcie *pci) +{ + struct intel_pcie *pcie =3D dev_get_drvdata(pci->dev); + + intel_pcie_device_rst_deassert(pcie); + intel_pcie_ltssm_enable(pcie); + + return 0; +} + static int intel_pcie_host_setup(struct intel_pcie *pcie) { int ret; @@ -310,25 +320,12 @@ static int intel_pcie_host_setup(struct intel_pcie *p= cie) intel_pcie_link_setup(pcie); intel_pcie_init_n_fts(pci); =20 - ret =3D dw_pcie_setup_rc(&pci->pp); - if (ret) - goto err; - dw_pcie_upconfig_setup(pci); =20 - intel_pcie_device_rst_deassert(pcie); - intel_pcie_ltssm_enable(pcie); - - ret =3D dw_pcie_wait_for_link(pci); - if (ret) - goto err; - intel_pcie_core_irq_enable(pcie); =20 return 0; =20 -err: - phy_exit(pcie->phy); phy_err: clk_disable_unprepare(pcie->core_clk); clk_err: @@ -386,6 +383,7 @@ static int intel_pcie_rc_init(struct dw_pcie_rp *pp) } =20 static const struct dw_pcie_ops intel_pcie_ops =3D { + .start_link =3D intel_pcie_start_link, }; =20 static const struct dw_pcie_host_ops intel_pcie_dw_ops =3D { --=20 2.47.3 From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3981C3CF032; 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Wed, 1 Apr 2026 11:31:44 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 02315240040; Wed, 1 Apr 2026 11:31:44 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id B921B23C6F; Wed, 1 Apr 2026 11:31:43 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:42 +0200 Subject: [PATCH v3 6/7] PCI: intel-gw: Move driver atu base assignment to probe function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260401-pcie-intel-gw-v3-6-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=3975; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=Uirz/FKs+IwSVaGspwLzgInnY3C/WWrZXZmhIyMs3ww=; b=Jd98K2cRrkn4RSEm8cX9bkhkxxtSviuDs0QJhUoGiv2tzARq8fkFSRyRdICAdWJn4AD6usr7B Wy6UjdjsZ5xBu+GurJoRvAzsv/iS3AJR0qedRX04b8HeC7hymNs0rEQ X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate-type: clean X-purgate: clean X-purgate-ID: 151534::1775035904-4A7C8233-E0A53BA3/0/0 If no ATU resource is defined in the devicetree, then driver=C2=B4s default value '0x300000' [1] is set. This is done during probing in the function 'dw_pcie_get_resources()' [2] by dwc core. The driver overwrites this again when its own init callback 'pp->ops->init()' [3] function 'intel_pcie_host_setup()' [4] is called. This is done, because the 'atu_base' value for this IP is '0xC0000' rather than '0x300000'. callstack: intel_pcie_probe() dw_pcie_host_init() dw_pcie_host_get_resources() dw_pcie_get_resources() [2] pp->ops->init =3D intel_pcie_rc_init() [3] intel_pcie_host_setup() [4] However, this is a problem because, the callback 'pp->ops->init' is called after 'dw_pcie_get_resources()' in dwc core (see callstack). The 'atu_base' must be set before, so that this value is not set by dwc core. Therefor the assignment of 'atu_base' is moved to driver=C2=B4s probe function. While we=E2=80=99re at it, the change also adds the option to load ATU info= rmation from the device tree. For reasons of backwards compatibility, this is not mandatory. If =E2=80=98atu=E2=80=99 is still not specified in the devicetre= e, then driver=E2=80=99s default value is still used and set in driver=C2=B4s probe function. If the= 'atu' resource is present in the devicetree, then dwc core loads it via the function 'dw_pcie_get_resources()' and not in the driver=C2=B4s probe funct= ion. [1] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller= /dwc/pcie-designware.h#L292 [2] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller= /dwc/pcie-designware.c#L150 [3] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller= /dwc/pcie-designware-host.c#L589 [4] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller= /dwc/pcie-intel-gw.c#L301 Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 28 ++++++++++++++++++++++++++= -- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index afd933050c92ee31c477e0b1738ab1136bdcfbf6..59b11e45944e199aac0f599f96d= 6cc90e2104708 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -310,8 +310,6 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) goto clk_err; } =20 - pci->atu_base =3D pci->dbi_base + 0xC0000; - ret =3D phy_init(pcie->phy); if (ret) goto phy_err; @@ -395,6 +393,7 @@ static int intel_pcie_probe(struct platform_device *pde= v) struct device *dev =3D &pdev->dev; struct intel_pcie *pcie; struct dw_pcie_rp *pp; + struct resource *res; struct dw_pcie *pci; int ret; =20 @@ -419,6 +418,31 @@ static int intel_pcie_probe(struct platform_device *pd= ev) pci->ops =3D &intel_pcie_ops; pp->ops =3D &intel_pcie_dw_ops; =20 + /* + * If the 'atu' resource is not available in the devicetree, + * then use the driver default value for backward compatibility. + * The 'atu' should always be set in the devicetree, as this is + * hardware specific setting that should not be defined in the + * source. + */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + if (!res) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + pci->dbi_base =3D devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + pci->dbi_phys_addr =3D res->start; + pci->atu_base =3D devm_ioremap(dev, res->start + 0xC0000, SZ_4K); + if (!pci->atu_base) { + dev_err(dev, "failed to remap ATU space\n"); + return -ENOMEM; + + } + pci->atu_size =3D SZ_4K; + pci->atu_phys_addr =3D res->start + 0xC0000; + dev_warn(dev, "devicetree ATU resource is missing; driver`s default valu= e is being used\n"); + } + ret =3D dw_pcie_host_init(pp); if (ret) { dev_err(dev, "Cannot initialize host\n"); --=20 2.47.3 From nobody Wed Apr 1 22:35:44 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 397853CF02D; Wed, 1 Apr 2026 09:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.37.255.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775035917; cv=none; b=Flae8pASdlMsaQVPt8TFR1izkEKdG5ROywY03fZDKxn5ldatZoR/14HD/iCLS3+JW5zKnTm8cvjs6qqFQPryg+ElVKvHSxoMOZsTe0C3NEufAAvHumnjmwzawjYT9anhXxcm2qnLMx0qMFKopgkW9ubwBrhjG1TQ7KSNdrSHHVA= ARC-Message-Signature: i=1; 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Wed, 1 Apr 2026 11:31:44 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 0059923C7E; Wed, 1 Apr 2026 11:31:44 +0200 (CEST) From: Florian Eckert Date: Wed, 01 Apr 2026 11:31:43 +0200 Subject: [PATCH v3 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu resource Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260401-pcie-intel-gw-v3-7-63b008c5b7b2@dev.tdt.de> References: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> In-Reply-To: <20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley , Rahul Tanwar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775035902; l=2237; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=HJlP/B9l/9XIBtHUr6FUXPARzVZw8W2vrdkskTwd5Tw=; b=FLahYPjlIdeF7+mWTBgC9P9Ri0wSzLTVgpjH7VcmM1VkQS1r9ehocBcI+yYgbRDkcApt6ocxl 6aj5lslBovIBwy/y0NI+YJvacqDqm+NNkjtkS2Ot7+1L4hV7ZrMXtY+ X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate-ID: 151534::1775035905-3CFC5233-26DC20E1/0/0 X-purgate: clean X-purgate-type: clean The 'atu' information is already set in the dwc core, if it is specified in the devicetree. The driver uses its own default, if not set in the devicetree. This information is hardware specific and should therefore be maintained in the devicetree rather than in the source. To be backward compatibile, this field is not mandatory. If 'atu' resource is not specified in the devicetree, the driver=E2=80=99s default v= alue is used. Old DTS entry for PCIe: reg =3D <0xd1000000 0x1000>, <0xd3000000 0x20000>, <0xd0c41000.0x1000>; reg-names =3D "dbi", "config", "app"; New DTS entry for PCIe: reg =3D <0xd1000000 0x1000>, <0xd10c0000 0x1000>, <0xd3000000 0x20000>, <0xd0c41000.0x1000>; reg-names =3D "dbi", "atu", "config", "app"; Signed-off-by: Florian Eckert --- Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/intel-gw-pcie.yaml index 54e2890ae6314ac6847fc23f49440d05d66d87d4..a7cb2b66b382a55d88211890aee= 068f25f05f61b 100644 --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml @@ -27,16 +27,19 @@ properties: - const: snps,dw-pcie =20 reg: + minItems: 3 items: - description: Controller control and status registers. - description: PCIe configuration registers. - description: Controller application registers. + - description: Internal Address Translation Unit (iATU) registers. =20 reg-names: items: - const: dbi - const: config - const: app + - const: atu =20 ranges: maxItems: 1 @@ -94,9 +97,10 @@ examples: #address-cells =3D <3>; #size-cells =3D <2>; reg =3D <0xd0e00000 0x1000>, + <0xd0ec0000 0x1000>, <0xd2000000 0x800000>, <0xd0a41000 0x1000>; - reg-names =3D "dbi", "config", "app"; + reg-names =3D "dbi", "atu", "config", "app"; linux,pci-domain =3D <0>; max-link-speed =3D <4>; bus-range =3D <0x00 0x08>; --=20 2.47.3