From nobody Wed Apr 1 20:46:06 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F96C421A08 for ; Wed, 1 Apr 2026 11:52:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775044341; cv=none; b=mb97lbqcWcWozDouCdilZR6CUPKA9etbe8bdCzyzrY7a3uPj58o16Rmr6MEUdJlF2JnFz1Z454H2ueLdxdYT16OWb+bZA+A67SxURHKPqU2xda7Afx1uXd/JhaoElUi1oPIdEoQx2NNfL9UCzIptyVLldFBJ1TBVkRJyjJim4DE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775044341; c=relaxed/simple; bh=DN2hdJkQfwOmkV73g25P6amt7YJJMBYy4ixSvMZeed0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rPBPM8PruP+ujf6zP8f+OObX7hdhkS6nRJpnEN9Sew/plHsFADcGhFjf3bOt/UlNUcZpsyxIl7vyjEt7OpcgS2KY+2d44K6ke77nwwh/qj0bhs48PFZ4kDkSc9Mzi5/5cr0nMAzQjQ2qWR4MiWakZPS0f+0pUx4NQ0KGBlW0ONk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=DArvxcAD; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=j0Y+hhre; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="DArvxcAD"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="j0Y+hhre" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6317BCC0719536 for ; Wed, 1 Apr 2026 11:52:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= B1qj1pjFBSlaz4iTK542UNdUPrp5cuuyZd0VJJVSPDU=; b=DArvxcADu8+8+nZ0 OQznhjZsM0ojhErJDfpf2hngq9yP0uHbMiuFL/Io3X8dzzPat90CYKpZqfHdFk/q ymeU3YP+KfJ33x2So4d2kvYht2TXh8BLW19wkxeoWRITu0ePcfcHmSLeA61yO38D 1LYyoTQ9ib0J3W3uJ9For3UA+CYt0rX1Q6zl/PHlj+EsfRPMHaTspwAHybzWGN2y 8/DiE5v0l9c5GTTOA7xIDvS47OJGmCxkQ1jYgN+r4+g0obKvPfeu8N6/EqeyWLlv AE9nWIUbQQHUJOyvlNS3zkRnt+GVZgaT8/vLRIWxaaMVJlOSZy5+BrahHuWkD4da 8PePyg== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d8kcsutbm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 01 Apr 2026 11:52:18 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-82cf084fe58so293422b3a.1 for ; Wed, 01 Apr 2026 04:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775044337; x=1775649137; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B1qj1pjFBSlaz4iTK542UNdUPrp5cuuyZd0VJJVSPDU=; b=j0Y+hhref5kJG5rwROoDPYgZeL4TAdCFykuxCF21Xu71y+u5tjmS2nqS3dz7vVFuC4 Nvn/bCEC/lzUhscs4QAD+sSRX0LnXStbku7he0ylWbhdBAxA7ppihTozyeeoeJDnGUh6 85xpNMd/l4iSoy4qJ8f91XcKp4m6yaGGJv7XNz+qEctbdg1Ybc+BnkB5czL/It99RvO7 /J7KmsTAN/UKqrXiJQ/rvVMHIvnkHu3FKLQJFzYV+kJ2cpVbsKcdGhJ18u9obEhmzcac 8/bdoZ4wMkE6HRa9+uDptFU3hWhf9P3PxpM0aP4PiG5xFKdWbEXN0ApIvrRS2STrOyCS WwZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775044337; x=1775649137; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=B1qj1pjFBSlaz4iTK542UNdUPrp5cuuyZd0VJJVSPDU=; b=lTsVeDZ2XeZg/EwWPL7P+A8JsnquoNSSfoL5xiYSi6jfgmgj0FGkcjopRpx9KYLafD 0j+GxWYyATndw+jp+Zim9miSS4o9dqGT+qf0LAfPZzEUk5hCptJ4BqYhFuRYE/3Cnf4V R3s4yI3pl2o61mUDKYCweYr/MkPCP6S6cmlTVIFBg8Kk2EW8EtBOakGCUXC6zw3BESXN z6Nm/E0xwk4e7EeMxlXJ/Tupk/Giz/pMEYOiO8zOgwOH697xerKPd9lyrfajZdQlwHfG Cd0L8XeHp3X16dv3mdS5CC+9wjtZrLeuMC/FTorYUfUNmxOf/KU8QHGG3LNNHL95i4OE 6a8w== X-Forwarded-Encrypted: i=1; AJvYcCUCUQXIfxCkY3VlZ5bbVYvk+q08J6S9FtzkhpGqU+egr+Q2svbLU0nlZkVypKY0ExzdUoIAgg63JRN6+n0=@vger.kernel.org X-Gm-Message-State: AOJu0YxLBfghV8s35MYFx7OCbt404uRcgegQjU1eqVizvYSKG2IIE4ur yvtKAKPC5jDSS5AzhRWopmW+/Nu+j/vNnf8q45AqB4mdP8/VjisU0w33LY52trawTvytiAu8AIZ hbqO8XLkhUH0Ey+MH7hNhnqJr82sxWmwW3kQi6SYd7/RMLeY63A+dzieKMNo9JcGO41Y= X-Gm-Gg: ATEYQzyo3/I7uJjdA2moBHRfeJkvBQzaNcY6lM1WUtNgCs/GIIyyxocNYKvyFIZ4dJY cTYPVzY+e9Otr3wewO+zmd3YFVQDBWyBg6KVt4XKKy5I0y11ZX0Jn+TNLfgmQHRldXcnjGuvpri Gq8NSojxTzZbvIEfz3P2JpZvK7pOF0WtJQpEUU+7DiJ627uXR7kqyJwBa9rgw4rcq5jcISudtex QF+OFkpmpIvcKKEmtCnhOV2b7AWIeDFPG/jIMEKhtf+zCKXe6jyqvkikS5O9hheN5eIF/Fvk0se hgPTHNE7TdzTJC5ye5U5QnXrcD4A8G8/xclLFl9hPR3KDLhL08JacWz5XmnlicincRW7bFm6mMF hVaeOsw/hL+p459WvrIV2sttbGP9Qj5Kw2xHOr3YFTkAPFu0n X-Received: by 2002:a05:6a00:2d98:b0:82c:2480:4e3d with SMTP id d2e1a72fcca58-82ce894352emr3330640b3a.9.1775044337263; Wed, 01 Apr 2026 04:52:17 -0700 (PDT) X-Received: by 2002:a05:6a00:2d98:b0:82c:2480:4e3d with SMTP id d2e1a72fcca58-82ce894352emr3330607b3a.9.1775044336641; Wed, 01 Apr 2026 04:52:16 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82ca8465785sm18128456b3a.18.2026.04.01.04.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 04:52:16 -0700 (PDT) From: Mukesh Ojha Date: Wed, 01 Apr 2026 17:22:07 +0530 Subject: [PATCH 1/2] dt-bindings: pinctrl: describe Hawi TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-hawi-pinctrl-v1-1-4718da24e531@oss.qualcomm.com> References: <20260401-hawi-pinctrl-v1-0-4718da24e531@oss.qualcomm.com> In-Reply-To: <20260401-hawi-pinctrl-v1-0-4718da24e531@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mukesh Ojha X-Mailer: b4 0.14-dev-f7c49 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775044329; l=5116; i=mukesh.ojha@oss.qualcomm.com; s=20250708; h=from:subject:message-id; bh=DN2hdJkQfwOmkV73g25P6amt7YJJMBYy4ixSvMZeed0=; b=MvkLZJ7m5M1Y3895YsXu0qHuOgRR2PXaJKLD88QyTe5f3T16BTLu7qzFXL05VkVQkqaBFDUyu CFWZZrXOct3D7IzjwGoRnrWtKAAuSGO/1HX9ELKXzDVE+J38i1T/CZg X-Developer-Key: i=mukesh.ojha@oss.qualcomm.com; a=ed25519; pk=eX8dr/7d4HJz/HEXZIpe3c+Ukopa/wZmxH+5YV3gdNc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDEwOCBTYWx0ZWRfX8S+T1OzaWpDZ iZvmQAqJ+akcDtT3/u4RTKCObvKCHsa2ospFbjCdecX5VWQE2baGcdXLFBtBrNMO3yxXWFRwha+ LXHoBeLM/dcPAVDLyPb9uROgNvafAtMOI1DH7Dc/jY7UNl828iGX68Y7Ypz05d24HqbMCNNhzMz OpUJoWEPTdd/W4zEExRIiuoJkTmOiDd4J25hVHXgyjbxu0osiBKnTLVAYKz03juFuHud8bUmK7v fNMV9OQBFJ3Fxi+lMAd4wvQ5j8GsggV+ekjuc0ZfcIUYWoLSWx6D3bOIfgVjffFKM8Jk8SN63EC hjtPu+GJb4Za6C2WpTXy5kS2IVz1AhaiJPSNRT0YXk8tPj36/eOBv8vzgSu07VpK00Y5QR2pXqe 2aJ2KFqxOKQYvBtATniQIH3PQiiRTI/88kstM6zhYCw4W4NBn6eBOfg1Ip8hnK8ndOyj1W7ez5s LP497adPSSLREAbfsgQ== X-Authority-Analysis: v=2.4 cv=KNlXzVFo c=1 sm=1 tr=0 ts=69cd06f2 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=bT5XQOCXPleopHcqzpYA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: JszDKiZTJY_9OaUXXmgRvVFjnzSgGvsR X-Proofpoint-GUID: JszDKiZTJY_9OaUXXmgRvVFjnzSgGvsR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_03,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010108 The Top Level Mode Multiplexer (TLMM) in the Hawi SoC provide GPIO and pinctrl functionality for UFS, SDC and 226 GPIO pins. Add a DeviceTree binding to describe the Hawi TLMM block. Signed-off-by: Mukesh Ojha --- .../bindings/pinctrl/qcom,hawi-tlmm.yaml | 123 +++++++++++++++++= ++++ 1 file changed, 123 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml new file mode 100644 index 000000000000..303bd7262aac --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Hawi TLMM block + +maintainers: + - Mukesh Ojha + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,hawi-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 113 + + gpio-line-names: + maxItems: 226 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-hawi-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-hawi-tlmm-state" + additionalProperties: false + +$defs: + qcom-hawi-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]= |22[0-5])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl, cci_i2= c_sda, + cci_timer, coex_espmi_sclk, coex_espmi_sdata, coex_uart1_r= x, + coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, + egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0, i2chub0_se= 1, + i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0_data, i2s0_sck, + i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bis= t, + mdp_esync0, mdp_esync1, mdp_esync2, mdp_vsync, mdp_vsync_e, + mdp_vsync_p, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_ou= t, + mdp_vsync3_out, mdp_vsync5_out, modem_pps_in, modem_pps_ou= t, + nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, nav_gpio4, nav= _gpio5, + nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n, + phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink_en= able, + qlink_request, qlink_wmss, qspi, qspi_clk, qspi_cs, qup1_s= e0, + qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, + qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4= _l0, + qup2_se4_l1, qup2_se4_l2, qup2_se4_l3, qup3_se0_l0, qup3_s= e0_l1, + qup3_se0_l2, qup3_se0_l3, qup3_se1, qup3_se2, qup3_se3, qu= p3_se4, + qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_l0, qup4_= se3_l1, + qup4_se3_l2, qup4_se3_l3, qup4_se4_l0, qup4_se4_l1, qup4_s= e4_l2, + qup4_se4_l3, rng_rosc, sd_write_protect, sdc4_clk, + sdc4_cmd, sdc4_data, sys_throttle, tb_trig_sdc, tmess_rng, + tsense_clm, tsense_pwm, uim0_clk, uim0_data, uim0_present, + uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, + usb0_hs, usb_phy, vfr, vsense_trigger_mirnat, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,hawi-tlmm"; + reg =3D <0x0f100000 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 227>; + interrupt-controller; + #interrupt-cells =3D <2>; + + qup-uart7-state { + pins =3D "gpio62", "gpio63"; + function =3D "qup1_se7"; + }; + }; +... --=20 2.53.0 From nobody Wed Apr 1 20:46:06 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09A6B421EEA for ; Wed, 1 Apr 2026 11:52:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775044348; cv=none; b=ucclU3KM8AfDONKMhHqvARniWq8qpU8cfPQg1SJUiw/qtK4GW2lsgEbxwHhR4hNcY/ZhZkSf+TTgxxoyHpH/zq6wae1ErKktraggYtH03uaNFdkPxRXLEi1G4j8hNYwftnymvqrwbUx4ryKqUea/0O6yoqUWAD21XRti4Gpd7uY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775044348; c=relaxed/simple; bh=a9ydf/RFTgt+RZ7T99u7/unHLs6aC+CWKBGO9l/f1ms=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E09Kzpenh+c/OLpIxZNHeFDDAYQKM/Q8RII8G2AxZ8tVV16yaBmspfZLXGtnVofilXciPGwUNNlNK+NLPogDVsCa0SR0TM0SeviRlYTqIJjPTyc77t6Okni+EiknXF/7uJjfmKGf4dhVz8B32HwzZ4zPxAooF3ZRCyQU+U4fHTA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=WRWILDSc; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bDwjCKPw; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="WRWILDSc"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bDwjCKPw" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 631AYM5c1579948 for ; Wed, 1 Apr 2026 11:52:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= tIznDBlxwQvgKPsXtCNfFdqDHLei+HMt3T0ddp0b9C0=; b=WRWILDScbA4X+OQ/ VoFU85vwt8kpnwyE55h7oxhpN1ZlWMJfNFnI30zyJKMFrm8QiLll+vqagf1bJxcK Y6XT90G6zYeEu+/0lD7eOhZzMhLqXaVGNvU/RLke0YMSGRrkhuvG5gacKvy1lnlq D5UUKbDTFT6L3zA3JlL4dR5nvhad2MywKpIMZjJO78GTLuFYokdweQdmxW0udhhW 96pH621LnDdIkMlVghVG0H6FWJYBk3fVBj/W8jhexcdiyBeWMmXC8PDNumgNvTNE UmAN1GjiOBmlxS0k0z+KtRrIw8ZUZIATkPaaZE/CZFtoGL5hll0Q7TeC5N6j1Pr4 mZFZow== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d8mr2ub8n-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 01 Apr 2026 11:52:23 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-82c7a84a43eso14361239b3a.0 for ; Wed, 01 Apr 2026 04:52:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775044343; x=1775649143; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tIznDBlxwQvgKPsXtCNfFdqDHLei+HMt3T0ddp0b9C0=; b=bDwjCKPwLYTGFTtkSgxFUmyl8PGuHTyxDoBsKSQHQI8Qv8pLNsL1cxvitJzrKVLRe4 TgKMQnXDAGAJcoC6azaV6ie+alv9OajecBapdbG5oyy7V0RCweR026rUA1pTFtriuDn4 dKFmVC/ESWZ5+Q3YuKyorJUTpq9F78JrDoWIVsoslc9QqXWSfdCN6QeQjfzWQ5Sebb+n YSzqVOh9u750TWo+y6FRY8uYEerRtZ9dYDsbVz63fhHMNzlQn+N1M3ah8l9TUK6UXyhH YP5weeygO3nxbEPNr12+35w0fDxuFAZe6ryayNm1Dfgle4ttzojLtxXllWgwjIHnQxhG UWAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775044343; x=1775649143; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=tIznDBlxwQvgKPsXtCNfFdqDHLei+HMt3T0ddp0b9C0=; b=BV6rhW2jij9URxDCJ+ccXnAE+kkCz23FNDQL07QTyz8MBwuY27fNpq2eD/BtbXhaE9 a4QgwCaBkq4z9ZGbGhNfxK1kfR4495yo8KMt6ZLQa7pG0FURIgzyAEwzVT612Gd3i4qy GoRSkxDiIBtQT/jyQnmqEkWgOIgH0kioBfPH4JjmX2GMaWtt2r/ai6fkC5DV/R/tztBs X9dX5GZzgMTfrKYsNnPvrsxZ2MUXZikUOMvW1AR/+IPQS2bC6c5jmyO0ajNJGdjgAKkH ExIDfXdwam9qc1YV7HsoezAGxPFq3Bh1nbK78Oqh0qo6cgPznZL7SRCw0ACsV7QswQgd Iylw== X-Forwarded-Encrypted: i=1; AJvYcCX26y3+KTeuaeR/3pKJevgOUtImP99O0R5Na1OHW+CC7M31gM6AfCLy2GHpbjg7Tvg4ok44y9CNGaFhPxE=@vger.kernel.org X-Gm-Message-State: AOJu0Yy/qY/XBTCtXzLLYiNHmaEQrrtptPiFY6wxlJ50ZSAndE71t7K0 FO+JpP/eh6EjPWlLgBBGXorxWUPyK8ooAFQAfA/h+P8UK6LaZ+PVQYw9EcC9fMyGwr7EEBkdqOn 7VoF/ZeLEcCfrqAzoHAyHTkypZveSytxxISClWXl+0Ea4aEdwEz9+u/ANyWKnjIXhPKc= X-Gm-Gg: ATEYQzzvcqAQ2IYW3cVMsPzXVtzbnepRtgTklUXG6PT7QDHHAV3h3jQAUBcG7srNwcY l7Ax9p1IdEpL4lZeHt6Xd9Kz+r1uR0N/tSaNhBHrBtSbPaSyd/jXknl9chZ0Sr1PA1CU4kWzigt ief1teWqHHIUlyJ6I71PSsGhShvGj2cGjTH+mD4AYWEWNkbV3qlv5bm77Q6lWMgGfhO0u/7g2x8 1P3II7iU36uTTpmOJFKyqzgjF4TAEZdNiwFkV5oPAJ4YYxxkKNwAg/EzHXuWVXSd8lrGtxzNlwA X56p6o6xcdJC70anU6uijlvK+bekeQwZMHNzpxFWMyQJOxn6U6HS7mJ2oMPwciSj2G2gPNEUckY hpmhtXee82ttyujU1P1EU7bIwIzWsIh0uH3zctbYTk97UegwJ X-Received: by 2002:a05:6a00:4517:b0:82a:805a:7e2 with SMTP id d2e1a72fcca58-82ce88bbedbmr3704817b3a.9.1775044341902; Wed, 01 Apr 2026 04:52:21 -0700 (PDT) X-Received: by 2002:a05:6a00:4517:b0:82a:805a:7e2 with SMTP id d2e1a72fcca58-82ce88bbedbmr3704757b3a.9.1775044340727; Wed, 01 Apr 2026 04:52:20 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82ca8465785sm18128456b3a.18.2026.04.01.04.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 04:52:20 -0700 (PDT) From: Mukesh Ojha Date: Wed, 01 Apr 2026 17:22:08 +0530 Subject: [PATCH 2/2] pinctrl: qcom: Add Hawi pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-hawi-pinctrl-v1-2-4718da24e531@oss.qualcomm.com> References: <20260401-hawi-pinctrl-v1-0-4718da24e531@oss.qualcomm.com> In-Reply-To: <20260401-hawi-pinctrl-v1-0-4718da24e531@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mukesh Ojha , Konrad Dybcio X-Mailer: b4 0.14-dev-f7c49 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775044329; l=61255; i=mukesh.ojha@oss.qualcomm.com; s=20250708; h=from:subject:message-id; bh=a9ydf/RFTgt+RZ7T99u7/unHLs6aC+CWKBGO9l/f1ms=; b=QtTOCeuIrMYGN5ZFAZHp6PyefQ7f14o1ZNdSsNUpBtrQxZ0OHxvZ4LwczWeMsz6OSDJqToQj+ Kcm3Qv+92djBeZxWRXPjsxERvEc93+4QtESwpVvhLMQbb9p3xhoHJjP X-Developer-Key: i=mukesh.ojha@oss.qualcomm.com; a=ed25519; pk=eX8dr/7d4HJz/HEXZIpe3c+Ukopa/wZmxH+5YV3gdNc= X-Authority-Analysis: v=2.4 cv=B+O0EetM c=1 sm=1 tr=0 ts=69cd06f7 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=FpwGTtBS0TdsuDR0F6QA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: WyRt-jSuEa3471uUx9m9Il1UjdDQndNy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDEwOCBTYWx0ZWRfXxSHVhYPRG7lI 9fidQ9GGsP8YED+f4Ju+tJoeQHfK1q6cG5TESmo24Auya4Sr4tCkkqOKoUupZ9j2I6eJGSXJEN+ bCWNnkffi1cagAOeSC496ZOjK+TcJunAfoV/n0v035ANd0+RPoRiaxZoPU08mrCVeRdpTjyIBFF 6m6O2LPlUZEc0mg1wX7NvODuozlREfzQWjFNC+m8GKhOcGx95OrV5Vwx+AD9/ZGenQup1hnP1I2 9FbuYjHwBRi5TLLI3aKnTIfMwToMdeah0QZxSyeUIQ7bkuCbEDT6jbI/vt6/PRn7ryVKLUB49BP yTKB6QOoxa+w4PAntHdIKyudPjvRkPtQl/3fCh90SZy/Z+MzAvX3AkBdT8I+y2XQfPgB9RBnePD lb4Gf9X/gBIGsynTk7cVRsP56/FniqlA3sthly4M9AluVBEV599E3aWAs0NPPFzQKgVwu7GISJx niG79X0jPR3nPU8uMVQ== X-Proofpoint-GUID: WyRt-jSuEa3471uUx9m9Il1UjdDQndNy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_03,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010108 Add pinctrl driver for TLMM block found in the Hawi SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- drivers/pinctrl/qcom/Kconfig.msm | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-hawi.c | 1716 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 1727 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 6df6159fa5f8..63c88cbf2381 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -35,6 +35,16 @@ config PINCTRL_GLYMUR Say Y here to compile statically, or M here to compile it as a module. If unsure, say N. =20 +config PINCTRL_HAWI + tristate "Qualcomm Technologies Inc Hawi pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + block found on the Qualcomm Technologies Inc Hawi platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_IPQ4019 tristate "Qualcomm IPQ4019 pin controller driver" depends on ARM || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a8fd12f90d6e..dc6457e69a02 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) +=3D pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) +=3D pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_ELIZA) +=3D pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) +=3D pinctrl-glymur.o +obj-$(CONFIG_PINCTRL_HAWI) +=3D pinctrl-hawi.o obj-$(CONFIG_PINCTRL_IPQ4019) +=3D pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) +=3D pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) +=3D pinctrl-ipq8064.o diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pin= ctrl-hawi.c new file mode 100644 index 000000000000..3c0648a6931a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c @@ -0,0 +1,1716 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs =3D 12, \ + .ctl_reg =3D REG_SIZE * id, \ + .io_reg =3D 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D 0xc + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .egpio_enable =3D 12, \ + .egpio_present =3D 11, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_wakeup_present_bit =3D 6, \ + .intr_wakeup_enable_bit =3D 7, \ + .intr_target_bit =3D 8, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D 0, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D pull, \ + .drv_bit =3D drv, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D -1, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D io, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D 3, \ + .drv_bit =3D 0, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D 0, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +static const struct pinctrl_pin_desc hawi_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "UFS_RESET"), + PINCTRL_PIN(227, "SDC2_CLK"), + PINCTRL_PIN(228, "SDC2_CMD"), + PINCTRL_PIN(229, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); + +static const unsigned int ufs_reset_pins[] =3D { 226 }; +static const unsigned int sdc2_clk_pins[] =3D { 227 }; +static const unsigned int sdc2_cmd_pins[] =3D { 228 }; +static const unsigned int sdc2_data_pins[] =3D { 229 }; + +enum hawi_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_coex_espmi_sclk, + msm_mux_coex_espmi_sdata, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp, + msm_mux_gnss_adc, + msm_mux_host_rst, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2s0_data, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s1_data, + msm_mux_i2s1_sck, + msm_mux_i2s1_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_esync0, + msm_mux_mdp_esync1, + msm_mux_mdp_esync2, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync5_out, + msm_mux_modem_pps_in, + msm_mux_modem_pps_out, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_nav_gpio3, + msm_mux_nav_gpio4, + msm_mux_nav_gpio5, + msm_mux_nav_rffe, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_rst_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qlink_wmss, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4_l0, + msm_mux_qup2_se4_l1, + msm_mux_qup2_se4_l2, + msm_mux_qup2_se4_l3, + msm_mux_qup3_se0_l0, + msm_mux_qup3_se0_l1, + msm_mux_qup3_se0_l2, + msm_mux_qup3_se0_l3, + msm_mux_qup3_se1, + msm_mux_qup3_se2, + msm_mux_qup3_se3, + msm_mux_qup3_se4, + msm_mux_qup3_se5, + msm_mux_qup4_se0, + msm_mux_qup4_se1, + msm_mux_qup4_se2, + msm_mux_qup4_se3_l0, + msm_mux_qup4_se3_l1, + msm_mux_qup4_se3_l2, + msm_mux_qup4_se3_l3, + msm_mux_qup4_se4_l0, + msm_mux_qup4_se4_l1, + msm_mux_qup4_se4_l2, + msm_mux_qup4_se4_l3, + msm_mux_rng_rosc, + msm_mux_sd_write_protect, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sys_throttle, + msm_mux_tb_trig_sdc, + msm_mux_tmess_rng, + msm_mux_tsense_clm, + msm_mux_tsense_pwm, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const aoss_cti_groups[] =3D { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const atest_char_groups[] =3D { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133", +}; + +static const char *const atest_usb_groups[] =3D { + "gpio70", "gpio71", "gpio72", "gpio73", "gpio129", +}; + +static const char *const audio_ext_mclk_groups[] =3D { + "gpio120", "gpio121", +}; + +static const char *const audio_ref_clk_groups[] =3D { + "gpio120", +}; + +static const char *const cam_mclk_groups[] =3D { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", + "gpio95", "gpio96", +}; + +static const char *const cci_async_in_groups[] =3D { + "gpio15", "gpio109", "gpio110", +}; + +static const char *const cci_i2c_scl_groups[] =3D { + "gpio110", "gpio112", "gpio114", "gpio116", "gpio149", "gpio160", +}; + +static const char *const cci_i2c_sda_groups[] =3D { + "gpio107", "gpio108", "gpio109", "gpio111", "gpio113", "gpio115", +}; + +static const char *const cci_timer_groups[] =3D { + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160", +}; + +static const char *const coex_espmi_sclk_groups[] =3D { + "gpio144", +}; + +static const char *const coex_espmi_sdata_groups[] =3D { + "gpio145", +}; + +static const char *const coex_uart1_rx_groups[] =3D { + "gpio144", +}; + +static const char *const coex_uart1_tx_groups[] =3D { + "gpio145", +}; + +static const char *const dbg_out_clk_groups[] =3D { + "gpio82", +}; + +static const char *const ddr_bist_groups[] =3D { + "gpio40", "gpio41", "gpio44", "gpio45", +}; + +static const char *const ddr_pxi_groups[] =3D { + "gpio43", "gpio44", "gpio45", "gpio46", + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const dp_hot_groups[] =3D { + "gpio47", +}; + +static const char *const egpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio218", +}; + +static const char *const gcc_gp_groups[] =3D { + "gpio86", "gpio87", "gpio130", "gpio131", "gpio132", "gpio158", +}; + +static const char *const gnss_adc_groups[] =3D { + "gpio40", "gpio41", "gpio42", "gpio77", +}; + +static const char *const host_rst_groups[] =3D { + "gpio106", +}; + +static const char *const i2chub0_se0_groups[] =3D { + "gpio66", "gpio67", +}; + +static const char *const i2chub0_se1_groups[] =3D { + "gpio78", "gpio79", +}; + +static const char *const i2chub0_se2_groups[] =3D { + "gpio68", "gpio69", +}; + +static const char *const i2chub0_se3_groups[] =3D { + "gpio70", "gpio71", +}; + +static const char *const i2chub0_se4_groups[] =3D { + "gpio72", "gpio73", +}; + +static const char *const i2s0_data_groups[] =3D { + "gpio123", "gpio124", +}; + +static const char *const i2s0_sck_groups[] =3D { + "gpio122", +}; + +static const char *const i2s0_ws_groups[] =3D { + "gpio125", +}; + +static const char *const i2s1_data_groups[] =3D { + "gpio118", "gpio120", +}; + +static const char *const i2s1_sck_groups[] =3D { + "gpio117", +}; + +static const char *const i2s1_ws_groups[] =3D { + "gpio119", +}; + +static const char *const ibi_i3c_groups[] =3D { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33", + "gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61", +}; + +static const char *const jitter_bist_groups[] =3D { + "gpio73", +}; + +static const char *const mdp_esync0_groups[] =3D { + "gpio88", "gpio100", +}; + +static const char *const mdp_esync1_groups[] =3D { + "gpio86", "gpio100", +}; + +static const char *const mdp_esync2_groups[] =3D { + "gpio87", "gpio97", +}; + +static const char *const mdp_vsync_groups[] =3D { + "gpio86", "gpio87", "gpio88", "gpio97", +}; + +static const char *const mdp_vsync_e_groups[] =3D { + "gpio98", +}; + +static const char *const mdp_vsync_p_groups[] =3D { + "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] =3D { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] =3D { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] =3D { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] =3D { + "gpio87", +}; + +static const char *const mdp_vsync5_out_groups[] =3D { + "gpio87", +}; + +static const char *const modem_pps_in_groups[] =3D { + "gpio151", +}; + +static const char *const modem_pps_out_groups[] =3D { + "gpio151", +}; + +static const char *const nav_gpio0_groups[] =3D { + "gpio150", +}; + +static const char *const nav_gpio1_groups[] =3D { + "gpio151", +}; + +static const char *const nav_gpio2_groups[] =3D { + "gpio148", +}; + +static const char *const nav_gpio3_groups[] =3D { + "gpio150", +}; + +static const char *const nav_gpio4_groups[] =3D { + "gpio146", +}; + +static const char *const nav_gpio5_groups[] =3D { + "gpio147", +}; + +static const char *const nav_rffe_groups[] =3D { + "gpio134", "gpio135", "gpio138", "gpio139", +}; + +static const char *const pcie0_clk_req_n_groups[] =3D { + "gpio103", +}; + +static const char *const pcie0_rst_n_groups[] =3D { + "gpio102", +}; + +static const char *const pcie1_clk_req_n_groups[] =3D { + "gpio221", +}; + +static const char *const phase_flag_groups[] =3D { + "gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125", + "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175", + "gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185", + "gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204", + "gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214", + "gpio215", "gpio216", +}; + +static const char *const pll_bist_sync_groups[] =3D { + "gpio104", +}; + +static const char *const pll_clk_aux_groups[] =3D { + "gpio94", +}; + +static const char *const qdss_cti_groups[] =3D { + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83", + "gpio152", "gpio158", +}; + +static const char *const qlink_enable_groups[] =3D { + "gpio153", +}; + +static const char *const qlink_request_groups[] =3D { + "gpio152", +}; + +static const char *const qlink_wmss_groups[] =3D { + "gpio154", +}; + +static const char *const qspi_groups[] =3D { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const qspi_clk_groups[] =3D { + "gpio83", +}; + +static const char *const qspi_cs_groups[] =3D { + "gpio146", "gpio148", +}; + +static const char *const qup1_se0_groups[] =3D { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup1_se1_groups[] =3D { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const qup1_se2_groups[] =3D { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132", +}; + +static const char *const qup1_se3_groups[] =3D { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] =3D { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se5_groups[] =3D { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] =3D { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] =3D { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se0_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] =3D { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup2_se3_groups[] =3D { + "gpio97", "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char *const qup2_se4_l0_groups[] =3D { + "gpio208", +}; + +static const char *const qup2_se4_l1_groups[] =3D { + "gpio209", +}; + +static const char *const qup2_se4_l2_groups[] =3D { + "gpio208", +}; + +static const char *const qup2_se4_l3_groups[] =3D { + "gpio209", +}; + +static const char *const qup3_se0_l0_groups[] =3D { + "gpio64", +}; + +static const char *const qup3_se0_l1_groups[] =3D { + "gpio65", +}; + +static const char *const qup3_se0_l2_groups[] =3D { + "gpio64", +}; + +static const char *const qup3_se0_l3_groups[] =3D { + "gpio65", +}; + +static const char *const qup3_se1_groups[] =3D { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", +}; + +static const char *const qup3_se2_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const qup3_se3_groups[] =3D { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup3_se4_groups[] =3D { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup3_se5_groups[] =3D { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup4_se0_groups[] =3D { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup4_se1_groups[] =3D { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup4_se2_groups[] =3D { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup4_se3_l0_groups[] =3D { + "gpio121", +}; + +static const char *const qup4_se3_l1_groups[] =3D { + "gpio84", +}; + +static const char *const qup4_se3_l2_groups[] =3D { + "gpio121", +}; + +static const char *const qup4_se3_l3_groups[] =3D { + "gpio84", "gpio98", +}; + +static const char *const qup4_se4_l0_groups[] =3D { + "gpio161", +}; + +static const char *const qup4_se4_l1_groups[] =3D { + "gpio162", +}; + +static const char *const qup4_se4_l2_groups[] =3D { + "gpio161", +}; + +static const char *const qup4_se4_l3_groups[] =3D { + "gpio88", "gpio162", +}; + +static const char *const rng_rosc_groups[] =3D { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const sd_write_protect_groups[] =3D { + "gpio85", +}; + +static const char *const sdc4_clk_groups[] =3D { + "gpio83", +}; + +static const char *const sdc4_cmd_groups[] =3D { + "gpio148", +}; + +static const char *const sdc4_data_groups[] =3D { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const sys_throttle_groups[] =3D { + "gpio99", +}; + +static const char *const tb_trig_sdc_groups[] =3D { + "gpio88", "gpio146", +}; + +static const char *const tmess_rng_groups[] =3D { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const tsense_clm_groups[] =3D { + "gpio10", "gpio87", "gpio97", "gpio99", "gpio105", "gpio106", + "gpio159", +}; + +static const char *const tsense_pwm_groups[] =3D { + "gpio10", "gpio87", "gpio97", "gpio99", "gpio223", "gpio224", + "gpio225", +}; + +static const char *const uim0_clk_groups[] =3D { + "gpio127", +}; + +static const char *const uim0_data_groups[] =3D { + "gpio126", +}; + +static const char *const uim0_present_groups[] =3D { + "gpio129", +}; + +static const char *const uim0_reset_groups[] =3D { + "gpio128", +}; + +static const char *const uim1_clk_groups[] =3D { + "gpio37", "gpio55", "gpio71", "gpio131", +}; + +static const char *const uim1_data_groups[] =3D { + "gpio36", "gpio54", "gpio70", "gpio130", +}; + +static const char *const uim1_present_groups[] =3D { + "gpio133", +}; + +static const char *const uim1_reset_groups[] =3D { + "gpio39", "gpio56", "gpio72", "gpio132", +}; + +static const char *const usb0_hs_groups[] =3D { + "gpio79", +}; + +static const char *const usb_phy_groups[] =3D { + "gpio59", "gpio60", +}; + +static const char *const vfr_groups[] =3D { + "gpio146", "gpio151", +}; + +static const char *const vsense_trigger_mirnat_groups[] =3D { + "gpio59", +}; + +static const char *const wcn_sw_ctrl_groups[] =3D { + "gpio18", "gpio19", "gpio155", "gpio156", +}; + +static const struct pinfunction hawi_functions[] =3D { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_espmi_sclk), + MSM_PIN_FUNCTION(coex_espmi_sdata), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gnss_adc), + MSM_PIN_FUNCTION(host_rst), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2s0_data), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s1_data), + MSM_PIN_FUNCTION(i2s1_sck), + MSM_PIN_FUNCTION(i2s1_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0), + MSM_PIN_FUNCTION(mdp_esync1), + MSM_PIN_FUNCTION(mdp_esync2), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(modem_pps_in), + MSM_PIN_FUNCTION(modem_pps_out), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(nav_gpio4), + MSM_PIN_FUNCTION(nav_gpio5), + MSM_PIN_FUNCTION(nav_rffe), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_rst_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qlink_wmss), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4_l0), + MSM_PIN_FUNCTION(qup2_se4_l1), + MSM_PIN_FUNCTION(qup2_se4_l2), + MSM_PIN_FUNCTION(qup2_se4_l3), + MSM_PIN_FUNCTION(qup3_se0_l0), + MSM_PIN_FUNCTION(qup3_se0_l1), + MSM_PIN_FUNCTION(qup3_se0_l2), + MSM_PIN_FUNCTION(qup3_se0_l3), + MSM_PIN_FUNCTION(qup3_se1), + MSM_PIN_FUNCTION(qup3_se2), + MSM_PIN_FUNCTION(qup3_se3), + MSM_PIN_FUNCTION(qup3_se4), + MSM_PIN_FUNCTION(qup3_se5), + MSM_PIN_FUNCTION(qup4_se0), + MSM_PIN_FUNCTION(qup4_se1), + MSM_PIN_FUNCTION(qup4_se2), + MSM_PIN_FUNCTION(qup4_se3_l0), + MSM_PIN_FUNCTION(qup4_se3_l1), + MSM_PIN_FUNCTION(qup4_se3_l2), + MSM_PIN_FUNCTION(qup4_se3_l3), + MSM_PIN_FUNCTION(qup4_se4_l0), + MSM_PIN_FUNCTION(qup4_se4_l1), + MSM_PIN_FUNCTION(qup4_se4_l2), + MSM_PIN_FUNCTION(qup4_se4_l3), + MSM_PIN_FUNCTION(rng_rosc), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sys_throttle), + MSM_PIN_FUNCTION(tb_trig_sdc), + MSM_PIN_FUNCTION(tmess_rng), + MSM_PIN_FUNCTION(tsense_clm), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing = pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup hawi_groups[] =3D { + [0] =3D PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [1] =3D PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [2] =3D PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [3] =3D PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [4] =3D PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [5] =3D PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [6] =3D PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [7] =3D PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [8] =3D PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [9] =3D PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [10] =3D PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _,= _, _), + [11] =3D PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _), + [12] =3D PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _= ), + [13] =3D PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _= ), + [14] =3D PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _), + [15] =3D PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _,= _, _), + [16] =3D PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _), + [17] =3D PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _), + [18] =3D PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _), + [19] =3D PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _), + [20] =3D PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [21] =3D PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [22] =3D PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [23] =3D PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [24] =3D PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [27] =3D PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _), + [28] =3D PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] =3D PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] =3D PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio), + [31] =3D PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio), + [32] =3D PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [33] =3D PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [34] =3D PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [35] =3D PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [36] =3D PINGROUP(36, qup1_se4, uim1_data, ibi_i3c, _, _, _, _, _, _, _, = _), + [37] =3D PINGROUP(37, qup1_se4, uim1_clk, ibi_i3c, _, _, _, _, _, _, _, _= ), + [38] =3D PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _), + [39] =3D PINGROUP(39, qup1_se4, uim1_reset, _, _, _, _, _, _, _, _, _), + [40] =3D PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, = _), + [41] =3D PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, = _), + [42] =3D PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _), + [43] =3D PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _), + [44] =3D PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _= ), + [45] =3D PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _= ), + [46] =3D PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _), + [47] =3D PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _), + [48] =3D PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [49] =3D PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [50] =3D PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [51] =3D PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [52] =3D PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _), + [53] =3D PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _), + [54] =3D PINGROUP(54, qup1_se5, uim1_data, ddr_pxi, _, _, _, _, _, _, _, = _), + [55] =3D PINGROUP(55, qup1_se5, uim1_clk, ddr_pxi, _, _, _, _, _, _, _, _= ), + [56] =3D PINGROUP(56, qup1_se6, uim1_reset, _, _, _, _, _, _, _, _, _), + [57] =3D PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [58] =3D PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [59] =3D PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, = _, _, _, _, _), + [60] =3D PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _), + [61] =3D PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _), + [62] =3D PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [63] =3D PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [64] =3D PINGROUP(64, qup3_se0_l0, qup3_se0_l2, rng_rosc, tmess_rng, _, _= , _, _, _, _, _), + [65] =3D PINGROUP(65, qup3_se0_l1, qup3_se0_l3, rng_rosc, tmess_rng, _, _= , _, _, _, _, _), + [66] =3D PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _,= _, _), + [67] =3D PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _), + [68] =3D PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _), + [69] =3D PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _), + [70] =3D PINGROUP(70, i2chub0_se3, uim1_data, _, atest_usb, _, _, _, _, _= , _, _), + [71] =3D PINGROUP(71, i2chub0_se3, uim1_clk, _, atest_usb, _, _, _, _, _,= _, _), + [72] =3D PINGROUP(72, i2chub0_se4, uim1_reset, qdss_cti, _, atest_usb, _,= _, _, _, _, _), + [73] =3D PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _= , _, _, _, _, _), + [74] =3D PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [75] =3D PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [76] =3D PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [77] =3D PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, = _), + [78] =3D PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _), + [79] =3D PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _), + [80] =3D PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _), + [81] =3D PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _), + [82] =3D PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _= , _, _, _, _, _), + [83] =3D PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _,= _, _, _), + [84] =3D PINGROUP(84, qup4_se3_l1, qup4_se3_l3, rng_rosc, tmess_rng, _, _= , _, _, _, _, _), + [85] =3D PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _), + [86] =3D PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esyn= c1, gcc_gp, + _, _, _, _, _, _), + [87] =3D PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsyn= c5_out, + mdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _), + [88] =3D PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _,= _, _, _, _, _, _), + [89] =3D PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [90] =3D PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [91] =3D PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [92] =3D PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [93] =3D PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [94] =3D PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), + [95] =3D PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [96] =3D PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [97] =3D PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense= _pwm, _, _, + _, _, _, _), + [98] =3D PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, = _, _, _, _), + [99] =3D PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _= , _, _, _), + [100] =3D PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _= ), + [101] =3D PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] =3D PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _), + [103] =3D PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [104] =3D PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _), + [105] =3D PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [106] =3D PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _= , _, _), + [107] =3D PINGROUP(107, cci_i2c_sda, cci_timer, _, _, _, _, _, _, _, _, _= ), + [108] =3D PINGROUP(108, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [109] =3D PINGROUP(109, cci_i2c_sda, cci_async_in, _, _, _, _, _, _, _, _= , _), + [110] =3D PINGROUP(110, cci_i2c_scl, cci_async_in, _, _, _, _, _, _, _, _= , _), + [111] =3D PINGROUP(111, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [112] =3D PINGROUP(112, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [113] =3D PINGROUP(113, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [114] =3D PINGROUP(114, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [115] =3D PINGROUP(115, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [116] =3D PINGROUP(116, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [117] =3D PINGROUP(117, i2s1_sck, qup2_se2, phase_flag, _, _, _, _, _, _,= _, _), + [118] =3D PINGROUP(118, i2s1_data, qup2_se2, phase_flag, _, _, _, _, _, _= , _, _), + [119] =3D PINGROUP(119, i2s1_ws, qup2_se2, phase_flag, _, _, _, _, _, _, = _, _), + [120] =3D PINGROUP(120, i2s1_data, qup2_se2, audio_ext_mclk, audio_ref_cl= k, _, _, + _, _, _, _, _), + [121] =3D PINGROUP(121, audio_ext_mclk, qup4_se3_l0, qup4_se3_l2, _, _, _= , _, _, _, _, _), + [122] =3D PINGROUP(122, i2s0_sck, qup2_se3, _, _, _, _, _, _, _, _, _), + [123] =3D PINGROUP(123, i2s0_data, qup2_se3, _, phase_flag, _, _, _, _, _= , _, _), + [124] =3D PINGROUP(124, i2s0_data, qup2_se3, _, phase_flag, _, _, _, _, _= , _, _), + [125] =3D PINGROUP(125, i2s0_ws, qup2_se3, phase_flag, _, _, _, _, _, _, = _, _), + [126] =3D PINGROUP(126, uim0_data, atest_char, _, _, _, _, _, _, _, _, _), + [127] =3D PINGROUP(127, uim0_clk, atest_char, _, _, _, _, _, _, _, _, _), + [128] =3D PINGROUP(128, uim0_reset, atest_char, _, _, _, _, _, _, _, _, _= ), + [129] =3D PINGROUP(129, uim0_present, atest_usb, atest_char, _, _, _, _, = _, _, _, _), + [130] =3D PINGROUP(130, uim1_data, qup1_se2, gcc_gp, _, _, _, _, _, _, _,= _), + [131] =3D PINGROUP(131, uim1_clk, qup1_se2, gcc_gp, _, _, _, _, _, _, _, = _), + [132] =3D PINGROUP(132, uim1_reset, qup1_se2, gcc_gp, _, _, _, _, _, _, _= , _), + [133] =3D PINGROUP(133, uim1_present, atest_char, _, _, _, _, _, _, _, _,= _), + [134] =3D PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [135] =3D PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [136] =3D PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] =3D PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] =3D PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [139] =3D PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [140] =3D PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), + [141] =3D PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), + [142] =3D PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), + [143] =3D PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), + [144] =3D PINGROUP(144, coex_uart1_rx, coex_espmi_sclk, _, _, _, _, _, _,= _, _, _), + [145] =3D PINGROUP(145, coex_uart1_tx, coex_espmi_sdata, _, _, _, _, _, _= , _, _, _), + [146] =3D PINGROUP(146, _, vfr, nav_gpio4, tb_trig_sdc, qspi_cs, _, _, _,= _, _, _), + [147] =3D PINGROUP(147, _, nav_gpio5, sdc4_data, qspi, _, _, _, _, _, _, = _), + [148] =3D PINGROUP(148, nav_gpio2, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _= , _), + [149] =3D PINGROUP(149, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [150] =3D PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), + [151] =3D PINGROUP(151, nav_gpio1, vfr, modem_pps_in, modem_pps_out, _, _= , _, _, _, _, _), + [152] =3D PINGROUP(152, qlink_request, qdss_cti, _, _, _, _, _, _, _, _, = _), + [153] =3D PINGROUP(153, qlink_enable, _, _, _, _, _, _, _, _, _, _), + [154] =3D PINGROUP(154, qlink_wmss, _, _, _, _, _, _, _, _, _, _), + [155] =3D PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [156] =3D PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [157] =3D PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] =3D PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _), + [159] =3D PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [160] =3D PINGROUP(160, cci_timer, cci_i2c_scl, _, _, _, _, _, _, _, _, _= ), + [161] =3D PINGROUP(161, qup4_se4_l0, qup4_se4_l2, _, _, _, _, _, _, _, _,= _), + [162] =3D PINGROUP(162, qup4_se4_l1, qup4_se4_l3, _, _, _, _, _, _, _, _,= _), + [163] =3D PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio), + [164] =3D PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio), + [165] =3D PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), + [166] =3D PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), + [167] =3D PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), + [168] =3D PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), + [169] =3D PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [170] =3D PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [171] =3D PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [172] =3D PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [173] =3D PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [174] =3D PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio), + [175] =3D PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [176] =3D PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [177] =3D PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), + [178] =3D PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio), + [179] =3D PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [180] =3D PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [181] =3D PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [182] =3D PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio), + [183] =3D PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio), + [184] =3D PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [185] =3D PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [186] =3D PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), + [187] =3D PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), + [188] =3D PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio), + [189] =3D PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio), + [190] =3D PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), + [191] =3D PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), + [192] =3D PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [193] =3D PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio), + [194] =3D PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] =3D PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] =3D PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [197] =3D PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [198] =3D PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [199] =3D PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [200] =3D PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] =3D PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] =3D PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] =3D PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] =3D PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [205] =3D PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio), + [206] =3D PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [207] =3D PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [208] =3D PINGROUP(208, qup2_se4_l0, qup2_se4_l2, phase_flag, _, _, _, _,= _, _, _, egpio), + [209] =3D PINGROUP(209, qup2_se4_l1, qup2_se4_l3, _, _, _, _, _, _, _, _,= egpio), + [210] =3D PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _), + [211] =3D PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _), + [212] =3D PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] =3D PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] =3D PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [215] =3D PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [216] =3D PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [217] =3D PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio), + [218] =3D PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio), + [219] =3D PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _), + [220] =3D PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _), + [221] =3D PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [222] =3D PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _), + [223] =3D PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [224] =3D PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [225] =3D PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [226] =3D UFS_RESET(ufs_reset, 0xf1004, 0xf2000), + [227] =3D SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6), + [228] =3D SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3), + [229] =3D SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map hawi_pdc_map[] =3D { + { 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 1= 1, 109 }, + { 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 1= 9, 112 }, + { 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 3= 2, 127 }, + { 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 4= 8, 135 }, + { 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 6= 0, 139 }, + { 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 6= 8, 146 }, + { 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 8= 0, 156 }, + { 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 8= 7, 161 }, + { 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 9= 9, 111 }, + { 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 1= 23, 170 }, + { 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 1= 51, 174 }, + { 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 1= 65, 177 }, + { 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 1= 83, 183 }, + { 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 2= 03, 103 }, + { 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 2= 22, 189 }, + { 223, 190 }, { 224, 191 }, { 225, 192 }, +}; + +static const struct msm_pinctrl_soc_data hawi_tlmm =3D { + .pins =3D hawi_pins, + .npins =3D ARRAY_SIZE(hawi_pins), + .functions =3D hawi_functions, + .nfunctions =3D ARRAY_SIZE(hawi_functions), + .groups =3D hawi_groups, + .ngroups =3D ARRAY_SIZE(hawi_groups), + .ngpios =3D 227, + .wakeirq_map =3D hawi_pdc_map, + .nwakeirq_map =3D ARRAY_SIZE(hawi_pdc_map), + .egpio_func =3D 11, +}; + +static int hawi_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &hawi_tlmm); +} + +static const struct of_device_id hawi_tlmm_of_match[] =3D { + { .compatible =3D "qcom,hawi-tlmm", }, + {}, +}; + +static struct platform_driver hawi_tlmm_driver =3D { + .driver =3D { + .name =3D "hawi-tlmm", + .of_match_table =3D hawi_tlmm_of_match, + }, + .probe =3D hawi_tlmm_probe, +}; + +static int __init hawi_tlmm_init(void) +{ + return platform_driver_register(&hawi_tlmm_driver); +} +arch_initcall(hawi_tlmm_init); + +static void __exit hawi_tlmm_exit(void) +{ + platform_driver_unregister(&hawi_tlmm_driver); +} +module_exit(hawi_tlmm_exit); + +MODULE_DESCRIPTION("QTI Hawi TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match); --=20 2.53.0