From nobody Wed Apr 1 22:13:35 2026 Received: from fsn-vps-1.bereza.email (fsn-vps-1.bereza.email [162.55.44.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D51E93FB077; Wed, 1 Apr 2026 10:57:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.55.44.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775041023; cv=none; b=u6Y6kBOg3BpUA4qwqIJ1QKQFpPEhz2FaUUkd2PJPGx3aqPovNviwlryrW0dK1QMZ9342VzRbDX3B3d1Qu8Uo9ORsIiTAYUvI7JZv3pSqVLR8138enh750tQ1Bfd5ndgMpEacui9Ekp1G9LbF/q+mYkV4TJ/SEEk3hbZtne1gdHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775041023; c=relaxed/simple; bh=yt8u5bqU77K+5SN5B86I2/Ko4ach/FfUyB2CUoXPM+4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Gd39C8wlhrWFBbEeAtkNOE+YpPqlnyRKieKQlmwe6dEiE+Evfmk6U8podPCPZEXfCEY43X5IADoEkzoI1KZ3gWjR1jN3oeDJ4igNd31FMmMf2Co/CdxHR+RqjtPF9SemL6x/yP+vHboZIRMCLXvzDtQWGpAuOqUbwf7EWhw1pQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bereza.email; spf=pass smtp.mailfrom=bereza.email; dkim=pass (2048-bit key) header.d=bereza.email header.i=@bereza.email header.b=i7Qax5IU; arc=none smtp.client-ip=162.55.44.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bereza.email Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bereza.email Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bereza.email header.i=@bereza.email header.b="i7Qax5IU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=bereza.email; s=mail; t=1775041020; bh=yt8u5bqU77K+5SN5B86I2/Ko4ach/FfUyB2CUoXPM+4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i7Qax5IUL1uWUeQEfnwNrMPzVazEGhgV6zl6Dr52V0+hj/iRM9kpasG6J6AiUT+hT smcQgwebDmD/wRJwI4069JcmeHryskfpjZpmIhGRSFxcObLoe27b5rk3vZfbUVEL3H Frqw1is5Ib6uL2wD/Mj+9eIa2CaST4Qm2huH2O896tDccKHrzgQ2dI4+iAx6QODFTr x58Bjb+OFnzT/w8HiLHb6Ce2sgIjVqqnwmaleepTbS5yQ88VZM/kw8Vg61F8vAEC1T edEeLr9UZ7QeXEJV1xXvOQfRd7KIUjMMW5tcE1z5AFpKrY83gKX4eEIw+jQaHjZtNO 9BK1OMVsSu4cQ== Received: from [127.0.1.1] (pd95bbad8.dip0.t-ipconnect.de [217.91.186.216]) by fsn-vps-1.bereza.email (Postfix) with ESMTPSA id 212485DF95; Wed, 1 Apr 2026 12:57:00 +0200 (CEST) From: Alex Bereza Date: Wed, 01 Apr 2026 12:56:32 +0200 Subject: [PATCH v3 1/2] dmaengine: xilinx_dma: Fix CPU stall in xilinx_dma_poll_timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-fix-atomic-poll-timeout-regression-v3-1-85508f0aedde@bereza.email> References: <20260401-fix-atomic-poll-timeout-regression-v3-0-85508f0aedde@bereza.email> In-Reply-To: <20260401-fix-atomic-poll-timeout-regression-v3-0-85508f0aedde@bereza.email> To: Vinod Koul , Frank Li , Michal Simek , Geert Uytterhoeven , Ulf Hansson , Arnd Bergmann , Tony Lindgren , Kedareswara rao Appana Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bereza X-Mailer: b4 0.15.1 Currently when calling xilinx_dma_poll_timeout with delay_us=3D0 and a condition that is never fulfilled, the CPU busy-waits for prolonged time and the timeout triggers only with a massive delay causing a CPU stall. This happens due to a huge underestimation of wall clock time in poll_timeout_us_atomic. Commit 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_atomic()") changed the behavior to no longer use ktime_get at the expense of underestimation of wall clock time which appears to be very large for delay_us=3D0. Instead of timing out after approximately XILINX_DMA_LOOP_COUNT microseconds, the timeout takes XILINX_DMA_LOOP_COUNT * 1000 * (time that the overhead of the for loop in poll_timeout_us_atomic takes) which is in the range of several minutes for XILINX_DMA_LOOP_COUNT=3D1000000. Fix this by using a non-zero value for delay_us. Use delay_us=3D10 to keep the delay in the hot path of starting DMA transfers minimal but still avoid CPU stalls in case of unexpected hardware failures. One-off measurement with delay_us=3D0 causes the cpu to busy wait around 7 minutes in the timeout case. After applying this patch with delay_us=3D10 the measured timeout was 1053428 microseconds which is roughly equivalent to the expected 1000000 microseconds specified in XILINX_DMA_LOOP_COUNT. Add a constant XILINX_DMA_POLL_DELAY_US for delay_us value. Fixes: 9495f2648287 ("dmaengine: xilinx_vdma: Use readl_poll_timeout instea= d of do while loop's") Fixes: 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_a= tomic()") Signed-off-by: Alex Bereza --- drivers/dma/xilinx/xilinx_dma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 02a05f215614..345a738bab2c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -167,6 +167,8 @@ =20 /* Delay loop counter to prevent hardware failure */ #define XILINX_DMA_LOOP_COUNT 1000000 +/* Delay between polls (avoid a delay of 0 to prevent CPU stalls) */ +#define XILINX_DMA_POLL_DELAY_US 10 =20 /* AXI DMA Specific Registers/Offsets */ #define XILINX_DMA_REG_SRCDSTADDR 0x18 @@ -1332,7 +1334,8 @@ static int xilinx_dma_stop_transfer(struct xilinx_dma= _chan *chan) =20 /* Wait for the hardware to halt */ return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, - val & XILINX_DMA_DMASR_HALTED, 0, + val & XILINX_DMA_DMASR_HALTED, + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); } =20 @@ -1347,7 +1350,8 @@ static int xilinx_cdma_stop_transfer(struct xilinx_dm= a_chan *chan) u32 val; =20 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, - val & XILINX_DMA_DMASR_IDLE, 0, + val & XILINX_DMA_DMASR_IDLE, + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); } =20 @@ -1364,7 +1368,8 @@ static void xilinx_dma_start(struct xilinx_dma_chan *= chan) =20 /* Wait for the hardware to start */ err =3D xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, - !(val & XILINX_DMA_DMASR_HALTED), 0, + !(val & XILINX_DMA_DMASR_HALTED), + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); =20 if (err) { @@ -1780,7 +1785,8 @@ static int xilinx_dma_reset(struct xilinx_dma_chan *c= han) =20 /* Wait for the hardware to finish reset */ err =3D xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, - !(tmp & XILINX_DMA_DMACR_RESET), 0, + !(tmp & XILINX_DMA_DMACR_RESET), + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); =20 if (err) { --=20 2.53.0