From nobody Wed Apr 1 22:35:54 2026 Received: from fsn-vps-1.bereza.email (fsn-vps-1.bereza.email [162.55.44.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FA1D36CDF2; Wed, 1 Apr 2026 09:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.55.44.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775037497; cv=none; b=DyIjlejOdYVaDxs3sm7FH62jttyY1D/CpEoVvJ1qCPgS89iXBJ+0LlY7XfC21R46x/hGZ+KLRcPCbYMIK8Rn193ey++3UuuH8yQ22EcPbwwxbDBoIolG8XY0J84He9zmPmxEINH6NMaAshoGXslRCcLhA3jY7pOjNQvD6+KL74w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775037497; c=relaxed/simple; bh=Kl6JmqCrf42hfpt3PEtmRDalCUj2fSnXQP8BtsdNym0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bp68nBKWR/g4ihSacgRjpNcawXWKcUKS8tBP74YA67Sg0o+HMO2sRERNUs5r82T0Fasfsw3toB+O31v9q7fS2NKXtp6Xxn9HbimzXue3BYtZ8gdNj/0x/EMj9/uGGTdlfKXiDlxibSQxpU8l+Fg7KmoT+lo5I6FpxujVpfUt6Xc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bereza.email; spf=pass smtp.mailfrom=bereza.email; dkim=pass (2048-bit key) header.d=bereza.email header.i=@bereza.email header.b=lEMN2Vet; arc=none smtp.client-ip=162.55.44.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bereza.email Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bereza.email Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bereza.email header.i=@bereza.email header.b="lEMN2Vet" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=bereza.email; s=mail; t=1775037494; bh=Kl6JmqCrf42hfpt3PEtmRDalCUj2fSnXQP8BtsdNym0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lEMN2Vetn19zRwFR3/mmnYzbtt60PYOcpvEJCSlF2upw0QfiFB1uHFv4WjcBrcsIB WULJiugDTyk//DbvZtgKBrmHYm4m++VmDBduSz/URcKv2AUY0z6vPR/4ACbPMfhXHf 1Bcn7xHcndX2sTXMlBs9SsBxhlLG5mShYais9Wf0pVkb4U7O8W6KxXZUDLMUKr8sZo mXTN6VapiGmt5Pt2kbOj2+YGhisuB8vp+Qn3RGWazJN7TPC1mr68Sf8lqfRD8j92NH 3Fjn0FcxASqs/QjDFg3ldMIPWfwH2i5r/hjxQzzCq5/N5lkQmTyo8TqSK9NIK8l6wf Fy68n0AF0yl1w== Received: from [127.0.1.1] (pd95bbad8.dip0.t-ipconnect.de [217.91.186.216]) by fsn-vps-1.bereza.email (Postfix) with ESMTPSA id 377515DF95; Wed, 1 Apr 2026 11:58:14 +0200 (CEST) From: Alex Bereza Date: Wed, 01 Apr 2026 11:57:47 +0200 Subject: [PATCH v2 1/2] dmaengine: xilinx_dma: Fix CPU stall in xilinx_dma_poll_timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-fix-atomic-poll-timeout-regression-v2-1-68a265e3770f@bereza.email> References: <20260401-fix-atomic-poll-timeout-regression-v2-0-68a265e3770f@bereza.email> In-Reply-To: <20260401-fix-atomic-poll-timeout-regression-v2-0-68a265e3770f@bereza.email> To: Vinod Koul , Frank Li , Michal Simek , Geert Uytterhoeven , Ulf Hansson , Arnd Bergmann , Tony Lindgren , Kedareswara rao Appana Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bereza X-Mailer: b4 0.15.1 Currently when calling xilinx_dma_poll_timeout with delay_us=3D0 and a condition that is never fulfilled, the CPU busy-waits for prolonged time and the timeout triggers only with a massive delay causing a CPU stall. This happens due to a huge underestimation of wall clock time in poll_timeout_us_atomic. Commit 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_atomic()") changed the behavior to no longer use ktime_get at the expense of underestimation of wall clock time which appears to be very large for delay_us=3D0. Instead of timing out after approximately XILINX_DMA_LOOP_COUNT microseconds, the timeout takes XILINX_DMA_LOOP_COUNT * 1000 * (time that the overhead of the for loop in poll_timeout_us_atomic takes) which is in the range of several minutes for XILINX_DMA_LOOP_COUNT=3D1000000. Fix this by using a non-zero value for delay_us. Use delay_us=3D10 to keep the delay in the hot path of starting DMA transfers minimal but still avoid CPU stalls in case of unexpected hardware failures. One-off measurement with delay_us=3D0 causes the cpu to busy wait around 7 minutes in the timeout case. After applying this patch with delay_us=3D10 the measured timeout was 1053428 microseconds which is roughly equivalent to the expected 1000000 microseconds specified in XILINX_DMA_LOOP_COUNT. Add a constant XILINX_DMA_POLL_DELAY_US for delay_us value. Fixes: 9495f2648287 ("dmaengine: xilinx_vdma: Use readl_poll_timeout instea= d of do while loop's") Fixes: 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_a= tomic()") Signed-off-by: Alex Bereza --- drivers/dma/xilinx/xilinx_dma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 02a05f215614..345a738bab2c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -167,6 +167,8 @@ =20 /* Delay loop counter to prevent hardware failure */ #define XILINX_DMA_LOOP_COUNT 1000000 +/* Delay between polls (avoid a delay of 0 to prevent CPU stalls) */ +#define XILINX_DMA_POLL_DELAY_US 10 =20 /* AXI DMA Specific Registers/Offsets */ #define XILINX_DMA_REG_SRCDSTADDR 0x18 @@ -1332,7 +1334,8 @@ static int xilinx_dma_stop_transfer(struct xilinx_dma= _chan *chan) =20 /* Wait for the hardware to halt */ return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, - val & XILINX_DMA_DMASR_HALTED, 0, + val & XILINX_DMA_DMASR_HALTED, + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); } =20 @@ -1347,7 +1350,8 @@ static int xilinx_cdma_stop_transfer(struct xilinx_dm= a_chan *chan) u32 val; =20 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, - val & XILINX_DMA_DMASR_IDLE, 0, + val & XILINX_DMA_DMASR_IDLE, + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); } =20 @@ -1364,7 +1368,8 @@ static void xilinx_dma_start(struct xilinx_dma_chan *= chan) =20 /* Wait for the hardware to start */ err =3D xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, - !(val & XILINX_DMA_DMASR_HALTED), 0, + !(val & XILINX_DMA_DMASR_HALTED), + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); =20 if (err) { @@ -1780,7 +1785,8 @@ static int xilinx_dma_reset(struct xilinx_dma_chan *c= han) =20 /* Wait for the hardware to finish reset */ err =3D xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, - !(tmp & XILINX_DMA_DMACR_RESET), 0, + !(tmp & XILINX_DMA_DMACR_RESET), + XILINX_DMA_POLL_DELAY_US, XILINX_DMA_LOOP_COUNT); =20 if (err) { --=20 2.53.0 From nobody Wed Apr 1 22:35:54 2026 Received: from fsn-vps-1.bereza.email (fsn-vps-1.bereza.email [162.55.44.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B72036AB50; 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Wed, 1 Apr 2026 11:58:14 +0200 (CEST) From: Alex Bereza Date: Wed, 01 Apr 2026 11:57:48 +0200 Subject: [PATCH v2 2/2] dmaengine: xilinx_dma: Rename XILINX_DMA_LOOP_COUNT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-fix-atomic-poll-timeout-regression-v2-2-68a265e3770f@bereza.email> References: <20260401-fix-atomic-poll-timeout-regression-v2-0-68a265e3770f@bereza.email> In-Reply-To: <20260401-fix-atomic-poll-timeout-regression-v2-0-68a265e3770f@bereza.email> To: Vinod Koul , Frank Li , Michal Simek , Geert Uytterhoeven , Ulf Hansson , Arnd Bergmann , Tony Lindgren , Kedareswara rao Appana Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bereza X-Mailer: b4 0.15.1 Rename XILINX_DMA_LOOP_COUNT to XILINX_DMA_POLL_TIMEOUT_US because the former is incorrect. It is a timeout value for polling various register bits in microseconds. It is not a loop count. Signed-off-by: Alex Bereza --- drivers/dma/xilinx/xilinx_dma.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 345a738bab2c..253c27fd1a0e 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -165,8 +165,8 @@ #define XILINX_DMA_FLUSH_MM2S 2 #define XILINX_DMA_FLUSH_BOTH 1 =20 -/* Delay loop counter to prevent hardware failure */ -#define XILINX_DMA_LOOP_COUNT 1000000 +/* Timeout for polling various registers */ +#define XILINX_DMA_POLL_TIMEOUT_US 1000000 /* Delay between polls (avoid a delay of 0 to prevent CPU stalls) */ #define XILINX_DMA_POLL_DELAY_US 10 =20 @@ -1336,7 +1336,7 @@ static int xilinx_dma_stop_transfer(struct xilinx_dma= _chan *chan) return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, val & XILINX_DMA_DMASR_HALTED, XILINX_DMA_POLL_DELAY_US, - XILINX_DMA_LOOP_COUNT); + XILINX_DMA_POLL_TIMEOUT_US); } =20 /** @@ -1352,7 +1352,7 @@ static int xilinx_cdma_stop_transfer(struct xilinx_dm= a_chan *chan) return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, val & XILINX_DMA_DMASR_IDLE, XILINX_DMA_POLL_DELAY_US, - XILINX_DMA_LOOP_COUNT); + XILINX_DMA_POLL_TIMEOUT_US); } =20 /** @@ -1370,7 +1370,7 @@ static void xilinx_dma_start(struct xilinx_dma_chan *= chan) err =3D xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, !(val & XILINX_DMA_DMASR_HALTED), XILINX_DMA_POLL_DELAY_US, - XILINX_DMA_LOOP_COUNT); + XILINX_DMA_POLL_TIMEOUT_US); =20 if (err) { dev_err(chan->dev, "Cannot start channel %p: %x\n", @@ -1787,7 +1787,7 @@ static int xilinx_dma_reset(struct xilinx_dma_chan *c= han) err =3D xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, !(tmp & XILINX_DMA_DMACR_RESET), XILINX_DMA_POLL_DELAY_US, - XILINX_DMA_LOOP_COUNT); + XILINX_DMA_POLL_TIMEOUT_US); =20 if (err) { dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", --=20 2.53.0