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Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c | 282 +++++++++++++++++++++++++= ++++ 1 file changed, 282 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c b/drivers/phy/qualc= omm/phy-qcom-hdmi-28hpm.c index 720757f8f393..801e304801b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c +++ b/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c @@ -6,10 +6,13 @@ * Author: Rob Clark */ =20 +#include #include #include +#include =20 #include "phy-qcom-hdmi-preqmp.h" +#include "phy-qcom-uniphy.h" =20 #define REG_HDMI_8x74_ANA_CFG0 0x00000000 #define REG_HDMI_8x74_ANA_CFG1 0x00000004 @@ -31,8 +34,282 @@ #define REG_HDMI_8x74_BIST_PATN3 0x00000048 #define REG_HDMI_8x74_STATUS 0x0000005c =20 +#define HDMI_8974_VCO_MAX_FREQ 1800000000UL +#define HDMI_8974_VCO_MIN_FREQ 600000000UL + +#define HDMI_8974_COMMON_DIV 5 + +static inline void write16(u16 val, void __iomem *reg) +{ + writel(val & 0xff, reg); + writel(val >> 8, reg + 4); +} + +static inline void write24(u32 val, void __iomem *reg) +{ + writel(val & 0xff, reg); + writel((val >> 8) & 0xff, reg + 4); + writel(val >> 16, reg + 8); +} + +static inline u32 read24(void __iomem *reg) +{ + u32 val =3D readl(reg); + + val |=3D readl(reg + 4) << 8; + val |=3D readl(reg + 8) << 16; + + return val; +} + +static void qcom_uniphy_setup(void __iomem *base, unsigned int ref_freq, + bool sdm_mode, + bool ref_freq_mult_2, + bool dither, + unsigned int refclk_div, + unsigned int vco_freq) +{ + unsigned int int_ref_freq =3D ref_freq * (ref_freq_mult_2 ? 2 : 1); + unsigned int div_in_freq =3D vco_freq / refclk_div; + unsigned int dc_offset =3D div_in_freq / int_ref_freq - 1; + unsigned int sdm_freq_seed; + unsigned int val; + u64 tmp =3D div_in_freq % int_ref_freq; + + tmp *=3D 0x10000; + sdm_freq_seed =3D div_u64(tmp, int_ref_freq); + + val =3D FIELD_PREP(UNIPHY_PLL_REFCLK_DBLR, ref_freq_mult_2) | + FIELD_PREP(UNIPHY_PLL_REFCLK_DIV, refclk_div - 1); + writel(val, base + UNIPHY_PLL_REFCLK_CFG); + + if (sdm_mode) { + writel(0, base + UNIPHY_PLL_SDM_CFG0); + writel(FIELD_PREP(UNIPHY_PLL_SDM_DITHER_EN, dither) | dc_offset, + base + UNIPHY_PLL_SDM_CFG1); + write24(sdm_freq_seed, base + UNIPHY_PLL_SDM_CFG2); + } else { + writel(UNIPHY_PLL_SDM_BYP | dc_offset, base + UNIPHY_PLL_SDM_CFG0); + writel(0, base + UNIPHY_PLL_SDM_CFG1); + write24(0, base + UNIPHY_PLL_SDM_CFG2); + } + + write16(mult_frac(ref_freq, 5, 1000000), base + UNIPHY_PLL_CAL_CFG8); + write16(vco_freq / 16, base + UNIPHY_PLL_CAL_CFG10); +} + +static unsigned long qcom_uniphy_recalc(void __iomem *base, unsigned long = parent_rate) +{ + unsigned long rate; + u32 refclk_cfg; + u32 dc_offset; + u64 fraq_n; + u32 val; + + refclk_cfg =3D readl(base + UNIPHY_PLL_REFCLK_CFG); + if (refclk_cfg & UNIPHY_PLL_REFCLK_DBLR) + parent_rate *=3D 2; + + val =3D readl(base + UNIPHY_PLL_SDM_CFG0); + if (FIELD_GET(UNIPHY_PLL_SDM_BYP, val)) { + dc_offset =3D FIELD_GET(UNIPHY_PLL_SDM_BYP_DIV, val); + fraq_n =3D 0; + } else { + dc_offset =3D FIELD_GET(UNIPHY_PLL_SDM_DC_OFFSET, + readl(base + UNIPHY_PLL_SDM_CFG1)); + fraq_n =3D read24(base + UNIPHY_PLL_SDM_CFG2); + } + + rate =3D (dc_offset + 1) * parent_rate; + rate +=3D div_u64(fraq_n * parent_rate, 0x10000); + + rate *=3D FIELD_GET(UNIPHY_PLL_REFCLK_DIV, refclk_cfg) + 1; + + return rate; +} + +static const unsigned int qcom_hdmi_8974_divs[] =3D {1, 2, 4, 6}; + +static unsigned long qcom_hdmi_8974_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct qcom_hdmi_preqmp_phy *hdmi_phy =3D hw_clk_to_phy(hw); + u32 div_idx =3D readl(hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV1_CFG); + unsigned long rate =3D qcom_uniphy_recalc(hdmi_phy->pll_reg, parent_rate); + + return rate / HDMI_8974_COMMON_DIV / qcom_hdmi_8974_divs[div_idx & 0x3]; +} + +static int qcom_hdmi_8974_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long min_freq =3D HDMI_8974_VCO_MIN_FREQ / HDMI_8974_COMMON_DIV; + unsigned long max_freq =3D HDMI_8974_VCO_MAX_FREQ / HDMI_8974_COMMON_DIV; + + req->rate =3D clamp(req->rate, min_freq / 6, max_freq); + + return 0; +} + +static const struct clk_ops qcom_hdmi_8974_pll_ops =3D { + .recalc_rate =3D qcom_hdmi_8974_pll_recalc_rate, + .determine_rate =3D qcom_hdmi_8974_pll_determine_rate, +}; + +static int qcom_hdmi_msm8974_phy_find_div(unsigned long long pixclk) +{ + unsigned long long min_freq =3D HDMI_8974_VCO_MIN_FREQ / HDMI_8974_COMMON= _DIV; + int i; + + if (pixclk > HDMI_8974_VCO_MAX_FREQ / HDMI_8974_COMMON_DIV) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(qcom_hdmi_8974_divs); i++) { + if (pixclk >=3D min_freq / qcom_hdmi_8974_divs[i]) + return i; + } + + return -EINVAL; +} + +static int qcom_hdmi_msm8974_phy_pll_set_rate(struct qcom_hdmi_preqmp_phy = *hdmi_phy) +{ + unsigned long long pixclk =3D hdmi_phy->hdmi_opts.tmds_char_rate; + unsigned long vco_rate; + unsigned int div; + int div_idx =3D 0; + + div_idx =3D qcom_hdmi_msm8974_phy_find_div(pixclk); + if (WARN_ON(div_idx < 0)) + return div_idx; + + div =3D qcom_hdmi_8974_divs[div_idx]; + vco_rate =3D pixclk * HDMI_8974_COMMON_DIV * div; + + writel(0x81, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + + writel(0x01, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + writel(0x19, hdmi_phy->pll_reg + UNIPHY_PLL_VCOLPF_CFG); + writel(0x0e, hdmi_phy->pll_reg + UNIPHY_PLL_LPFR_CFG); + writel(0x20, hdmi_phy->pll_reg + UNIPHY_PLL_LPFC1_CFG); + writel(0x0d, hdmi_phy->pll_reg + UNIPHY_PLL_LPFC2_CFG); + + qcom_uniphy_setup(hdmi_phy->pll_reg, 19200000, true, true, true, 1, vco_r= ate); + + writel(0x10, hdmi_phy->pll_reg + UNIPHY_PLL_LKDET_CFG0); + writel(0x1a, hdmi_phy->pll_reg + UNIPHY_PLL_LKDET_CFG1); + writel(0x05, hdmi_phy->pll_reg + UNIPHY_PLL_LKDET_CFG2); + + writel(div_idx, hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV1_CFG); + + writel(0x00, hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV2_CFG); + writel(0x00, hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV3_CFG); + writel(0x01, hdmi_phy->pll_reg + UNIPHY_PLL_CAL_CFG2); + + writel(0x1f, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL0); + udelay(50); + + writel(0x0f, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL1); + writel(0x10, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0xdb, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG0); + writel(0x43, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG1); + if (pixclk =3D=3D 297000000) { + writel(0x06, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0x03, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG3); + } else if (pixclk =3D=3D 268500000) { + writel(0x05, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG3); + } else { + writel(0x02, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG3); + } + + writel(0x04, hdmi_phy->pll_reg + UNIPHY_PLL_VREG_CFG); + + writel(0xd0, hdmi_phy->phy_reg + REG_HDMI_8x74_DCC_CFG0); + writel(0x1a, hdmi_phy->phy_reg + REG_HDMI_8x74_DCC_CFG1); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG0); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG1); + + if (pixclk =3D=3D 268500000) + writel(0x11, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG2); + else + writel(0x02, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG2); + + writel(0x05, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG3); + udelay(200); + + return 0; +} + +static int qcom_hdmi_msm8974_phy_pll_enable(struct qcom_hdmi_preqmp_phy *h= dmi_phy) +{ + int ret; + unsigned long status; + + /* Global enable */ + writel(0x81, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + + /* Power up power gen */ + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL0); + udelay(350); + + /* PLL power up */ + writel(0x01, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(5); + + /* Power up PLL LDO */ + writel(0x03, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(350); + + /* PLL power up */ + writel(0x0f, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(350); + + /* Poll for PLL ready status */ + ret =3D readl_poll_timeout(hdmi_phy->pll_reg + UNIPHY_PLL_STATUS, + status, status & BIT(0), + 100, 2000); + if (ret) { + dev_warn(hdmi_phy->dev, "HDMI PLL not ready\n"); + goto err; + } + + udelay(350); + + /* Poll for PHY ready status */ + ret =3D readl_poll_timeout(hdmi_phy->phy_reg + REG_HDMI_8x74_STATUS, + status, status & BIT(0), + 100, 2000); + if (ret) { + dev_warn(hdmi_phy->dev, "HDMI PHY not ready\n"); + goto err; + } + + return 0; + +err: + writel(0, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(5); + writel(0, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + + return ret; +} + static int qcom_hdmi_msm8974_phy_power_on(struct qcom_hdmi_preqmp_phy *hdm= i_phy) { + int ret; + + ret =3D qcom_hdmi_msm8974_phy_pll_set_rate(hdmi_phy); + if (ret) + return ret; + + ret =3D qcom_hdmi_msm8974_phy_pll_enable(hdmi_phy); + if (ret) + return ret; + writel(0x1b, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG0); writel(0xf2, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG1); writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_BIST_CFG0); @@ -49,6 +326,10 @@ static int qcom_hdmi_msm8974_phy_power_off(struct qcom_= hdmi_preqmp_phy *hdmi_phy { writel(0x7f, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL0); =20 + writel(0, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(5); + writel(0, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + return 0; } =20 @@ -67,5 +348,6 @@ const struct qcom_hdmi_preqmp_cfg msm8974_hdmi_phy_cfg = =3D { .power_on =3D qcom_hdmi_msm8974_phy_power_on, .power_off =3D qcom_hdmi_msm8974_phy_power_off, =20 + .pll_ops =3D &qcom_hdmi_8974_pll_ops, .pll_parent =3D &msm8974_hdmi_pll_parent, }; --=20 2.47.3