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Tue, 31 Mar 2026 21:52:01 -0700 (PDT) From: Alexey Klimov Date: Wed, 01 Apr 2026 05:51:58 +0100 Subject: [PATCH v2 5/7] soc: samsung: exynos-pmu: add Exynos850 CPU hotplug support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-exynos850-cpuhotplug-v2-5-c5a760a3e259@linaro.org> References: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org> In-Reply-To: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexey Klimov X-Mailer: b4 0.14.3 Add cpuhotplug support for Exynos850 platforms. This SoC requires its own specific set of writes/updates to PMU and PMU interrupts generation block in order to put a CPU or a group of CPUs into a different sleep states or prepare these entities for a CPU_OFF or wake-up out of idle state or after CPU online. Without these writes/updates the CPU(s) wake-up or online fails. While at this, also add description of Exynos850 PMU registers. Signed-off-by: Alexey Klimov --- drivers/soc/samsung/Makefile | 2 +- drivers/soc/samsung/exynos-pmu.c | 1 + drivers/soc/samsung/exynos-pmu.h | 1 + drivers/soc/samsung/exynos850-pmu.c | 78 +++++++++++++++++++++++++= ++++ include/linux/soc/samsung/exynos-regs-pmu.h | 5 ++ 5 files changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 636a762608c9..7f544e3c1fcc 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -7,7 +7,7 @@ exynos_chipid-y +=3D exynos-chipid.o exynos-asv.o obj-$(CONFIG_EXYNOS_USI) +=3D exynos-usi.o =20 obj-$(CONFIG_EXYNOS_PMU) +=3D exynos_pmu.o -exynos_pmu-y +=3D exynos-pmu.o gs101-pmu.o +exynos_pmu-y +=3D exynos-pmu.o gs101-pmu.o exynos850-pmu.o =20 obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) +=3D exynos3250-pmu.o exynos4-pmu.o \ exynos5250-pmu.o exynos5420-pmu.o diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-= pmu.c index 4e5fcc01e5e0..daa870ba88f5 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -133,6 +133,7 @@ static const struct of_device_id exynos_pmu_of_device_i= ds[] =3D { .compatible =3D "samsung,exynos7-pmu", }, { .compatible =3D "samsung,exynos850-pmu", + .data =3D &exynos850_pmu_data, }, { /*sentinel*/ }, }; diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-= pmu.h index 186299a049a8..4202d3cd94c9 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -102,6 +102,7 @@ extern const struct exynos_pmu_data exynos5250_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; #endif extern const struct exynos_pmu_data gs101_pmu_data; +extern const struct exynos_pmu_data exynos850_pmu_data; =20 extern void pmu_raw_writel(u32 val, u32 offset); extern u32 pmu_raw_readl(u32 offset); diff --git a/drivers/soc/samsung/exynos850-pmu.c b/drivers/soc/samsung/exyn= os850-pmu.c new file mode 100644 index 000000000000..b3841547577a --- /dev/null +++ b/drivers/soc/samsung/exynos850-pmu.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2026 Linaro Ltd. + * + * Exynos850 PMU support + */ + +#include +#include +#include + +#include "exynos-pmu.h" + +static int exynos850_cpu_pmu_offline(struct exynos_pmu_context *pmu_contex= t, unsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + u32 this_cluster =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2); + u32 cluster_cpu =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + unsigned int cpuhint =3D smp_processor_id(); + u32 reg, mask; + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpuhint), + CPU_INFORM_C2); + + mask =3D BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, BIT(cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, + reg & mask); + + mask =3D (BIT(cpu + 8)); + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, + reg & mask); + + regmap_update_bits(pmu_context->pmureg, + EXYNOS850_CLUSTER_CPU_INT_EN(this_cluster, cluster_cpu), + 1 << 3, 1 << 3); + return 0; +} + +static int exynos850_cpu_pmu_online(struct exynos_pmu_context *pmu_context= , unsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + u32 this_cluster =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2); + u32 cluster_cpu =3D MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + unsigned int cpuhint =3D smp_processor_id(); + u32 reg, mask; + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpuhint), + CPU_INFORM_CLEAR); + + mask =3D BIT(cpu); + + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, (0 << cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®); + + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR, + reg & mask); + + regmap_update_bits(pmu_context->pmureg, + EXYNOS850_CLUSTER_CPU_INT_EN(this_cluster, cluster_cpu), + 1 << 3, 0 << 3); + return 0; +} + +const struct exynos_pmu_data exynos850_pmu_data =3D { + .pmu_cpuhp =3D true, + .cpu_pmu_offline =3D exynos850_cpu_pmu_offline, + .cpu_pmu_online =3D exynos850_cpu_pmu_online, +}; + diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 9c4d3da41dbf..93c4d724c8ea 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1015,6 +1015,11 @@ #define EXYNOS_GRP2_INTR_BID_UPEND (0x0208) #define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* Exynos850 PMU Alive */ +#define EXYNOS850_CPU_INFORM(cpu) (0x0860 + ((cpu) & 7) * 4) +#define EXYNOS850_CLUSTER_CPU_OFFSET(cl, cpu) (0x1000 + ((cl * 0x400) + ((= cpu) * 0x80))) +#define EXYNOS850_CLUSTER_CPU_INT_EN(cl, cpu) (EXYNOS850_CLUSTER_CPU_OFFSE= T(cl, cpu) + 0x44) + /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) --=20 2.51.0