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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82ca843bd8bsm13348329b3a.10.2026.04.01.03.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 03:24:56 -0700 (PDT) From: Wangao Wang Date: Wed, 01 Apr 2026 18:24:39 +0800 Subject: [PATCH v4 2/5] media: iris: Add hardware power on/off ops for X1P42100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-enable_iris_on_purwa-v4-2-ca784552a3e9@oss.qualcomm.com> References: <20260401-enable_iris_on_purwa-v4-0-ca784552a3e9@oss.qualcomm.com> In-Reply-To: <20260401-enable_iris_on_purwa-v4-0-ca784552a3e9@oss.qualcomm.com> To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775039081; l=3442; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=zsfwswlQ3m1rrBxd+JimmXRbTnuQ2uja3PrneN8KEM8=; b=ouAzJs/qhwyUO7AzX8pbS6btmScPc6Wi2z170U9E9YQVFG1WqjaOpBfMm03EQk/fS3WdMJ1zq 5FH0SLqRy3DCkZqcWoIDgETqN5o1VG7xUQm2tgz8RFPUoiquoHFe+MC X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDA5NCBTYWx0ZWRfX1RK3MpxhSm4a 4L09AcsPfsrzT20jFEZzfPV/AMGm70r03RbDGgNMTIgrxMsI1lsZDpk36RXp+14UnENQvyYB6mL l1ph/O7/4Mp30bfcsODDl4upLfVKngyHS8OsFMz8p7WMt+tPOmCEUyKhb6PZpGTyCM9trMM/Ph+ 4284/Lr3+Vlm5uvKGJIbeGa+x+kDNhWjX0+l0CEInc4Q1mIMxkV4xY1Cls2GOZXKUN4DwRTU8Jg Htc+yak1+SlPTDYJ0MqiHsAY+tyBHZ3i2ywPVhickytNzJPLI+2/Ugu4Brx/9eav5AMVXYVtyah rHQprKpK7fy5UcZEcEu1K/PfYCxbc1TgOeTtJ+1V2e2I39hfuU1fKtYg1gaWYII5Xps2nAmYGtX Qf5Z/eJHUTIE2ViB28P2gnTArwV18WxFxH0UU/zw7aQP0ugHBMvUUXK2jO0lIKcKN2RN7Jy6wrG 3Fjzxs5O4xzjL9RBErg== X-Proofpoint-GUID: _xnHmn-spCoRM2Wld7g5BRbJcmYvz20b X-Authority-Analysis: v=2.4 cv=YsQChoYX c=1 sm=1 tr=0 ts=69ccf27a cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=41qbuk9xwJvO8P9Mh2cA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: _xnHmn-spCoRM2Wld7g5BRbJcmYvz20b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_03,2026-04-01_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010094 On X1P42100 the Iris block has an extra BSE clock. Wire this clock into the power on/off sequence. The BSE clock is used to drive the Bin Stream Engine, which is a sub-block of the video codec hardware responsible for bitstream-level processing. It is required to be enabled separately from the core clock to ensure proper codec operation. Signed-off-by: Wangao Wang Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 46 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 2 files changed, 47 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index fe4423b951b1e9e31d06dffc69d18071cc985731..e6a62b3ca78efeefa2eed267636= 789a6b405689f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -71,6 +71,44 @@ static void iris_vpu3_power_off_hardware(struct iris_cor= e *core) iris_vpu_power_off_hw(core); } =20 +static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret) + goto err_disable_hw_clock; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); + if (ret) + goto err_disable_bse_hw_clock; + + return 0; + +err_disable_bse_hw_clock: + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) +{ + iris_vpu3_power_off_hardware(core); + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +} + static void iris_vpu33_power_off_hardware(struct iris_core *core) { bool handshake_done =3D false, handshake_busy =3D false; @@ -268,6 +306,14 @@ const struct vpu_ops iris_vpu3_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, }; =20 +const struct vpu_ops iris_vpu3_purwa_ops =3D { + .power_off_hw =3D iris_vpu3_purwa_power_off_hardware, + .power_on_hw =3D iris_vpu3_purwa_power_on_hw, + .power_off_controller =3D iris_vpu_power_off_controller, + .power_on_controller =3D iris_vpu_power_on_controller, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, +}; + const struct vpu_ops iris_vpu33_ops =3D { .power_off_hw =3D iris_vpu33_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f6dffc613b822341fb21e12de6b1395202f62cde..88a23cbdc06c5b38b4c8db67718= cbd538f0e0721 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; =20 extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu3_purwa_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; --=20 2.43.0