From nobody Wed Apr 1 20:46:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D02863FE674; Wed, 1 Apr 2026 10:56:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775041011; cv=none; b=qiQHM8x84pnmtRdLv21bp1hx1VtjnyavTJUohopSzMqwzEItprvFhIjAib9Bplpk5prXHsRgIp0XdTc1hhXBGqv5vHQKOSmH++lp6rMhzPxaZ5P9E7uwXFhX6KDvEFhh8igmI07jjIYYsgpUxoh+wd7Uoi2CN5KWhFpfv/7th84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775041011; c=relaxed/simple; bh=CoW9hSLLuoVLtxXARNfquX7TanxZeUf0AG9iM9ylRlw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=IWJVBEON4XO4oSYSSQBa3+7kDJwDMdoSsO7Shium/4Q06bp88Cbd5zsu2z90ajFIH1tV1NengnMg5iT6aAYWS/FodzKqhzNZdSUWjSwiQggQ35ODrwykTeRVavyWMDHmzrMHCzovI8pd3+ju6ebFDM6x8DoPq1UBcVDgWwUDjjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L1CN1NAz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L1CN1NAz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 69FD0C2BC9E; Wed, 1 Apr 2026 10:56:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775041011; bh=CoW9hSLLuoVLtxXARNfquX7TanxZeUf0AG9iM9ylRlw=; h=From:Date:Subject:To:Cc:Reply-To:From; b=L1CN1NAzGL9nmOPFWQp2Xh4/Lok1yqnmk5e4lRoE+6iB8cnl/Y1VCV6+MEAZejQJe miLJ8qIkjhcOly7UVsbGQGw/yMZ1q4k54f9wCsMVdhqCSuxvExFCefQ8KLMZENjcyw gAqOGGYh83t/o7eoM0rpIGFOptDiJus1AaKZhqnzgZL5vWh3h34hb9W0Fq83WufhsP KnPkM6tTsHN7qMlvIv37RrPeU0XLGp6xE9isPRoOzXtYs6P/tzbZDWRZ558Oi2xwt8 3BBWbu2nXntURwThgdFOV/jezLOBD4Pckm+tS8ud/eEsXC/+wH5P+JfrrV8ebChCt+ CVemnUB9Pd2Ew== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E372D35162; Wed, 1 Apr 2026 10:56:51 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Wed, 01 Apr 2026 13:56:48 +0300 Subject: [PATCH v2] iio: adc: ad4695: Fix call ordering in offload buffer postenable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260401-ad4696-fix-v2-1-2480b9a30749@analog.com> X-B4-Tracking: v=1; b=H4sIAO/5zGkC/22MQQ7CIBAAv9LsWQxLgYAn/2F6QLq2JAoGDNE0/ F3s2eNMMrNBoRyowGnYIFMNJaTYQRwG8KuLC7EwdwbBhebjyJmbpbaa3cKbodFWKWe8QoQePDN 1vc8uU+c1lFfKn/1d8Wf/bioyZGQkktVS4VWcXXT3tBx9esDUWvsCCtavFqUAAAA= X-Change-ID: 20260330-ad4696-fix-186955a8c511 To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Andy Shevchenko Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775041007; l=3768; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=pmd7DXpg+W48mt7EX681vGeYH0zmSrEeahfH1uvhrOc=; b=AteRS/37NSqfXWYdQ/bHxM0GXDUoX1o68LnrWkoPfyhEW5kiCIZiBEqLzy+SlufivqtxrVX5M N0eGcccUp1EABrUGgcT0IoExqjy5Unu+qZ7DRmnYVJjn9EGhGIB0nyR X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau ad4695_enter_advanced_sequencer_mode() was called after spi_offload_trigger_enable(). That is wrong because ad4695_enter_advanced_sequencer_mode() issues regular SPI transfers to put the ADC into advanced sequencer mode, and spi_offload_trigger_enable() enables the PWM trigger that drives CNV. Once the PWM is running, CNV pulses start arriving and the offload engine owns the SPI bus; any concurrent regular SPI transfer produces undefined behaviour. Fix this by calling ad4695_enter_advanced_sequencer_mode() before spi_offload_trigger_enable(), so the ADC is fully configured before the first CNV pulse can occur. This is consistent with the same constraint that already applies to the BUSY_GP_EN write above it. Update the error unwind labels accordingly: add err_exit_conversion_mode so that a failure of spi_offload_trigger_enable() correctly exits conversion mode before clearing BUSY_GP_EN. Fixes: f09f140e3ea8 ("iio: adc: ad4695: Add support for SPI offload") Reviewed-by: Nuno S=C3=A1 Signed-off-by: Radu Sabau --- ad4695_enter_advanced_sequencer_mode() issues regular SPI transfers to configure the ADC. These must complete before spi_offload_trigger_enable() enables the PWM/CNV trigger, because once CNV pulses are live the offload engine owns the SPI bus. This fixes the call ordering and updates the error unwind path accordingly. --- Changes in v2: - Reword commit message to explain the correct bus-ownership invariant directly, without reference to the HDL bug that exposed it. - Remove unnecessary comment since the error path changed. - Link to v1: https://lore.kernel.org/r/20260330-ad4696-fix-v1-1-e841e96451= b2@analog.com --- drivers/iio/adc/ad4695.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/ad4695.c b/drivers/iio/adc/ad4695.c index cda419638d9a..4471acd6fd5f 100644 --- a/drivers/iio/adc/ad4695.c +++ b/drivers/iio/adc/ad4695.c @@ -876,14 +876,14 @@ static int ad4695_offload_buffer_postenable(struct ii= o_dev *indio_dev) if (ret) goto err_unoptimize_message; =20 - ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, - &config); + ret =3D ad4695_enter_advanced_sequencer_mode(st, num_slots); if (ret) goto err_disable_busy_output; =20 - ret =3D ad4695_enter_advanced_sequencer_mode(st, num_slots); + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &config); if (ret) - goto err_offload_trigger_disable; + goto err_exit_conversion_mode; =20 mutex_lock(&st->cnv_pwm_lock); pwm_get_state(st->cnv_pwm, &state); @@ -895,22 +895,15 @@ static int ad4695_offload_buffer_postenable(struct ii= o_dev *indio_dev) ret =3D pwm_apply_might_sleep(st->cnv_pwm, &state); mutex_unlock(&st->cnv_pwm_lock); if (ret) - goto err_offload_exit_conversion_mode; + goto err_trigger_disable; =20 return 0; =20 -err_offload_exit_conversion_mode: - /* - * We have to unwind in a different order to avoid triggering offload. - * ad4695_exit_conversion_mode() triggers a conversion, so it has to be - * done after spi_offload_trigger_disable(). - */ +err_trigger_disable: spi_offload_trigger_disable(st->offload, st->offload_trigger); - ad4695_exit_conversion_mode(st); - goto err_disable_busy_output; =20 -err_offload_trigger_disable: - spi_offload_trigger_disable(st->offload, st->offload_trigger); +err_exit_conversion_mode: + ad4695_exit_conversion_mode(st); =20 err_disable_busy_output: regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE, --- base-commit: 11439c4635edd669ae435eec308f4ab8a0804808 change-id: 20260330-ad4696-fix-186955a8c511 Best regards, --=20 Radu Sabau