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Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 7/7] powercap: intel_rapl: Consolidate PL4 and PMU support flags into rapl_defaults Date: Tue, 31 Mar 2026 14:19:50 -0700 Message-ID: <20260331211950.3329932-8-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, PL4 and MSR-based RAPL PMU support are detected using separate CPU ID tables (pl4_support_ids and pmu_support_ids) in the MSR driver probe path. This creates a maintenance burden since adding a new CPU requires updates in two places: the rapl_ids table and one or both of these capability tables. Consolidate PL4 and PMU capability information directly into struct rapl_defaults by adding msr_pl4_support and msr_pmu_support flags. This allows per-CPU capability to be expressed in a single place alongside other per-CPU defaults, eliminating the duplicate CPU ID tables entirely. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Acked-by: Srinivas Pandruvada Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_msr.c | 83 ++++++++++++++----------------- include/linux/intel_rapl.h | 2 + 2 files changed, 38 insertions(+), 47 deletions(-) diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index cfb35973f0b5..a34543e66446 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -216,33 +216,6 @@ static int rapl_msr_write_raw(int cpu, struct reg_acti= on *ra) return ra->err; } =20 -/* List of verified CPUs. */ -static const struct x86_cpu_id pl4_support_ids[] =3D { - X86_MATCH_VFM(INTEL_ICELAKE_L, NULL), - X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), - X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL), - X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), - X86_MATCH_VFM(INTEL_METEORLAKE, NULL), - X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL), - X86_MATCH_VFM(INTEL_ARROWLAKE_U, NULL), - X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL), - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), - X86_MATCH_VFM(INTEL_NOVALAKE, NULL), - X86_MATCH_VFM(INTEL_NOVALAKE_L, NULL), - {} -}; - -/* List of MSR-based RAPL PMU support CPUs */ -static const struct x86_cpu_id pmu_support_ids[] =3D { - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), - {} -}; - static int rapl_check_unit_atom(struct rapl_domain *rd) { struct reg_action ra; @@ -420,6 +393,23 @@ static const struct rapl_defaults rapl_defaults_amd = =3D { .check_unit =3D rapl_default_check_unit, }; =20 +static const struct rapl_defaults rapl_defaults_core_pl4 =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, + .msr_pl4_support =3D 1, +}; + +static const struct rapl_defaults rapl_defaults_core_pl4_pmu =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, + .msr_pl4_support =3D 1, + .msr_pmu_support =3D 1, +}; + static const struct x86_cpu_id rapl_ids[] =3D { X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), @@ -443,35 +433,35 @@ static const struct x86_cpu_id rapl_ids[] =3D { X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core_pl4_pmu), + X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core_pl4_pmu), + X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), =20 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), @@ -498,7 +488,6 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_ids); =20 static int rapl_msr_probe(struct platform_device *pdev) { - const struct x86_cpu_id *id =3D x86_match_cpu(pl4_support_ids); int ret; =20 switch (boot_cpu_data.x86_vendor) { @@ -518,16 +507,16 @@ static int rapl_msr_probe(struct platform_device *pde= v) rapl_msr_priv->defaults =3D (const struct rapl_defaults *)pdev->dev.platf= orm_data; rapl_msr_priv->rpi =3D rpi_msr; =20 - if (id) { + if (rapl_msr_priv->defaults->msr_pl4_support) { rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |=3D BIT(POWER_LIMIT4); rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4].msr =3D MSR_VR_CURRENT_CONFIG; - pr_info("PL4 support detected.\n"); + pr_info("PL4 support detected (updated).\n"); } =20 - if (x86_match_cpu(pmu_support_ids)) { + if (rapl_msr_priv->defaults->msr_pmu_support) { rapl_msr_pmu =3D true; - pr_info("MSR-based RAPL PMU support enabled\n"); + pr_info("MSR-based RAPL PMU support enabled (updated)\n"); } =20 rapl_msr_priv->control_type =3D powercap_register_control_type(NULL, "int= el-rapl", NULL); diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h index 01f290de3586..328004f605c3 100644 --- a/include/linux/intel_rapl.h +++ b/include/linux/intel_rapl.h @@ -135,6 +135,8 @@ struct rapl_defaults { unsigned int dram_domain_energy_unit; unsigned int psys_domain_energy_unit; bool spr_psys_bits; + bool msr_pl4_support; + bool msr_pmu_support; }; =20 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ --=20 2.43.0