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Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/7] powercap: intel_rapl: Move MSR default settings into MSR interface driver Date: Tue, 31 Mar 2026 14:19:44 -0700 Message-ID: <20260331211950.3329932-2-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MSR-specific RAPL defaults differ from those used by the TPMI interface. The MMIO and MSR interfaces shared the same rapl_defaults pointer in the common driver, but MMIO does not require the CPU-specific variations needed by MSR. Keeping these in the common driver adds unnecessary complexity and MSR-specific initialization. Move MSR defaults and CPU matching into the MSR interface driver. Moves Acked-by: Srinivas Pandruvada ----- * Move rapl_check_unit_atom(), set_floor_freq_atom(), and rapl_compute_time_window_atom() into intel_rapl_msr.c. * Move MSR unit-field GENMASK definitions and local constants. * Move all MSR-related rapl_defaults tables and the CPU-ID matching logic (rapl_ids[]) into the MSR driver. * Move iosf_mbi dependencies (floor-frequency control and related MBI register definitions) as they are MSR-platform specific. Modifications ------------- * Replace the common driver's platform-device manual alloc/add sequence with platform_device_register_data() in the MSR driver to pass matching rapl_defaults as platform_data. * Update MSR driver probe to assign pdev->dev.platform_data to priv->defaults. * Update Atom helper functions to use rp->lead_cpu directly for MSR reads/writes instead of the generic get_rid(). * Update Atom floor frequency logic to access defaults via the package private data pointer. * Convert MSR device creation from fs_initcall() to module_init(). This preserves existing enumeration behavior as the driver was already using module_init(). * Since rapl_ids need to exist after boot, remove __initconst specifier. No functional changes are expected. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 228 +----------------------- drivers/powercap/intel_rapl_msr.c | 250 ++++++++++++++++++++++++++- 2 files changed, 250 insertions(+), 228 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index e099514e6c56..1e8146283009 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -28,7 +28,6 @@ =20 #include #include -#include #include =20 /* bitmasks for RAPL MSRs, used by primitive access functions */ @@ -212,8 +211,6 @@ static int get_pl_prim(struct rapl_domain *rd, int pl, = enum pl_prims prim) #define power_zone_to_rapl_domain(_zone) \ container_of(_zone, struct rapl_domain, power_zone) =20 -static const struct rapl_defaults *defaults_msr; - static const struct rapl_defaults *get_defaults(struct rapl_package *rp) { return rp->priv->defaults; @@ -759,7 +756,6 @@ static int rapl_config(struct rapl_package *rp) /* MMIO I/F shares the same register layout as MSR registers */ case RAPL_IF_MMIO: case RAPL_IF_MSR: - rp->priv->defaults =3D defaults_msr; rp->priv->rpi =3D (void *)rpi_msr; break; case RAPL_IF_TPMI: @@ -947,34 +943,6 @@ int rapl_default_check_unit(struct rapl_domain *rd) } EXPORT_SYMBOL_NS_GPL(rapl_default_check_unit, "INTEL_RAPL"); =20 -static int rapl_check_unit_atom(struct rapl_domain *rd) -{ - struct reg_action ra; - u32 value; - - ra.reg =3D rd->regs[RAPL_DOMAIN_REG_UNIT]; - ra.mask =3D ~0; - if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) { - pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", - ra.reg.val, rd->rp->name, rd->name); - return -ENODEV; - } - - value =3D (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; - rd->energy_unit =3D ENERGY_UNIT_SCALE * (1ULL << value); - - value =3D (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; - rd->power_unit =3D (1ULL << value) * MILLIWATT_PER_WATT; - - value =3D (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; - rd->time_unit =3D USEC_PER_SEC >> value; - - pr_debug("Atom %s:%s energy=3D%dpJ, time=3D%dus, power=3D%duW\n", - rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); - - return 0; -} - static void power_limit_irq_save_cpu(void *info) { u32 l, h =3D 0; @@ -1055,30 +1023,6 @@ void rapl_default_set_floor_freq(struct rapl_domain = *rd, bool mode) } EXPORT_SYMBOL_NS_GPL(rapl_default_set_floor_freq, "INTEL_RAPL"); =20 -static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) -{ - static u32 power_ctrl_orig_val; - const struct rapl_defaults *defaults =3D get_defaults(rd->rp); - u32 mdata; - - if (!defaults->floor_freq_reg_addr) { - pr_err("Invalid floor frequency config register\n"); - return; - } - - if (!power_ctrl_orig_val) - iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, - defaults->floor_freq_reg_addr, - &power_ctrl_orig_val); - mdata =3D power_ctrl_orig_val; - if (enable) { - mdata &=3D ~GENMASK(14, 8); - mdata |=3D BIT(8); - } - iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, - defaults->floor_freq_reg_addr, mdata); -} - u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bo= ol to_raw) { u64 f, y; /* fraction and exp. used for time unit */ @@ -1112,149 +1056,6 @@ u64 rapl_default_compute_time_window(struct rapl_do= main *rd, u64 value, bool to_ } EXPORT_SYMBOL_NS_GPL(rapl_default_compute_time_window, "INTEL_RAPL"); =20 -static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, - bool to_raw) -{ - if (to_raw) - return div64_u64(value, rd->time_unit); - - /* - * Atom time unit encoding is straight forward val * time_unit, - * where time_unit is default to 1 sec. Never 0. - */ - return (value) ? value * rd->time_unit : rd->time_unit; -} - -static const struct rapl_defaults rapl_defaults_core =3D { - .floor_freq_reg_addr =3D 0, - .check_unit =3D rapl_default_check_unit, - .set_floor_freq =3D rapl_default_set_floor_freq, - .compute_time_window =3D rapl_default_compute_time_window, -}; - -static const struct rapl_defaults rapl_defaults_hsw_server =3D { - .check_unit =3D rapl_default_check_unit, - .set_floor_freq =3D rapl_default_set_floor_freq, - .compute_time_window =3D rapl_default_compute_time_window, - .dram_domain_energy_unit =3D 15300, -}; - -static const struct rapl_defaults rapl_defaults_spr_server =3D { - .check_unit =3D rapl_default_check_unit, - .set_floor_freq =3D rapl_default_set_floor_freq, - .compute_time_window =3D rapl_default_compute_time_window, - .psys_domain_energy_unit =3D NANOJOULE_PER_JOULE, - .spr_psys_bits =3D true, -}; - -static const struct rapl_defaults rapl_defaults_byt =3D { - .floor_freq_reg_addr =3D IOSF_CPU_POWER_BUDGET_CTL_BYT, - .check_unit =3D rapl_check_unit_atom, - .set_floor_freq =3D set_floor_freq_atom, - .compute_time_window =3D rapl_compute_time_window_atom, -}; - -static const struct rapl_defaults rapl_defaults_tng =3D { - .floor_freq_reg_addr =3D IOSF_CPU_POWER_BUDGET_CTL_TNG, - .check_unit =3D rapl_check_unit_atom, - .set_floor_freq =3D set_floor_freq_atom, - .compute_time_window =3D rapl_compute_time_window_atom, -}; - -static const struct rapl_defaults rapl_defaults_ann =3D { - .floor_freq_reg_addr =3D 0, - .check_unit =3D rapl_check_unit_atom, - .set_floor_freq =3D NULL, - .compute_time_window =3D rapl_compute_time_window_atom, -}; - -static const struct rapl_defaults rapl_defaults_cht =3D { - .floor_freq_reg_addr =3D 0, - .check_unit =3D rapl_check_unit_atom, - .set_floor_freq =3D NULL, - .compute_time_window =3D rapl_compute_time_window_atom, -}; - -static const struct rapl_defaults rapl_defaults_amd =3D { - .check_unit =3D rapl_default_check_unit, -}; - -static const struct x86_cpu_id rapl_ids[] __initconst =3D { - X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), - - X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), - - X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), - - X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), - - X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), - X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), - X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), - X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), - X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), - X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), - - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), - X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann), - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), - - X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), - X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), - - X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), - X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), - X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), - X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), - {} -}; -MODULE_DEVICE_TABLE(x86cpu, rapl_ids); - /* Read once for all raw primitive data for domains */ static void rapl_update_domain_data(struct rapl_package *rp) { @@ -2266,40 +2067,13 @@ static struct notifier_block rapl_pm_notifier =3D { .notifier_call =3D rapl_pm_callback, }; =20 -static struct platform_device *rapl_msr_platdev; - static int __init rapl_init(void) { - const struct x86_cpu_id *id; - int ret; - - id =3D x86_match_cpu(rapl_ids); - if (id) { - defaults_msr =3D (const struct rapl_defaults *)id->driver_data; - - rapl_msr_platdev =3D platform_device_alloc("intel_rapl_msr", 0); - if (!rapl_msr_platdev) - return -ENOMEM; - - ret =3D platform_device_add(rapl_msr_platdev); - if (ret) { - platform_device_put(rapl_msr_platdev); - return ret; - } - } - - ret =3D register_pm_notifier(&rapl_pm_notifier); - if (ret && rapl_msr_platdev) { - platform_device_del(rapl_msr_platdev); - platform_device_put(rapl_msr_platdev); - } - - return ret; + return register_pm_notifier(&rapl_pm_notifier); } =20 static void __exit rapl_exit(void) { - platform_device_unregister(rapl_msr_platdev); unregister_pm_notifier(&rapl_pm_notifier); } =20 diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index 9cd6a241df51..b7c10ed75d69 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -21,15 +21,33 @@ #include #include #include +#include +#include =20 #include #include +#include #include =20 /* Local defines */ #define MSR_PLATFORM_POWER_LIMIT 0x0000065C #define MSR_VR_CURRENT_CONFIG 0x00000601 =20 +#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit= */ + +#define POWER_UNIT_OFFSET 0x00 +#define POWER_UNIT_MASK GENMASK(3, 0) + +#define ENERGY_UNIT_OFFSET 0x08 +#define ENERGY_UNIT_MASK GENMASK(12, 8) + +#define TIME_UNIT_OFFSET 0x10 +#define TIME_UNIT_MASK GENMASK(19, 16) + +/* Sideband MBI registers */ +#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02 +#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF + /* private data for RAPL MSR Interface */ static struct rapl_if_priv *rapl_msr_priv; =20 @@ -185,6 +203,201 @@ static const struct x86_cpu_id pmu_support_ids[] =3D { {} }; =20 +static int rapl_check_unit_atom(struct rapl_domain *rd) +{ + struct reg_action ra; + u32 value; + + ra.reg =3D rd->regs[RAPL_DOMAIN_REG_UNIT]; + ra.mask =3D ~0; + if (rapl_msr_read_raw(rd->rp->lead_cpu, &ra, false)) { + pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", + ra.reg.val, rd->rp->name, rd->name); + return -ENODEV; + } + + value =3D (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; + rd->energy_unit =3D ENERGY_UNIT_SCALE * (1ULL << value); + + value =3D (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; + rd->power_unit =3D (1ULL << value) * MILLIWATT_PER_WATT; + + value =3D (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; + rd->time_unit =3D USEC_PER_SEC >> value; + + pr_debug("Atom %s:%s energy=3D%dpJ, time=3D%dus, power=3D%duW\n", + rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); + + return 0; +} + +static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) +{ + static u32 power_ctrl_orig_val; + const struct rapl_defaults *defaults =3D rd->rp->priv->defaults; + u32 mdata; + + if (!defaults->floor_freq_reg_addr) { + pr_err("Invalid floor frequency config register\n"); + return; + } + + if (!power_ctrl_orig_val) + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, + defaults->floor_freq_reg_addr, + &power_ctrl_orig_val); + mdata =3D power_ctrl_orig_val; + if (enable) { + mdata &=3D ~GENMASK(14, 8); + mdata |=3D BIT(8); + } + iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, + defaults->floor_freq_reg_addr, mdata); +} + +static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, + bool to_raw) +{ + if (to_raw) + return div64_u64(value, rd->time_unit); + + /* + * Atom time unit encoding is straight forward val * time_unit, + * where time_unit is default to 1 sec. Never 0. + */ + return value ? value * rd->time_unit : rd->time_unit; +} + +static const struct rapl_defaults rapl_defaults_core =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, +}; + +static const struct rapl_defaults rapl_defaults_hsw_server =3D { + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, + .dram_domain_energy_unit =3D 15300, +}; + +static const struct rapl_defaults rapl_defaults_spr_server =3D { + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, + .psys_domain_energy_unit =3D NANOJOULE_PER_JOULE, + .spr_psys_bits =3D true, +}; + +static const struct rapl_defaults rapl_defaults_byt =3D { + .floor_freq_reg_addr =3D IOSF_CPU_POWER_BUDGET_CTL_BYT, + .check_unit =3D rapl_check_unit_atom, + .set_floor_freq =3D set_floor_freq_atom, + .compute_time_window =3D rapl_compute_time_window_atom, +}; + +static const struct rapl_defaults rapl_defaults_tng =3D { + .floor_freq_reg_addr =3D IOSF_CPU_POWER_BUDGET_CTL_TNG, + .check_unit =3D rapl_check_unit_atom, + .set_floor_freq =3D set_floor_freq_atom, + .compute_time_window =3D rapl_compute_time_window_atom, +}; + +static const struct rapl_defaults rapl_defaults_ann =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_check_unit_atom, + .set_floor_freq =3D NULL, + .compute_time_window =3D rapl_compute_time_window_atom, +}; + +static const struct rapl_defaults rapl_defaults_cht =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_check_unit_atom, + .set_floor_freq =3D NULL, + .compute_time_window =3D rapl_compute_time_window_atom, +}; + +static const struct rapl_defaults rapl_defaults_amd =3D { + .check_unit =3D rapl_default_check_unit, +}; + +static const struct x86_cpu_id rapl_ids[] =3D { + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), + + X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), + + X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), + X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), + + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), + + X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), + X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), + X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), + X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, rapl_ids); + static int rapl_msr_probe(struct platform_device *pdev) { const struct x86_cpu_id *id =3D x86_match_cpu(pl4_support_ids); @@ -204,6 +417,7 @@ static int rapl_msr_probe(struct platform_device *pdev) } rapl_msr_priv->read_raw =3D rapl_msr_read_raw; rapl_msr_priv->write_raw =3D rapl_msr_write_raw; + rapl_msr_priv->defaults =3D (const struct rapl_defaults *)pdev->dev.platf= orm_data; =20 if (id) { rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |=3D BIT(POWER_LIMIT4); @@ -258,7 +472,41 @@ static struct platform_driver intel_rapl_msr_driver = =3D { }, }; =20 -module_platform_driver(intel_rapl_msr_driver); +static struct platform_device *rapl_msr_platdev; + +static int intel_rapl_msr_init(void) +{ + const struct rapl_defaults *def; + const struct x86_cpu_id *id; + int ret; + + ret =3D platform_driver_register(&intel_rapl_msr_driver); + if (ret) + return ret; + + /* Create the MSR RAPL platform device for supported platforms */ + id =3D x86_match_cpu(rapl_ids); + if (!id) + return 0; + + def =3D (const struct rapl_defaults *)id->driver_data; + + rapl_msr_platdev =3D platform_device_register_data(NULL, "intel_rapl_msr"= , 0, def, + sizeof(*def)); + if (IS_ERR(rapl_msr_platdev)) + pr_debug("intel_rapl_msr device register failed, ret:%ld\n", + PTR_ERR(rapl_msr_platdev)); + + return 0; +} +module_init(intel_rapl_msr_init); + +static void intel_rapl_msr_exit(void) +{ + platform_device_unregister(rapl_msr_platdev); + platform_driver_unregister(&intel_rapl_msr_driver); +} +module_exit(intel_rapl_msr_exit); =20 MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) co= ntrol via MSR interface"); MODULE_AUTHOR("Zhang Rui "); --=20 2.43.0 From nobody Wed Apr 1 09:47:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69DDE451062; Tue, 31 Mar 2026 21:20:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="79625012" X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="79625012" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:05 -0700 X-CSE-ConnectionGUID: 5Fceg9NTSaibRk9xBa2wKA== X-CSE-MsgGUID: ihdaIMaJTfyLZRrAKSrW7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="221627109" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:04 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/7] powercap: intel_rapl: Remove unused macro definitions Date: Tue, 31 Mar 2026 14:19:45 -0700 Message-ID: <20260331211950.3329932-3-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the following unused macro definitions from the RAPL common driver: * DOMAIN_STATE_INACTIVE and DOMAIN_STATE_POWER_LIMIT_SET * IOSF_CPU_POWER_BUDGET_CTL_BYT and IOSF_CPU_POWER_BUDGET_CTL_TNG * MAX_PRIM_NAME No functional changes. Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_common.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 1e8146283009..f2637cc2cc6a 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -96,15 +96,7 @@ /* per domain data, some are optional */ #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) =20 -#define DOMAIN_STATE_INACTIVE BIT(0) -#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) - -/* Sideband MBI registers */ -#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02 -#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF - #define PACKAGE_PLN_INT_SAVED BIT(0) -#define MAX_PRIM_NAME 32 =20 #define RAPL_EVENT_MASK GENMASK(7, 0) =20 --=20 2.43.0 From nobody Wed Apr 1 09:47:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DB7A45106D; Tue, 31 Mar 2026 21:20:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774992009; cv=none; b=sv1nT5AnJTmLbe0P7ZXBrbM/1lAZJxbVCdUv86CYQlSEFgHUBK418PYOTW+xy8eYzxnFRYMxutPtISuuNOeNxmFh2mdCnvJuGZ2aXxUSYLxJVQ5c2yZUCmdEIjL+FsmAdgSzOEbWjGxfg5NqN/m282rYeJut6LI8BUxIS/UbldY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774992009; c=relaxed/simple; bh=BFdhPDP2aWwfYpD15bEem6tQTUZHGiPijPgT9UqSegA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FM9FkAaITe+ahuFs4Z9iP6HNC2mhKMbBhZuY+jo6ZtE9tWF1KDvcgwP6bEvWWvLNak5sXhk2whaXgtHxwrtfkWUo4eTyRZx9oLNrtV/39Ryb/rFB3En+fVVeERZDY6gQXt6tiUHpoFEXM+M1EpRa77c2N92UxwyKvlIP5DrGcZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=F9ybjNTQ; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="F9ybjNTQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774992007; x=1806528007; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BFdhPDP2aWwfYpD15bEem6tQTUZHGiPijPgT9UqSegA=; b=F9ybjNTQ0bdPOlFIOp3WydTfjjoKOf8JX6QxPEbqpbVMEPzPm6CaXdvP uJXh4d2f9Exm9s8aXwyB2x5KK9irSsFllRQJ9ZkWaMWGGVOAHaAlBNWyR 6jdobc5Kno5DjD6KGPZ2CabD2TeWzBqm7WeUeBqEYsOF2Hpuiyn3qIWAp XQeEzmQMoKJ3UzT1Hg9UgMTb8V+vva9pkmfM1+X46r9kybE9nTwWmUqDG siUkbmqmsQk5QMvMmZUpmLuhrabOsV8HJi79mp3Ddz32nO8RONjzFRcbx O569GPH0YXZpmRWw7dOKH7CaS3LYD4fGMHJnd2s1goDP4wKRM2DgswDIA w==; X-CSE-ConnectionGUID: L5Fo1fqPS2G9BnRWVbANVQ== X-CSE-MsgGUID: F9zon+YJQDyFAhQhQtWMTA== X-IronPort-AV: E=McAfee;i="6800,10657,11745"; a="79625014" X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="79625014" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:05 -0700 X-CSE-ConnectionGUID: cdHhfcIfR8qB4vc97SLl6A== X-CSE-MsgGUID: Mdz4jCY7S9iAy+pHdPtaMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="221627115" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:04 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/7] powercap: intel_rapl: Move primitive info to header for interface drivers Date: Tue, 31 Mar 2026 14:19:46 -0700 Message-ID: <20260331211950.3329932-4-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RAPL primitive information varies across different RAPL interfaces (MSR, TPMI, MMIO). Keeping them in the common code adds no benefit, but requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the primitive info infrastructure to the shared header to allow interface drivers to configure RAPL primitives. Specific changes: 1. Move struct rapl_primitive_info, enum unit_type, and PRIMITIVE_INFO_INIT macro to intel_rapl.h. 2. Change the @rpi field in struct rapl_if_priv from void * to struct rapl_primitive_info * to improve type safety and eliminate unnecessary casts. No functional changes. This is a preparatory refactoring to allow interface drivers to supply their own RAPL primitive settings. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_common.c | 32 ++-------------------------- include/linux/intel_rapl.h | 32 ++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index f2637cc2cc6a..ffc9d0378257 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -100,13 +100,6 @@ =20 #define RAPL_EVENT_MASK GENMASK(7, 0) =20 -enum unit_type { - ARBITRARY_UNIT, /* no translation */ - POWER_UNIT, - ENERGY_UNIT, - TIME_UNIT, -}; - static const char *pl_names[NR_POWER_LIMITS] =3D { [POWER_LIMIT1] =3D "long_term", [POWER_LIMIT2] =3D "short_term", @@ -208,27 +201,6 @@ static const struct rapl_defaults *get_defaults(struct= rapl_package *rp) return rp->priv->defaults; } =20 -/* per domain data. used to describe individual knobs such that access fun= ction - * can be consolidated into one instead of many inline functions. - */ -struct rapl_primitive_info { - const char *name; - u64 mask; - int shift; - enum rapl_domain_reg_id id; - enum unit_type unit; - u32 flag; -}; - -#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ - .name =3D #p, \ - .mask =3D m, \ - .shift =3D s, \ - .id =3D i, \ - .unit =3D u, \ - .flag =3D f \ - } - static void rapl_init_domains(struct rapl_package *rp); static int rapl_read_data_raw(struct rapl_domain *rd, enum rapl_primitives prim, @@ -748,10 +720,10 @@ static int rapl_config(struct rapl_package *rp) /* MMIO I/F shares the same register layout as MSR registers */ case RAPL_IF_MMIO: case RAPL_IF_MSR: - rp->priv->rpi =3D (void *)rpi_msr; + rp->priv->rpi =3D rpi_msr; break; case RAPL_IF_TPMI: - rp->priv->rpi =3D (void *)rpi_tpmi; + rp->priv->rpi =3D rpi_tpmi; break; default: return -EINVAL; diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h index 9e6bd654be1f..01f290de3586 100644 --- a/include/linux/intel_rapl.h +++ b/include/linux/intel_rapl.h @@ -137,6 +137,34 @@ struct rapl_defaults { bool spr_psys_bits; }; =20 +#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ + .name =3D #p, \ + .mask =3D m, \ + .shift =3D s, \ + .id =3D i, \ + .unit =3D u, \ + .flag =3D f \ + } + +enum unit_type { + ARBITRARY_UNIT, /* no translation */ + POWER_UNIT, + ENERGY_UNIT, + TIME_UNIT, +}; + +/* per domain data. used to describe individual knobs such that access fun= ction + * can be consolidated into one instead of many inline functions. + */ +struct rapl_primitive_info { + const char *name; + u64 mask; + int shift; + enum rapl_domain_reg_id id; + enum unit_type unit; + u32 flag; +}; + /** * struct rapl_if_priv: private data for different RAPL interfaces * @control_type: Each RAPL interface must have its own powercap @@ -152,7 +180,7 @@ struct rapl_defaults { * @write_raw: Callback for writing RAPL interface specific * registers. * @defaults: pointer to default settings - * @rpi: internal pointer to interface primitive info + * @rpi: pointer to interface primitive info */ struct rapl_if_priv { enum rapl_if_type type; @@ -164,7 +192,7 @@ struct rapl_if_priv { int (*read_raw)(int id, struct reg_action *ra, bool pmu_ctx); int (*write_raw)(int id, struct reg_action *ra); const struct rapl_defaults *defaults; - void *rpi; + struct rapl_primitive_info *rpi; }; =20 #ifdef CONFIG_PERF_EVENTS --=20 2.43.0 From nobody Wed Apr 1 09:47:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F2934534A4; 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X-CSE-ConnectionGUID: X2PlkEz3Q8u/wU4HAQK6tQ== X-CSE-MsgGUID: C6Ey2EIuS4KXHkIPYw11DA== X-IronPort-AV: E=McAfee;i="6800,10657,11745"; a="79625017" X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="79625017" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:05 -0700 X-CSE-ConnectionGUID: ucXkdHAuSZi/Tf8rAojyNw== X-CSE-MsgGUID: Oz82nk08T+GbvBK/J+7BTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="221627118" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:05 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/7] powercap: intel_rapl: Move TPMI primitives to TPMI driver Date: Tue, 31 Mar 2026 14:19:47 -0700 Message-ID: <20260331211950.3329932-5-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TPMI-specific RAPL primitives differ from those used by MSR and MMIO interfaces. Keeping them in the common RAPL driver requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the TPMI primitive definitions and associated bitmasks into the TPMI interface driver. This change includes: 1. Move TPMI-specific bitmask definitions from intel_rapl_common.c to intel_rapl_tpmi.c. 2. Add TPMI-local struct rapl_primitive_info instance and assign it to priv->rpi during TPMI probe. 3. Remove the RAPL TPMI related definitions from the common driver. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_common.c | 51 -------------------------- drivers/powercap/intel_rapl_tpmi.c | 53 ++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 51 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index ffc9d0378257..06912cb805f7 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -79,15 +79,6 @@ #define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) #define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) =20 -/* bitmasks for RAPL TPMI, used by primitive access functions */ -#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0) -#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) -#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18) -#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0) -#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18) -#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36) -#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) - /* Non HW constants */ #define RAPL_PRIMITIVE_DUMMY BIT(2) =20 @@ -665,45 +656,6 @@ static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIM= ITIVES] =3D { 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), }; =20 -/* RAPL primitives for TPMI I/F */ -static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] =3D { - /* name, mask, shift, msr index, unit divisor */ - [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MA= SK, 0, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MA= SK, 0, - RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), - [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MA= SK, 0, - RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), - [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MA= SK, 0, - RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), - [PL1_LOCK] =3D PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_LOCK] =3D PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), - [PL4_LOCK] =3D PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), - [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, - RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), - [PL4_ENABLE] =3D PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, - RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), - [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MA= SK, 18, - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MA= SK, 18, - RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), - [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INF= O_SPEC_MASK, 0, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_= TIME_WIN_MASK, - 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), - [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THRO= TTLE_TIME_MASK, - 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), -}; - static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int pr= im) { struct rapl_primitive_info *rpi =3D rp->priv->rpi; @@ -722,9 +674,6 @@ static int rapl_config(struct rapl_package *rp) case RAPL_IF_MSR: rp->priv->rpi =3D rpi_msr; break; - case RAPL_IF_TPMI: - rp->priv->rpi =3D rpi_tpmi; - break; default: return -EINVAL; } diff --git a/drivers/powercap/intel_rapl_tpmi.c b/drivers/powercap/intel_ra= pl_tpmi.c index c06d687366fc..7f41491d9cd1 100644 --- a/drivers/powercap/intel_rapl_tpmi.c +++ b/drivers/powercap/intel_rapl_tpmi.c @@ -62,6 +62,58 @@ static DEFINE_MUTEX(tpmi_rapl_lock); =20 static struct powercap_control_type *tpmi_control_type; =20 +/* bitmasks for RAPL TPMI, used by primitive access functions */ +#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0) +#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) +#define TPMI_POWER_HIGH_LOCK BIT_ULL(63) +#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18) +#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0) +#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18) +#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36) +#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) +#define TPMI_ENERGY_STATUS_MASK GENMASK(31, 0) +#define TPMI_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) + +/* RAPL primitives for TPMI I/F */ +static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] =3D { + /* name, mask, shift, msr index, unit divisor */ + [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MA= SK, 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MA= SK, 0, + RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), + [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MA= SK, 0, + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), + [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, TPMI_ENERGY_STAT= US_MASK, 0, + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), + [PL1_LOCK] =3D PRIMITIVE_INFO_INIT(PL1_LOCK, TPMI_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_LOCK] =3D PRIMITIVE_INFO_INIT(PL2_LOCK, TPMI_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), + [PL4_LOCK] =3D PRIMITIVE_INFO_INIT(PL4_LOCK, TPMI_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), + [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, + RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), + [PL4_ENABLE] =3D PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, + RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), + [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MA= SK, 18, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MA= SK, 18, + RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), + [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INF= O_SPEC_MASK, 0, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_= TIME_WIN_MASK, + 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), + [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, + TPMI_PERF_STATUS_THROTTLE_TIME_MASK, + 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), +}; + static int tpmi_rapl_read_raw(int id, struct reg_action *ra, bool atomic) { if (!ra->reg.mmio) @@ -344,6 +396,7 @@ static int intel_rapl_tpmi_probe(struct auxiliary_devic= e *auxdev, trp->priv.write_raw =3D tpmi_rapl_write_raw; trp->priv.control_type =3D tpmi_control_type; trp->priv.defaults =3D &defaults_tpmi; + trp->priv.rpi =3D rpi_tpmi; =20 /* RAPL TPMI I/F is per physical package */ trp->rp =3D rapl_find_package_domain(info->package_id, &trp->priv, false); --=20 2.43.0 From nobody Wed Apr 1 09:47:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0C9E4534A9; Tue, 31 Mar 2026 21:20:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774992010; cv=none; b=RYaD+OGEvEA2ii1XyO+6YoTVjMrhIX3tuxZCCKo+vpeHcHgLrpgR+kEqiLrhpvzh/Z5ww11Oa4DY5atXUdAHezVaKP+gtKS6g4fiPrb6iHAPmAwfoPZtKtm2JKHrx1zQSaDjgkZ9ol9sfBbd7RBfs7weM4/HeeE77Qyh12IhnDw= ARC-Message-Signature: i=1; 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d="scan'208";a="221627122" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:05 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/7] thermal: intel: int340x: processor: Move MMIO primitives to MMIO driver Date: Tue, 31 Mar 2026 14:19:48 -0700 Message-ID: <20260331211950.3329932-6-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MMIO-specific primitives differ from those used by the TPMI interface. The MSR and MMIO interfaces shared the same primitives in the common driver, but MMIO does not require many MSR-specific entries (like PSYS). Keeping these in the common driver does not add any value and requires interface-specific handling logic that makes the common layer unnecessarily complex. Move the MMIO primitive definitions and associated bitmasks into the MMIO interface driver. This change includes: 1. Add MMIO-local struct rapl_primitive_info instance without MSR-specific entries and assign it to priv->rpi during MMIO initialization. 2. Remove the RAPL MMIO case from rapl_config() in the common driver. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_common.c | 1 - .../int340x_thermal/processor_thermal_rapl.c | 72 +++++++++++++++++++ 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 06912cb805f7..7c5e16598ba3 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -670,7 +670,6 @@ static int rapl_config(struct rapl_package *rp) { switch (rp->priv->type) { /* MMIO I/F shares the same register layout as MSR registers */ - case RAPL_IF_MMIO: case RAPL_IF_MSR: rp->priv->rpi =3D rpi_msr; break; diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c= b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c index 5dbeb0a43c8c..f8b9745c1b8a 100644 --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c @@ -11,6 +11,77 @@ =20 static struct rapl_if_priv rapl_mmio_priv; =20 +/* bitmasks for RAPL MSRs, used by primitive access functions */ +#define MMIO_ENERGY_STATUS_MASK GENMASK(31, 0) + +#define MMIO_POWER_LIMIT1_MASK GENMASK(14, 0) +#define MMIO_POWER_LIMIT1_ENABLE BIT(15) +#define MMIO_POWER_LIMIT1_CLAMP BIT(16) + +#define MMIO_POWER_LIMIT2_MASK GENMASK_ULL(46, 32) +#define MMIO_POWER_LIMIT2_ENABLE BIT_ULL(47) +#define MMIO_POWER_LIMIT2_CLAMP BIT_ULL(48) + +#define MMIO_POWER_LOW_LOCK BIT(31) +#define MMIO_POWER_HIGH_LOCK BIT_ULL(63) + +#define MMIO_POWER_LIMIT4_MASK GENMASK(12, 0) + +#define MMIO_TIME_WINDOW1_MASK GENMASK_ULL(23, 17) +#define MMIO_TIME_WINDOW2_MASK GENMASK_ULL(55, 49) + +#define MMIO_POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) +#define MMIO_POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) +#define MMIO_POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) +#define MMIO_POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) + +#define MMIO_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) +#define MMIO_PP_POLICY_MASK GENMASK(4, 0) + +/* RAPL primitives for MMIO I/F */ +static struct rapl_primitive_info rpi_mmio[NR_RAPL_PRIMITIVES] =3D { + /* name, mask, shift, msr index, unit divisor */ + [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, MMIO_POWER_LIMIT1_M= ASK, 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, MMIO_POWER_LIMIT2_M= ASK, 32, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, MMIO_POWER_LIMIT4_M= ASK, 0, + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), + [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, MMIO_ENERGY_STAT= US_MASK, 0, + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), + [FW_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_LOW_LOCK, 31, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [FW_HIGH_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, MMIO_POWER_LIMIT1_ENABL= E, 15, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_CLAMP] =3D PRIMITIVE_INFO_INIT(PL1_CLAMP, MMIO_POWER_LIMIT1_CLAMP, = 16, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, MMIO_POWER_LIMIT2_ENABL= E, 47, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_CLAMP] =3D PRIMITIVE_INFO_INIT(PL2_CLAMP, MMIO_POWER_LIMIT2_CLAMP, = 48, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, MMIO_TIME_WINDOW1_M= ASK, 17, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, MMIO_TIME_WINDOW2_M= ASK, 49, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, + MMIO_POWER_INFO_THERMAL_SPEC_MASK, 0, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, MMIO_POWER_INFO_MAX_MASK,= 32, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, MMIO_POWER_INFO_MIN_MASK,= 16, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, + MMIO_POWER_INFO_MAX_TIME_WIN_MASK, 48, + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), + [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, + MMIO_PERF_STATUS_THROTTLE_TIME_MASK, 0, + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), + [PRIORITY_LEVEL] =3D PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, MMIO_PP_POLICY_M= ASK, 0, + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), +}; + static const struct rapl_mmio_regs rapl_mmio_default =3D { .reg_unit =3D 0x5938, .regs[RAPL_DOMAIN_PACKAGE] =3D { 0x59a0, 0x593c, 0x58f0, 0, 0x5930, 0x59b= 0}, @@ -75,6 +146,7 @@ int proc_thermal_rapl_add(struct pci_dev *pdev, struct p= roc_thermal_device *proc rapl_mmio_priv.read_raw =3D rapl_mmio_read_raw; rapl_mmio_priv.write_raw =3D rapl_mmio_write_raw; rapl_mmio_priv.defaults =3D &rapl_defaults_mmio; + rapl_mmio_priv.rpi =3D rpi_mmio; =20 rapl_mmio_priv.control_type =3D powercap_register_control_type(NULL, "int= el-rapl-mmio", NULL); if (IS_ERR(rapl_mmio_priv.control_type)) { --=20 2.43.0 From nobody Wed Apr 1 09:47:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1314E4534B2; Tue, 31 Mar 2026 21:20:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; 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d="scan'208";a="79625023" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:06 -0700 X-CSE-ConnectionGUID: LWAep0Z5QTClyETDF2SBAQ== X-CSE-MsgGUID: Xn8JsurARrS7bnlG0VJ9pg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="221627127" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:05 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 6/7] powercap: intel_rapl: Move MSR primitives to MSR driver Date: Tue, 31 Mar 2026 14:19:49 -0700 Message-ID: <20260331211950.3329932-7-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MSR-specific RAPL primitives differ from those used by TPMI and MMIO interfaces. Keeping them in the common driver requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the MSR primitive definitions and associated bitmasks into the MSR interface driver. This change includes: 1. Move MSR-specific bitmask definitions to RAPL MSR driver. 2. Add MSR-local struct rapl_primitive_info instance and assign it to priv->rpi during MSR probe. 3. Remove the primitive assignment logic from rapl_config() in the common driver. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_common.c | 105 --------------------------- drivers/powercap/intel_rapl_msr.c | 99 +++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 105 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 7c5e16598ba3..a8dd02dff0a0 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -30,24 +30,8 @@ #include #include =20 -/* bitmasks for RAPL MSRs, used by primitive access functions */ #define ENERGY_STATUS_MASK GENMASK(31, 0) =20 -#define POWER_LIMIT1_MASK GENMASK(14, 0) -#define POWER_LIMIT1_ENABLE BIT(15) -#define POWER_LIMIT1_CLAMP BIT(16) - -#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32) -#define POWER_LIMIT2_ENABLE BIT_ULL(47) -#define POWER_LIMIT2_CLAMP BIT_ULL(48) -#define POWER_HIGH_LOCK BIT_ULL(63) -#define POWER_LOW_LOCK BIT(31) - -#define POWER_LIMIT4_MASK GENMASK(12, 0) - -#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17) -#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49) - #define POWER_UNIT_OFFSET 0x00 #define POWER_UNIT_MASK GENMASK(3, 0) =20 @@ -57,28 +41,6 @@ #define TIME_UNIT_OFFSET 0x10 #define TIME_UNIT_MASK GENMASK(19, 16) =20 -#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) -#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) -#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) -#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) - -#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) -#define PP_POLICY_MASK GENMASK(4, 0) - -/* - * SPR has different layout for Psys Domain PowerLimit registers. - * There are 17 bits of PL1 and PL2 instead of 15 bits. - * The Enable bits and TimeWindow bits are also shifted as a result. - */ -#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0) -#define PSYS_POWER_LIMIT1_ENABLE BIT(17) - -#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32) -#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) - -#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) -#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) - /* Non HW constants */ #define RAPL_PRIMITIVE_DUMMY BIT(2) =20 @@ -598,64 +560,6 @@ static u64 rapl_unit_xlate(struct rapl_domain *rd, enu= m unit_type type, return div64_u64(value, scale); } =20 -/* RAPL primitives for MSR and MMIO I/F */ -static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] =3D { - /* name, mask, shift, msr index, unit divisor */ - [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, = 0, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, = 32, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, = 0, - RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), - [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MA= SK, 0, - RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), - [FW_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [FW_HIGH_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL1_CLAMP] =3D PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_CLAMP] =3D PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, = 17, - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, = 49, - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, - POWER_INFO_THERMAL_SPEC_MASK, 0, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, - POWER_INFO_MAX_TIME_WIN_MASK, 48, - RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), - [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, - PERF_STATUS_THROTTLE_TIME_MASK, 0, - RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), - [PRIORITY_LEVEL] =3D PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, = 0, - RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), - [PSYS_POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER= _LIMIT1_MASK, 0, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [PSYS_POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER= _LIMIT2_MASK, - 32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [PSYS_PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIM= IT1_ENABLE, - 17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, - 0), - [PSYS_PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIM= IT2_ENABLE, - 49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, - 0), - [PSYS_TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_= WINDOW1_MASK, - 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [PSYS_TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_= WINDOW2_MASK, - 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), -}; - static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int pr= im) { struct rapl_primitive_info *rpi =3D rp->priv->rpi; @@ -668,15 +572,6 @@ static struct rapl_primitive_info *get_rpi(struct rapl= _package *rp, int prim) =20 static int rapl_config(struct rapl_package *rp) { - switch (rp->priv->type) { - /* MMIO I/F shares the same register layout as MSR registers */ - case RAPL_IF_MSR: - rp->priv->rpi =3D rpi_msr; - break; - default: - return -EINVAL; - } - /* defaults_msr can be NULL on unsupported platforms */ if (!rp->priv->defaults || !rp->priv->rpi) return -ENODEV; diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index b7c10ed75d69..cfb35973f0b5 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -44,6 +44,46 @@ #define TIME_UNIT_OFFSET 0x10 #define TIME_UNIT_MASK GENMASK(19, 16) =20 +/* bitmasks for RAPL MSRs, used by primitive access functions */ +#define ENERGY_STATUS_MASK GENMASK(31, 0) + +#define POWER_LIMIT1_MASK GENMASK(14, 0) +#define POWER_LIMIT1_ENABLE BIT(15) +#define POWER_LIMIT1_CLAMP BIT(16) + +#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32) +#define POWER_LIMIT2_ENABLE BIT_ULL(47) +#define POWER_LIMIT2_CLAMP BIT_ULL(48) +#define POWER_HIGH_LOCK BIT_ULL(63) +#define POWER_LOW_LOCK BIT(31) + +#define POWER_LIMIT4_MASK GENMASK(12, 0) + +#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17) +#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49) + +#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) +#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) +#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) +#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) + +#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) +#define PP_POLICY_MASK GENMASK(4, 0) + +/* + * SPR has different layout for Psys Domain PowerLimit registers. + * There are 17 bits of PL1 and PL2 instead of 15 bits. + * The Enable bits and TimeWindow bits are also shifted as a result. + */ +#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0) +#define PSYS_POWER_LIMIT1_ENABLE BIT(17) + +#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32) +#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) + +#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) +#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) + /* Sideband MBI registers */ #define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02 #define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF @@ -268,6 +308,64 @@ static u64 rapl_compute_time_window_atom(struct rapl_d= omain *rd, u64 value, return value ? value * rd->time_unit : rd->time_unit; } =20 +/* RAPL primitives for MSR I/F */ +static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] =3D { + /* name, mask, shift, msr index, unit divisor */ + [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, = 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, = 32, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, = 0, + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), + [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MA= SK, 0, + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), + [FW_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [FW_HIGH_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_CLAMP] =3D PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_CLAMP] =3D PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, = 17, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, = 49, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, + POWER_INFO_THERMAL_SPEC_MASK, 0, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, + POWER_INFO_MAX_TIME_WIN_MASK, 48, + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), + [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, + PERF_STATUS_THROTTLE_TIME_MASK, 0, + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), + [PRIORITY_LEVEL] =3D PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, = 0, + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), + [PSYS_POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER= _LIMIT1_MASK, 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [PSYS_POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER= _LIMIT2_MASK, + 32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [PSYS_PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIM= IT1_ENABLE, + 17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, + 0), + [PSYS_PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIM= IT2_ENABLE, + 49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, + 0), + [PSYS_TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_= WINDOW1_MASK, + 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [PSYS_TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_= WINDOW2_MASK, + 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), +}; + static const struct rapl_defaults rapl_defaults_core =3D { .floor_freq_reg_addr =3D 0, .check_unit =3D rapl_default_check_unit, @@ -418,6 +516,7 @@ static int rapl_msr_probe(struct platform_device *pdev) rapl_msr_priv->read_raw =3D rapl_msr_read_raw; rapl_msr_priv->write_raw =3D rapl_msr_write_raw; rapl_msr_priv->defaults =3D (const struct rapl_defaults *)pdev->dev.platf= orm_data; + rapl_msr_priv->rpi =3D rpi_msr; =20 if (id) { rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |=3D BIT(POWER_LIMIT4); --=20 2.43.0 From nobody Wed Apr 1 09:47:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C52D4611C9; Tue, 31 Mar 2026 21:20:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774992012; cv=none; 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d="scan'208";a="79625026" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:06 -0700 X-CSE-ConnectionGUID: gueX6qIuQGiVb6ALTioxVg== X-CSE-MsgGUID: +NTYWDmKRm+9cszVL7kZpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,152,1770624000"; d="scan'208";a="221627130" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2026 14:20:06 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" Cc: Srinivas Pandruvada , Zhang Rui , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 7/7] powercap: intel_rapl: Consolidate PL4 and PMU support flags into rapl_defaults Date: Tue, 31 Mar 2026 14:19:50 -0700 Message-ID: <20260331211950.3329932-8-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260331211950.3329932-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, PL4 and MSR-based RAPL PMU support are detected using separate CPU ID tables (pl4_support_ids and pmu_support_ids) in the MSR driver probe path. This creates a maintenance burden since adding a new CPU requires updates in two places: the rapl_ids table and one or both of these capability tables. Consolidate PL4 and PMU capability information directly into struct rapl_defaults by adding msr_pl4_support and msr_pmu_support flags. This allows per-CPU capability to be expressed in a single place alongside other per-CPU defaults, eliminating the duplicate CPU ID tables entirely. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Acked-by: Srinivas Pandruvada Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/powercap/intel_rapl_msr.c | 83 ++++++++++++++----------------- include/linux/intel_rapl.h | 2 + 2 files changed, 38 insertions(+), 47 deletions(-) diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index cfb35973f0b5..a34543e66446 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -216,33 +216,6 @@ static int rapl_msr_write_raw(int cpu, struct reg_acti= on *ra) return ra->err; } =20 -/* List of verified CPUs. */ -static const struct x86_cpu_id pl4_support_ids[] =3D { - X86_MATCH_VFM(INTEL_ICELAKE_L, NULL), - X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), - X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL), - X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), - X86_MATCH_VFM(INTEL_METEORLAKE, NULL), - X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL), - X86_MATCH_VFM(INTEL_ARROWLAKE_U, NULL), - X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL), - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), - X86_MATCH_VFM(INTEL_NOVALAKE, NULL), - X86_MATCH_VFM(INTEL_NOVALAKE_L, NULL), - {} -}; - -/* List of MSR-based RAPL PMU support CPUs */ -static const struct x86_cpu_id pmu_support_ids[] =3D { - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), - {} -}; - static int rapl_check_unit_atom(struct rapl_domain *rd) { struct reg_action ra; @@ -420,6 +393,23 @@ static const struct rapl_defaults rapl_defaults_amd = =3D { .check_unit =3D rapl_default_check_unit, }; =20 +static const struct rapl_defaults rapl_defaults_core_pl4 =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, + .msr_pl4_support =3D 1, +}; + +static const struct rapl_defaults rapl_defaults_core_pl4_pmu =3D { + .floor_freq_reg_addr =3D 0, + .check_unit =3D rapl_default_check_unit, + .set_floor_freq =3D rapl_default_set_floor_freq, + .compute_time_window =3D rapl_default_compute_time_window, + .msr_pl4_support =3D 1, + .msr_pmu_support =3D 1, +}; + static const struct x86_cpu_id rapl_ids[] =3D { X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), @@ -443,35 +433,35 @@ static const struct x86_cpu_id rapl_ids[] =3D { X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core_pl4_pmu), + X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core_pl4_pmu), + X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core_pl4), + X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), - X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), + X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core_pl4), X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), =20 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), @@ -498,7 +488,6 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_ids); =20 static int rapl_msr_probe(struct platform_device *pdev) { - const struct x86_cpu_id *id =3D x86_match_cpu(pl4_support_ids); int ret; =20 switch (boot_cpu_data.x86_vendor) { @@ -518,16 +507,16 @@ static int rapl_msr_probe(struct platform_device *pde= v) rapl_msr_priv->defaults =3D (const struct rapl_defaults *)pdev->dev.platf= orm_data; rapl_msr_priv->rpi =3D rpi_msr; =20 - if (id) { + if (rapl_msr_priv->defaults->msr_pl4_support) { rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |=3D BIT(POWER_LIMIT4); rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4].msr =3D MSR_VR_CURRENT_CONFIG; - pr_info("PL4 support detected.\n"); + pr_info("PL4 support detected (updated).\n"); } =20 - if (x86_match_cpu(pmu_support_ids)) { + if (rapl_msr_priv->defaults->msr_pmu_support) { rapl_msr_pmu =3D true; - pr_info("MSR-based RAPL PMU support enabled\n"); + pr_info("MSR-based RAPL PMU support enabled (updated)\n"); } =20 rapl_msr_priv->control_type =3D powercap_register_control_type(NULL, "int= el-rapl", NULL); diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h index 01f290de3586..328004f605c3 100644 --- a/include/linux/intel_rapl.h +++ b/include/linux/intel_rapl.h @@ -135,6 +135,8 @@ struct rapl_defaults { unsigned int dram_domain_energy_unit; unsigned int psys_domain_energy_unit; bool spr_psys_bits; + bool msr_pl4_support; + bool msr_pmu_support; }; =20 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ --=20 2.43.0