From nobody Wed Apr 1 08:17:26 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17C8031B838; Tue, 31 Mar 2026 17:13:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774977184; cv=none; b=ql0TKFKJhuZliJi5Zv38oXWy71kza3t8htKdH5ACbuRjO5kXkUhYdhtlkrI2JxM4ihBEerbJnG0uF41a8IJorAx9To6sM7oRabWSAbD07jj40SCrshXDIZMfR/jC9grC0MYASik0YMf2esbNCK6G60F73qr88nsZKD+yQcxNnac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774977184; c=relaxed/simple; bh=0pCEVgH7hlMCDs8dFYJ4JjgPyGAP2s1IYvC/6S6vRnw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IaA5tHYq0DbNVHXQ3XKTIYxaZ6xz92hMZZiLNt+Zqn6jkenagG2F1z5h++WnuLrFqQmbaDcwbyzvvq0EYpolfC4/bwKoLLhDjILp7lCYmleo2AyC/eEBZMebru3Jam3PI+4N4Lp93f32qhWvhFdITcAexkz0rOUttzqoQOQdcJE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [223.166.95.230]) by APP-03 (Coremail) with SMTP id rQCowABnhdyRAMxpydRzDA--.42156S3; Wed, 01 Apr 2026 01:12:51 +0800 (CST) From: Han Gao To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Han Gao , Zixian Zeng Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Han Gao Subject: [PATCH 1/2] dt-bindings: pci: sophgo: Add dma-coherent property for SG2042 Date: Wed, 1 Apr 2026 01:12:47 +0800 Message-ID: <20260331171248.973014-2-gaohan@iscas.ac.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260331171248.973014-1-gaohan@iscas.ac.cn> References: <20260331171248.973014-1-gaohan@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowABnhdyRAMxpydRzDA--.42156S3 X-Coremail-Antispam: 1UD129KBjvdXoWrKr17Wr17XFW8Gw1UJr1rtFb_yoWfKwb_W3 WfAF4kZrs8ArWYgrn0yw48GFW5Zw42vryDCw15Ka1F934IqrWDKa4kJas8AF17Grs8uFyf uwn3ZrykuwsrWjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbQAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGwA2048vs2IY02 0Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJwAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCF54CYxVCY1x0262kKe7AK xVW8ZVWrXwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I 0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAI cVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRMfOzDUUUU X-CM-SenderInfo: xjdrxt3q6l2u1dvotugofq/1tbiBg0DDGnL4ih7xQABsT Content-Type: text/plain; charset="utf-8" Add dma-coherent as an allowed property in the SG2042 PCIe host controller binding. SG2042's PCIe root complexes are cache-coherent with the CPU. Signed-off-by: Han Gao --- .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.= yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml index f8b7ca57fff1..ab482488b047 100644 --- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -30,6 +30,8 @@ properties: device-id: const: 0x2042 =20 + dma-coherent: true + msi-parent: true =20 allOf: @@ -60,5 +62,6 @@ examples: vendor-id =3D <0x1f1c>; device-id =3D <0x2042>; cdns,no-bar-match-nbits =3D <48>; + dma-coherent; msi-parent =3D <&msi>; }; --=20 2.47.3 From nobody Wed Apr 1 08:17:26 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC78331D371; Tue, 31 Mar 2026 17:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774977187; cv=none; b=MyA7DxHa+2Ax9oxdfzupKIzBs3Hv0rGM586060ge4NEaaaQcgEmZJj1pQJwDsRdlca/lECK0q/AMLr8q666evS0dRkkrkrqSsckBXOk3bVgfmCJTJAYWKdfHr3d8iI5TP+ESlaxC0ub9930xdJmk7pmnP3ToPUyiv2frEkEJReU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774977187; c=relaxed/simple; bh=LjAqqBgNW2sWmyeSHjj7o/HH2Z1LXM/vDtlzhXMFot8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NWwbOyJiFhaMJtg7qpdu48MGsrM5o5hBJMKpSZx9Ni/JTIfon/ueU7D5UX5A1+glahzd2n4nrJTAP4E7z/seOMdKHUJ1Z59ZeMfEC3KnyNXocq/mtphxCZcealE10YlatiiPAXfXFYWVWnKU3w0TIZeFomcXFZgNBcyzcybbuA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [223.166.95.230]) by APP-03 (Coremail) with SMTP id rQCowABnhdyRAMxpydRzDA--.42156S4; Wed, 01 Apr 2026 01:12:52 +0800 (CST) From: Han Gao To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Han Gao , Zixian Zeng Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Han Gao , stable@vger.kernel.org Subject: [PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers Date: Wed, 1 Apr 2026 01:12:48 +0800 Message-ID: <20260331171248.973014-3-gaohan@iscas.ac.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260331171248.973014-1-gaohan@iscas.ac.cn> References: <20260331171248.973014-1-gaohan@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowABnhdyRAMxpydRzDA--.42156S4 X-Coremail-Antispam: 1UD129KBjvJXoW7WrWrJFyxZFWkXry7tFyftFb_yoW8Gw45pr srCF45KFyxXrZYv3W7GFy0gr43JFZYkasxKrnYk3W8W3yYvryUXrn3Aw1Ig3WDGr4jq343 WFs8tFyrKF1qy3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQC14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxAqzxv26xkF7I0En4kS 14v26r4a6rW5MxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2 IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI 42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIx AIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2 jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjTRNiSHDUUUU X-CM-SenderInfo: xjdrxt3q6l2u1dvotugofq/1tbiBg0DDGnL4ih7zAAAsb Content-Type: text/plain; charset="utf-8" SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent so the kernel uses coherent DMA mappings instead of non-coherent bounce buffering. Cc: stable@vger.kernel.org Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index 9fddf3f0b3b9..3af770549742 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { vendor-id =3D <0x1f1c>; device-id =3D <0x2042>; cdns,no-bar-match-nbits =3D <48>; + dma-coherent; msi-parent =3D <&msi>; status =3D "disabled"; }; @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { vendor-id =3D <0x1f1c>; device-id =3D <0x2042>; cdns,no-bar-match-nbits =3D <48>; + dma-coherent; msi-parent =3D <&msi>; status =3D "disabled"; }; @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { vendor-id =3D <0x1f1c>; device-id =3D <0x2042>; cdns,no-bar-match-nbits =3D <48>; + dma-coherent; msi-parent =3D <&msi>; status =3D "disabled"; }; @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { vendor-id =3D <0x1f1c>; device-id =3D <0x2042>; cdns,no-bar-match-nbits =3D <48>; + dma-coherent; msi-parent =3D <&msi>; status =3D "disabled"; }; --=20 2.47.3