From nobody Wed Apr 1 09:46:37 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC6C8405AAB for ; Tue, 31 Mar 2026 15:26:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774970774; cv=none; b=nxRKaInB/RcwBqHFrqaJFGBLAK7MlkFTqSFKYaD3DfYOwMxFNSJFg2giIjpqox+1DU9VgIiLO5TPPEz0amUkNzkEyRlzF+Fch+loVV1W4c54Kc1Pre8TMzZEZylQNksbt8Iw4h9+s8PsTjjQGIVwFR4iFt7uzmELtXXXtU4NwOI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774970774; c=relaxed/simple; bh=DAISVYoms1Zxq5rhE8jzaBHN9WUxfvAS/7zdsmYKfhI=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=BsDdvOLqPOXcZuWHwW1TjVy7Zp2FRw1FmlRlofVzmNi65wVSsSebqn90LtEdsL3NIhvR6nOUjyYY/knu9wPMV06pZgQb5ZVzfiDXKg9T9fCaIdI3O8JlYCkdXK9PtMAV/i1IZF5lkVbFSajp1OxKK/6KtFuG9w8tQqRoaQPHc4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=HbDgOCwt; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="HbDgOCwt" Received: from zhangyu-hyperv.mshome.net (unknown [167.220.233.3]) by linux.microsoft.com (Postfix) with ESMTPSA id 04FC820B6F01; Tue, 31 Mar 2026 08:26:03 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 04FC820B6F01 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1774970772; bh=uv0h8K+vkDUfK8ImoG8bD+vnM+kcraBl3eM6Ol7J0CM=; h=From:To:Cc:Subject:Date:From; b=HbDgOCwtL5MvQ+OekV8z7uEdYoj4e6lfICw+tc9bJmYg+OLf5OnTxN8Mtf01LCcRe W0/Bj+uFSnHb0GBhkefahm/tAvE7Z5V4JRx01Z+tnFh5RtzWqhSUr3pDDVWxUtWqpR o2fZ9ILlyfs6uJDuRJ3bZLAQ8IBBkRKTflhAYWys= From: Yu Zhang To: iommu@lists.linux.dev Cc: Joerg Roedel , Jason Gunthorpe , Jacob Pan , Suravee Suthikulpanit , Will Deacon , Robin Murphy , linux-kernel@vger.kernel.org Subject: [PATCH] iommu/amd: Remove dead code for exclusion ranges in IVMD Date: Tue, 31 Mar 2026 23:25:50 +0800 Message-ID: <20260331152550.479841-1-zhangyu1@linux.microsoft.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Exclusion ranges in IVMD are treated as unity mappings with r&w permissions since commit 0bbe4ced53e3 ("iommu/amd: Fix the overwritten field in IVMD header"), using 1:1 mappings. And IOMMU Exclusion Base & Range Limit Registers (0x0020/0x0028) are actually no longer used. As a result, several definitions and code paths became dead code: - exclusion_start/exclusion_length in struct amd_iommu are never assigned, - iommu_set_exclusion_range() always returns 0 now. - MMIO_EXCL_ENABLE_MASK & MMIO_EXCL_ALLOW_MASK are only used by the removed iommu_set_exclusion_range(). - DEV_ENTRY_EX is no longer set in any DTE. - IOMMU_UNITY_MAP_FLAG_EXCL_RANGE is no longer set, thus the IOMMU_RESV_RESERVED branch in amd_iommu_get_resv_regions() is no longer reachable. Just remove all of the dead code. No functional change. Signed-off-by: Yu Zhang Reviewed-by: Jacob Pan --- drivers/iommu/amd/amd_iommu_types.h | 12 ------------ drivers/iommu/amd/init.c | 23 ----------------------- drivers/iommu/amd/iommu.c | 3 --- 3 files changed, 38 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index c685d3771436..a481d8cbd053 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -50,10 +50,6 @@ #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHI= FT) #define MMIO_MSI_NUM(x) ((x) & 0x1f) =20 -/* Flag masks for the AMD IOMMU exclusion range */ -#define MMIO_EXCL_ENABLE_MASK 0x01ULL -#define MMIO_EXCL_ALLOW_MASK 0x02ULL - /* Used offsets into the MMIO space */ #define MMIO_DEV_TABLE_OFFSET 0x0000 #define MMIO_CMD_BUF_OFFSET 0x0008 @@ -231,7 +227,6 @@ #define DEV_ENTRY_IR 0x3d #define DEV_ENTRY_IW 0x3e #define DEV_ENTRY_NO_PAGE_FAULT 0x62 -#define DEV_ENTRY_EX 0x67 #define DEV_ENTRY_SYSMGT1 0x68 #define DEV_ENTRY_SYSMGT2 0x69 #define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40) @@ -384,8 +379,6 @@ #define IOMMU_PROT_IR 0x01 #define IOMMU_PROT_IW 0x02 =20 -#define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) - /* IOMMU capabilities */ #define IOMMU_CAP_IOTLB 24 #define IOMMU_CAP_NPCACHE 26 @@ -680,11 +673,6 @@ struct amd_iommu { /* pci domain of this IOMMU */ struct amd_iommu_pci_seg *pci_seg; =20 - /* start of exclusion range of that IOMMU */ - u64 exclusion_start; - /* length of exclusion range of that IOMMU */ - u64 exclusion_length; - /* command buffer virtual address */ u8 *cmd_buf; u32 cmd_buf_head; diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index f3fd7f39efb4..a33bf3f5ed8a 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -352,28 +352,6 @@ static void iommu_write_l2(struct amd_iommu *iommu, u8= address, u32 val) * *************************************************************************= ***/ =20 -/* - * This function set the exclusion range in the IOMMU. DMA accesses to the - * exclusion range are passed through untranslated - */ -static void iommu_set_exclusion_range(struct amd_iommu *iommu) -{ - u64 start =3D iommu->exclusion_start & PAGE_MASK; - u64 limit =3D (start + iommu->exclusion_length - 1) & PAGE_MASK; - u64 entry; - - if (!iommu->exclusion_start) - return; - - entry =3D start | MMIO_EXCL_ENABLE_MASK; - memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, - &entry, sizeof(entry)); - - entry =3D limit; - memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, - &entry, sizeof(entry)); -} - static void iommu_set_cwwb_range(struct amd_iommu *iommu) { u64 start =3D iommu_virt_to_phys((void *)iommu->cmd_sem); @@ -2891,7 +2869,6 @@ static void early_enable_iommu(struct amd_iommu *iomm= u) iommu_set_device_table(iommu); iommu_enable_command_buffer(iommu); iommu_enable_event_buffer(iommu); - iommu_set_exclusion_range(iommu); iommu_enable_gt(iommu); iommu_enable_ga(iommu); iommu_enable_xt(iommu); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 760d5f4623b5..4e7f5b993c65 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3076,9 +3076,6 @@ static void amd_iommu_get_resv_regions(struct device = *dev, prot |=3D IOMMU_READ; if (entry->prot & IOMMU_PROT_IW) prot |=3D IOMMU_WRITE; - if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) - /* Exclusion range */ - type =3D IOMMU_RESV_RESERVED; =20 region =3D iommu_alloc_resv_region(entry->address_start, length, prot, type, --=20 2.52.0