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charset="utf-8" Some platforms use a QUP-based I2C controller in a configuration where the controller is shared with another system processor. In this setup the operating system must not assume exclusive ownership of the controller or its associated pins. Add support for enabling multi-owner operation when DeviceTree specifies qcom,qup-multi-owner. When enabled, mark the underlying serial engine as shared so the common GENI resource handling avoids selecting the "sleep" pinctrl state, which could disrupt transfers initiated by the other processor. For GPI mode transfers, request lock/unlock TRE sequencing from the GPI driver by setting a single lock_action selector per message, emitting lock before the first message and unlock after the last message (handling the single-message case as well). This serializes access to the shared controller without requiring message-position flags to be passed into the DMA engine layer. Signed-off-by: Mukesh Kumar Savaliya --- drivers/i2c/busses/i2c-qcom-geni.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index ae609bdd2ec4..1925e4ec9842 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -815,6 +815,14 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c= , struct i2c_msg msgs[], i if (i < num - 1) peripheral.stretch =3D 1; =20 + peripheral.lock_action =3D GPI_LOCK_NONE; + if (gi2c->se.multi_owner) { + if (i =3D=3D 0) + peripheral.lock_action =3D GPI_LOCK_ACQUIRE; + else if (i =3D=3D num - 1) + peripheral.lock_action =3D GPI_LOCK_RELEASE; + } + peripheral.addr =3D msgs[i].addr; if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) peripheral.multi_msg =3D false; @@ -1014,6 +1022,17 @@ static int geni_i2c_probe(struct platform_device *pd= ev) gi2c->clk_freq_out =3D I2C_MAX_STANDARD_MODE_FREQ; } =20 + if (of_property_read_bool(pdev->dev.of_node, "qcom,qup-multi-owner")) { + /* + * Multi-owner controller configuration: the controller may be + * used by another system processor. Mark the SE as shared so + * common GENI resource handling can avoid pin state changes + * that would disrupt the other user. + */ + gi2c->se.multi_owner =3D true; + dev_dbg(&pdev->dev, "I2C controller is shared with another system proces= sor\n"); + } + if (has_acpi_companion(dev)) ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); =20 @@ -1089,7 +1108,9 @@ static int geni_i2c_probe(struct platform_device *pde= v) } =20 if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ + /* FIFO is disabled, so we can only use GPI DMA. + * SE can be shared in GSI mode between subsystems, each SS owns a GPII. + */ gi2c->gpi_mode =3D true; ret =3D setup_gpi_dma(gi2c); if (ret) @@ -1098,6 +1119,10 @@ static int geni_i2c_probe(struct platform_device *pd= ev) dev_dbg(dev, "Using GPI DMA mode for I2C\n"); } else { gi2c->gpi_mode =3D false; + + if (gi2c->se.multi_owner) + dev_err_probe(dev, -EINVAL, "I2C sharing not supported in non GSI mode\= n"); + tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); =20 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ --=20 2.25.1