From nobody Wed Apr 1 11:14:35 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 555B03BF69C; Tue, 31 Mar 2026 11:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774957297; cv=none; b=mbXuhPiqGdM/l9jaWG3lTPmWvsuYfez3ezfinZzN/R3YNmgfHJqKnpUjg0gmvcHQQp8Ctn2HxInepGNylK7/IoIopbkOtcrYV7yApEbT6Cxlp4lSH9d6e/8EMEVMk9mjkF3vwUQE5qfY/HbYebs6ViAcG51ZkY3nCol+evPuIes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774957297; c=relaxed/simple; bh=+L/K8+O6tMPwhjokt9uI6DRjPbeTQNlOvbn7Q7JVKSk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dl6VIlwnUeKvnNEXUZZiPcN875coO39MqUtrQXGQRU+Ldws96fXK8bx7tPCRcpnuKjB8wdBHhxxzLAYkEEi2Kxc/wA4If9RZiB3UaKG2pIGk2XgtSXzgpCK132YSEnKYsJU+TvVOsGccdSsQzqqtsvERdTULaFq80EjMF7uX3Cs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=tsHvh5lN; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="tsHvh5lN" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 62VBcZbgD3149080, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1774957115; bh=R54LgNHSFQobFVsX7fHxSQcvp4mTFC0QLJ2acEvsUu0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=tsHvh5lNzoiQ+YHoqn6jZtfHdalvYo5kI0cm/1ZfK4UWlg1UoGjaECW6jsKQo5D54 ZO54s58KfMspsCXJFa1a/+qAhT9DywFtmu4rXkLAf/sVxINdgG4E16YCEA4w1R1s+D SOeSBT+oEL/rbC48rcfM8yorE4izp+sPgel5sYmQB4Z101+XGD7SPbWKO7ngyU88+j J1VVxoocQJvC+rYfh3YwBjj2NBzZ0J6aQsJamtb4K+7LizZqciodPuJpWSQfh9vhdc o3vymAno8Nr7rdBOrZqeSV3uibkeupVZ8vwgEVaVXPFFPCw9FgzmMnTkVpzIN7dgiq w4szu6zwXlReg== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 62VBcZbgD3149080 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 31 Mar 2026 19:38:35 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar 2026 19:38:36 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar 2026 19:38:35 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 31 Mar 2026 19:38:35 +0800 From: Yu-Chun Lin To: , , , , , , CC: , , , , , , , , Subject: [PATCH 1/3] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio Date: Tue, 31 Mar 2026 19:38:33 +0800 Message-ID: <20260331113835.3510341-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260331113835.3510341-1-eleanor.lin@realtek.com> References: <20260331113835.3510341-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add the device tree bindings for the Realtek DHC (Digital Home Center) RTD1625 GPIO controllers. The RTD1625 GPIO controller features a per-pin register architecture that differs significantly from previous generations. It utilizes separate register blocks for GPIO configuration and interrupt control. Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin --- .../bindings/gpio/realtek,rtd1625-gpio.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/realtek,rtd1625-= gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.ya= ml b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml new file mode 100644 index 000000000000..e81d13dfefc2 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/realtek,rtd1625-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1625 GPIO controller + +maintainers: + - Tzuyi Chang + +description: | + GPIO controller for the Realtek RTD1625 SoC, featuring a per-pin register + architecture that differs significantly from earlier RTD series controll= ers. + Each GPIO has dedicated registers for configuration (direction, input/ou= tput + values, debounce), and interrupt control supporting edge and level detec= tion + modes. + +properties: + compatible: + enum: + - realtek,rtd1625-iso-gpio + - realtek,rtd1625-isom-gpio + + reg: + items: + - description: GPIO controller registers + - description: GPIO interrupt registers + + interrupts: + items: + - description: Interrupt number of the assert GPIO interrupt, which = is + triggered when there is a rising edge. + - description: Interrupt number of the deassert GPIO interrupt, whic= h is + triggered when there is a falling edge. + - description: Interrupt number of the level-sensitive GPIO interrup= t, + triggered by a configured logic level. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-ranges: true + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - gpio-ranges + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@89120 { + compatible =3D "realtek,rtd1625-isom-gpio"; + reg =3D <0x89120 0x10>, + <0x89100 0x20>; + interrupt-parent =3D <&iso_m_irq_mux>; + interrupts =3D <0>, <1>, <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&isom_pinctrl 0 0 4>; + gpio-controller; + #gpio-cells =3D <2>; + }; --=20 2.34.1