From nobody Fri Apr 3 08:38:32 2026 Received: from va-1-115.ptr.blmpb.com (va-1-115.ptr.blmpb.com [209.127.230.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3133F31715D for ; Tue, 31 Mar 2026 11:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.127.230.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774956852; cv=none; b=DvcYv/MoxtMgFDNs4LaF+7smRj8NnBxYz5lcgp1z63e+Sif3By5YsmWR3Cvt+AmFxe0h77MsPYNUk/xE1RTPh2YEfnf8ObWvDbMtlI4eaQLqy2P6vK8IWoxsZULuyLysip6IQ5rAQd2vS2Hk1YD7pNqj6WM9mKn05+o1DDHTFfA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774956852; c=relaxed/simple; bh=SnTlhugGdX0bTE/87HbhO6BksKz0DZkq52gEATDYEPY=; h=To:Date:In-Reply-To:Content-Type:Subject:Cc:From:Message-Id: References:Mime-Version; b=MLMhXL5DWYxX6pD6b7bqx2A+s/kD5btVVbVMu4Sgcy63qYkf3P9O6xdIjC+ssGhacLk4z38VtvQCfadiN+T5AZwGhdApv+HFWD0ucFvM1wsa/shS2jxOSQxnKD5DZm0ia5DVQoxnCdWcTZLc4Keur+Cb0crGT80gHNuCW7sX4QI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=XTYe2BqR; arc=none smtp.client-ip=209.127.230.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="XTYe2BqR" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1774956847; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=3e681DmNzN1rxc8H3IUAJMYq13Sjy9zXysxvUnJSINE=; b=XTYe2BqR5Abak6QdZDJC5L6FCEcZGahcXrhU/eSmxFRH8oInibDb2CUc6YGrFjnWNW3Q9I /A7426sexxV0dB6O+a60O18xGazGNCsURvy6pNFL/kDxE9ZRc6g8kzabQ1X7tH/FA03/bj CCgRP572dub3JEs2FIEEcmI4WD/W45gMFH7vgDOgevBvqDFpICxhIbQb7O+h6udvvqjTJn J3IPhczKjPJpYAVkvx5XjOgtJD5mgFwYnldncYK6xMw7SlGjHtC4QYytdhIIpS7KysJe7M q2rwqb9wj825cMPqGB74bPo2tbQW2v05pR6bSSoBkLgQJjpBvcNWzQdjkcitZw== To: , , , , , , , , , , , , Date: Tue, 31 Mar 2026 19:31:03 +0800 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20260331113103.2197007-1-zhouchuyi@bytedance.com> Subject: [PATCH v4 12/12] x86/mm: Enable preemption during flush_tlb_kernel_range X-Mailer: git-send-email 2.20.1 Cc: , "Chuyi Zhou" From: "Chuyi Zhou" Message-Id: <20260331113103.2197007-13-zhouchuyi@bytedance.com> References: <20260331113103.2197007-1-zhouchuyi@bytedance.com> X-Lms-Return-Path: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Original-From: Chuyi Zhou Content-Type: text/plain; charset="utf-8" flush_tlb_kernel_range() is invoked when kernel memory mapping changes. On x86 platforms without the INVLPGB feature enabled, we need to send IPIs to every online CPU and synchronously wait for them to complete do_kernel_range_flush(). This process can be time-consuming due to factors such as a large number of CPUs or other issues (like interrupts being disabled). flush_tlb_kernel_range() always disables preemption, this may affect the scheduling latency of other tasks on the current CPU. Previous patch converted flush_tlb_info from per-cpu variable to on-stack variable. Additionally, it's no longer necessary to explicitly disable preemption before calling smp_call*() since they internally handles the preemption logic. Now is's safe to enable preemption during flush_tlb_kernel_range(). Additionally, in get_flush_tlb_info() use raw_smp_processor_id() to avoid warnings from check_preemption_disabled(). Signed-off-by: Chuyi Zhou --- arch/x86/mm/tlb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 58c6f3d2f993..c37cc9845abc 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1394,7 +1394,7 @@ static void get_flush_tlb_info(struct flush_tlb_info = *info, info->stride_shift =3D stride_shift; info->freed_tables =3D freed_tables; info->new_tlb_gen =3D new_tlb_gen; - info->initiating_cpu =3D smp_processor_id(); + info->initiating_cpu =3D raw_smp_processor_id(); info->trim_cpumask =3D 0; } =20 @@ -1461,6 +1461,8 @@ static void invlpgb_kernel_range_flush(struct flush_t= lb_info *info) { unsigned long addr, nr; =20 + guard(preempt)(); + for (addr =3D info->start; addr < info->end; addr +=3D nr << PAGE_SHIFT) { nr =3D (info->end - addr) >> PAGE_SHIFT; =20 @@ -1505,7 +1507,6 @@ void flush_tlb_kernel_range(unsigned long start, unsi= gned long end) { struct flush_tlb_info info; =20 - guard(preempt)(); get_flush_tlb_info(&info, NULL, start, end, PAGE_SHIFT, false, TLB_GENERATION_INVALID); =20 --=20 2.20.1