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Received: from AM8PR04MB7284.eurprd04.prod.outlook.com (2603:10a6:20b:1dc::8) by DU4PR04MB12064.eurprd04.prod.outlook.com (2603:10a6:10:63f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.15; Tue, 31 Mar 2026 11:30:04 +0000 Received: from AM8PR04MB7284.eurprd04.prod.outlook.com ([fe80::9cd6:51bd:82b:98dc]) by AM8PR04MB7284.eurprd04.prod.outlook.com ([fe80::9cd6:51bd:82b:98dc%5]) with mapi id 15.20.9745.027; Tue, 31 Mar 2026 11:30:04 +0000 From: Wei Fang To: claudiu.manoil@nxp.com, vladimir.oltean@nxp.com, xiaoning.wang@nxp.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, f.fainelli@gmail.com, frank.li@nxp.com, chleroy@kernel.org, horms@kernel.org, linux@armlinux.org.uk, andrew@lunn.ch Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev Subject: [PATCH v4 net-next 13/14] net: dsa: netc: initialize buffer bool table and implement flow-control Date: Tue, 31 Mar 2026 19:30:24 +0800 Message-Id: <20260331113025.1566878-14-wei.fang@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260331113025.1566878-1-wei.fang@nxp.com> References: <20260331113025.1566878-1-wei.fang@nxp.com> Content-Type: text/plain; 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The buffer pool tracks internal memory consumption with upper bound limits and optionally a non-shared portion when associated with a shared buffer pool. Currently the shared buffer pool is not supported, it will be added in the future. For i.MX94, the switch has 4 ports and 8 buffer pools, so each port is allocated two buffer pools. For frames with priorities of 0 to 3, they will be mapped to the first buffer pool; For frames with priorities of 4 to 7, they will be mapped to the second buffer pool. Each buffer pool has a flow control on threshold and a flow control off threshold. By setting these threshold, add the flow control support to each port. Signed-off-by: Wei Fang --- drivers/net/dsa/netc/netc_main.c | 133 ++++++++++++++++++++++++++ drivers/net/dsa/netc/netc_switch.h | 9 ++ drivers/net/dsa/netc/netc_switch_hw.h | 13 +++ 3 files changed, 155 insertions(+) diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_m= ain.c index 3609d83ac363..688dceb486c2 100644 --- a/drivers/net/dsa/netc/netc_main.c +++ b/drivers/net/dsa/netc/netc_main.c @@ -379,6 +379,8 @@ static void netc_port_set_mlo(struct netc_port *np, enu= m netc_mlo mlo) =20 static void netc_port_fixed_config(struct netc_port *np) { + u32 pqnt =3D 0xffff, qth =3D 0xff00; + /* Default IPV and DR setting */ netc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE, PQOSMR_VS | PQOSMR_VE); @@ -386,6 +388,15 @@ static void netc_port_fixed_config(struct netc_port *n= p) /* Enable L2 and L3 DOS */ netc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE, PCR_L2DOSE | PCR_L3DOSE); + + /* Set the quanta value of TX PAUSE frame */ + netc_mac_port_wr(np, NETC_PM_PAUSE_QUANTA(0), pqnt); + + /* When a quanta timer counts down and reaches this value, + * the MAC sends a refresh PAUSE frame with the programmed + * full quanta value if a pause condition still exists. + */ + netc_mac_port_wr(np, NETC_PM_PAUSE_TRHESH(0), qth); } =20 static void netc_port_default_config(struct netc_port *np) @@ -617,6 +628,87 @@ static int netc_add_standalone_fdb_bcast_entry(struct = netc_switch *priv) bcast, NETC_STANDALONE_PVID); } =20 +static u32 netc_get_buffer_pool_num(struct netc_switch *priv) +{ + /* The BPCAPR register is a read only register, the hardware + * guarantees that the BPCAPR_NUM_BP field will not be 0. + */ + return netc_base_rd(&priv->regs, NETC_BPCAPR) & BPCAPR_NUM_BP; +} + +static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping) +{ + u32 pbpmcr0 =3D lower_32_bits(mapping); + u32 pbpmcr1 =3D upper_32_bits(mapping); + + netc_port_wr(np, NETC_PBPMCR0, pbpmcr0); + netc_port_wr(np, NETC_PBPMCR1, pbpmcr1); +} + +static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv) +{ + int bp_per_port =3D priv->num_bp / priv->info->num_ports; + int q =3D NETC_IPV_NUM / bp_per_port; + int r =3D NETC_IPV_NUM % bp_per_port; + int num =3D q + r; + + /* IPV-to=E2=80=93buffer-pool mapping per port: + * Each port is allocated 'bp_per_port' buffer pools and supports 8 + * IPVs, where a higher IPV indicates a higher frame priority. Each + * IPV can be mapped to only one buffer pool. + * + * The mapping rule is as follows: + * - The first 'num' IPVs share the port's first buffer pool (index + * 'base_id'). + * - After that, every 'q' IPVs share one buffer pool, with pool + * indices increasing sequentially. + */ + for (int i =3D 0; i < priv->info->num_ports; i++) { + u32 base_id =3D i * bp_per_port; + u32 bp_id =3D base_id; + u64 mapping =3D 0; + + for (int ipv =3D 0; ipv < NETC_IPV_NUM; ipv++) { + /* Update the buffer pool index */ + if (ipv >=3D num) + bp_id =3D base_id + ((ipv - num) / q) + 1; + + mapping |=3D (u64)bp_id << (ipv * 8); + } + + netc_port_set_pbpmcr(priv->ports[i], mapping); + } +} + +static int netc_switch_bpt_default_config(struct netc_switch *priv) +{ + /* priv->num_bp is read from register, based on the NETC block + * guide, its value is hardcoded to a non-zero value. And it + * is greater than the number of ports (priv->info->num_ports). + */ + priv->num_bp =3D netc_get_buffer_pool_num(priv); + priv->bpt_list =3D devm_kcalloc(priv->dev, priv->num_bp, + sizeof(struct bpt_cfge_data), + GFP_KERNEL); + if (!priv->bpt_list) + return -ENOMEM; + + /* Initialize the maximum threshold of each buffer pool entry */ + for (int i =3D 0; i < priv->num_bp; i++) { + struct bpt_cfge_data *cfge =3D &priv->bpt_list[i]; + int err; + + cfge->max_thresh =3D cpu_to_le16(NETC_BP_THRESH); + err =3D ntmp_bpt_update_entry(&priv->ntmp, i, cfge); + if (err) + return err; + } + + netc_ipv_to_buffer_pool_mapping(priv); + + return 0; +} + static int netc_setup(struct dsa_switch *ds) { struct netc_switch *priv =3D ds->priv; @@ -644,6 +736,10 @@ static int netc_setup(struct dsa_switch *ds) dsa_switch_for_each_available_port(dp, ds) netc_port_default_config(priv->ports[dp->index]); =20 + err =3D netc_switch_bpt_default_config(priv); + if (err) + goto free_lock_and_ntmp_user; + err =3D netc_add_standalone_vlan_entry(priv); if (err) goto free_lock_and_ntmp_user; @@ -1195,6 +1291,41 @@ static void netc_port_set_rmii_mii_mac(struct netc_p= ort *np, netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val); } =20 +static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause) +{ + struct netc_switch *priv =3D np->switch_priv; + int port =3D np->dp->index; + int i, j, num_bp; + + num_bp =3D priv->num_bp / priv->info->num_ports; + for (i =3D 0, j =3D port * num_bp; i < num_bp; i++, j++) { + struct bpt_cfge_data *cfge =3D &priv->bpt_list[j]; + struct bpt_cfge_data old_cfge =3D *cfge; + + if (tx_pause) { + cfge->fc_on_thresh =3D cpu_to_le16(NETC_FC_THRESH_ON); + cfge->fc_off_thresh =3D cpu_to_le16(NETC_FC_THRESH_OFF); + cfge->fccfg_sbpen =3D FIELD_PREP(BPT_FC_CFG, + BPT_FC_CFG_EN_BPFC); + cfge->fc_ports =3D cpu_to_le32(BIT(port)); + } else { + cfge->fc_on_thresh =3D cpu_to_le16(0); + cfge->fc_off_thresh =3D cpu_to_le16(0); + cfge->fccfg_sbpen =3D 0; + cfge->fc_ports =3D cpu_to_le32(0); + } + + if (ntmp_bpt_update_entry(&priv->ntmp, j, cfge)) + *cfge =3D old_cfge; + } +} + +static void netc_port_set_rx_pause(struct netc_port *np, bool rx_pause) +{ + netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_PAUSE_IGN, + rx_pause ? 0 : PM_CMD_CFG_PAUSE_IGN); +} + static void netc_port_mac_rx_enable(struct netc_port *np) { netc_port_rmw(np, NETC_POR, PCR_RXDIS, 0); @@ -1256,6 +1387,8 @@ static void netc_mac_link_up(struct phylink_config *c= onfig, interface =3D=3D PHY_INTERFACE_MODE_MII) netc_port_set_rmii_mii_mac(np, speed, duplex); =20 + netc_port_set_tx_pause(np, tx_pause); + netc_port_set_rx_pause(np, rx_pause); netc_port_mac_rx_enable(np); } =20 diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc= _switch.h index 4b229a71578e..7ebffb136b2f 100644 --- a/drivers/net/dsa/netc/netc_switch.h +++ b/drivers/net/dsa/netc/netc_switch.h @@ -32,6 +32,12 @@ =20 #define NETC_STANDALONE_PVID 0 =20 +#define NETC_IPV_NUM 8 +/* MANT =3D bits 11:4, EXP =3D bits 3:0, threshold =3D MANT * 2 ^ EXP */ +#define NETC_BP_THRESH 0x334 +#define NETC_FC_THRESH_ON 0x533 +#define NETC_FC_THRESH_OFF 0x3c3 + struct netc_switch; =20 struct netc_switch_info { @@ -90,6 +96,9 @@ struct netc_switch { struct ntmp_user ntmp; struct hlist_head fdb_list; struct mutex fdbt_lock; /* FDB table lock */ + + u32 num_bp; + struct bpt_cfge_data *bpt_list; }; =20 #define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv)) diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/n= etc_switch_hw.h index c6a0c0a8ff8a..1e1c0d279a21 100644 --- a/drivers/net/dsa/netc/netc_switch_hw.h +++ b/drivers/net/dsa/netc/netc_switch_hw.h @@ -12,6 +12,12 @@ #define NETC_SWITCH_DEVICE_ID 0xeef2 =20 /* Definition of Switch base registers */ +#define NETC_BPCAPR 0x0008 +#define BPCAPR_NUM_BP GENMASK(7, 0) + +#define NETC_PBPMCR0 0x0400 +#define NETC_PBPMCR1 0x0404 + #define NETC_CBDRMR(a) (0x0800 + (a) * 0x30) #define NETC_CBDRBAR0(a) (0x0810 + (a) * 0x30) #define NETC_CBDRBAR1(a) (0x0814 + (a) * 0x30) @@ -138,6 +144,7 @@ enum netc_stg_stage { #define NETC_PM_CMD_CFG(a) (0x1008 + (a) * 0x400) #define PM_CMD_CFG_TX_EN BIT(0) #define PM_CMD_CFG_RX_EN BIT(1) +#define PM_CMD_CFG_PAUSE_IGN BIT(8) =20 #define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400) #define PM_MAXFRAM GENMASK(15, 0) @@ -145,6 +152,12 @@ enum netc_stg_stage { #define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400) #define PM_IEVENT_RX_EMPTY BIT(6) =20 +#define NETC_PM_PAUSE_QUANTA(a) (0x1054 + (a) * 0x400) +#define PAUSE_QUANTA_PQNT GENMASK(15, 0) + +#define NETC_PM_PAUSE_TRHESH(a) (0x1064 + (a) * 0x400) +#define PAUSE_TRHESH_QTH GENMASK(15, 0) + #define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400) #define PM_IF_MODE_IFMODE GENMASK(2, 0) #define IFMODE_MII 1 --=20 2.34.1