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charset="utf-8" Add Memory Controller driver support for Tegra238 SOC, including: - MC client definitions with Tegra238-specific stream IDs - Reuse of Tegra234 ICC operations for bandwidth management via BPMP-FW - Device tree compatible string "nvidia,tegra238-mc" Export tegra234_mc_icc_ops so it can be shared with the Tegra238 MC driver, as both SoCs use the same ICC aggregation and bandwidth management logic. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 3 + drivers/memory/tegra/mc.h | 6 + drivers/memory/tegra/tegra234.c | 2 +- drivers/memory/tegra/tegra238.c | 395 ++++++++++++++++++++++++++++++++ 5 files changed, 406 insertions(+), 1 deletion(-) create mode 100644 drivers/memory/tegra/tegra238.c diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 6334601e6120..0d50e37d43af 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -10,6 +10,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D tegra210.o tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) +=3D tegra186.o tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) +=3D tegra186.o tegra194.o tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) +=3D tegra186.o tegra234.o +tegra-mc-$(CONFIG_ARCH_TEGRA_238_SOC) +=3D tegra186.o tegra238.o tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) +=3D tegra186.o tegra264.o =20 obj-$(CONFIG_TEGRA_MC) +=3D tegra-mc.o diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index d620660da331..10ef3c323e22 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -49,6 +49,9 @@ static const struct of_device_id tegra_mc_of_match[] =3D { #ifdef CONFIG_ARCH_TEGRA_234_SOC { .compatible =3D "nvidia,tegra234-mc", .data =3D &tegra234_mc_soc }, #endif +#ifdef CONFIG_ARCH_TEGRA_238_SOC + { .compatible =3D "nvidia,tegra238-mc", .data =3D &tegra238_mc_soc }, +#endif #ifdef CONFIG_ARCH_TEGRA_264_SOC { .compatible =3D "nvidia,tegra264-mc", .data =3D &tegra264_mc_soc }, #endif diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 649b54369263..d0da4a5f192d 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -238,6 +238,11 @@ extern const struct tegra_mc_soc tegra194_mc_soc; =20 #ifdef CONFIG_ARCH_TEGRA_234_SOC extern const struct tegra_mc_soc tegra234_mc_soc; +extern const struct tegra_mc_icc_ops tegra234_mc_icc_ops; +#endif + +#ifdef CONFIG_ARCH_TEGRA_238_SOC +extern const struct tegra_mc_soc tegra238_mc_soc; #endif =20 #ifdef CONFIG_ARCH_TEGRA_264_SOC @@ -256,6 +261,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops; #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ defined(CONFIG_ARCH_TEGRA_194_SOC) || \ defined(CONFIG_ARCH_TEGRA_234_SOC) || \ + defined(CONFIG_ARCH_TEGRA_238_SOC) || \ defined(CONFIG_ARCH_TEGRA_264_SOC) extern const struct tegra_mc_ops tegra186_mc_ops; #endif diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 87b22038a5fb..9fbd34d4abe0 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1125,7 +1125,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_nod= e *node, u32 *avg, u32 *pea return 0; } =20 -static const struct tegra_mc_icc_ops tegra234_mc_icc_ops =3D { +const struct tegra_mc_icc_ops tegra234_mc_icc_ops =3D { .xlate =3D tegra_mc_icc_xlate, .aggregate =3D tegra234_mc_icc_aggregate, .get_bw =3D tegra234_mc_icc_get_init_bw, diff --git a/drivers/memory/tegra/tegra238.c b/drivers/memory/tegra/tegra23= 8.c new file mode 100644 index 000000000000..5abdca16a275 --- /dev/null +++ b/drivers/memory/tegra/tegra238.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include + +#include +#include +#include +#include + +#include +#include "mc.h" + +static const struct tegra_mc_client tegra238_mc_clients[] =3D { + { + .id =3D TEGRA234_MEMORY_CLIENT_HDAR, + .name =3D "hdar", + .bpmp_id =3D TEGRA_ICC_BPMP_HDA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_HDA, + .regs =3D { + .sid =3D { + .override =3D 0xa8, + .security =3D 0xac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_HDAW, + .name =3D "hdaw", + .bpmp_id =3D TEGRA_ICC_BPMP_HDA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_HDA, + .regs =3D { + .sid =3D { + .override =3D 0x1a8, + .security =3D 0x1ac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_SDMMCRAB, + .name =3D "sdmmcrab", + .bpmp_id =3D TEGRA_ICC_BPMP_SDMMC_4, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_SDMMC4A, + .regs =3D { + .sid =3D { + .override =3D 0x318, + .security =3D 0x31c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_SDMMCWAB, + .name =3D "sdmmcwab", + .bpmp_id =3D TEGRA_ICC_BPMP_SDMMC_4, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_SDMMC4A, + .regs =3D { + .sid =3D { + .override =3D 0x338, + .security =3D 0x33c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APER, + .name =3D "aper", + .bpmp_id =3D TEGRA_ICC_BPMP_APE, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE0, + .regs =3D { + .sid =3D { + .override =3D 0x3d0, + .security =3D 0x3d4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEW, + .name =3D "apew", + .bpmp_id =3D TEGRA_ICC_BPMP_APE, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE0, + .regs =3D { + .sid =3D { + .override =3D 0x3d8, + .security =3D 0x3dc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name =3D "nvdisplayr", + .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, + .type =3D TEGRA_ICC_ISO_DISPLAY, + .sid =3D TEGRA238_SID_ISO_NVDISPLAY, + .regs =3D { + .sid =3D { + .override =3D 0x490, + .security =3D 0x494, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name =3D "nvdisplayr1", + .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, + .type =3D TEGRA_ICC_ISO_DISPLAY, + .sid =3D TEGRA238_SID_ISO_NVDISPLAY, + .regs =3D { + .sid =3D { + .override =3D 0x508, + .security =3D 0x50c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPR, + .name =3D "bpmpr", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x498, + .security =3D 0x49c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPW, + .name =3D "bpmpw", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4a0, + .security =3D 0x4a4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPDMAR, + .name =3D "bpmpdmar", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4a8, + .security =3D 0x4ac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPDMAW, + .name =3D "bpmpdmaw", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4b0, + .security =3D 0x4b4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEDMAR, + .name =3D "apedmar", + .bpmp_id =3D TEGRA_ICC_BPMP_APEDMA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE1, + .regs =3D { + .sid =3D { + .override =3D 0x4f8, + .security =3D 0x4fc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEDMAW, + .name =3D "apedmaw", + .bpmp_id =3D TEGRA_ICC_BPMP_APEDMA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE1, + .regs =3D { + .sid =3D { + .override =3D 0x500, + .security =3D 0x504, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_VICSRD, + .name =3D "vicsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_VIC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_VIC, + .regs =3D { + .sid =3D { + .override =3D 0x360, + .security =3D 0x364, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_VICSWR, + .name =3D "vicswr", + .bpmp_id =3D TEGRA_ICC_BPMP_VIC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_VIC, + .regs =3D { + .sid =3D { + .override =3D 0x368, + .security =3D 0x36c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDECSRD, + .name =3D "nvdecsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVDEC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVDEC, + .regs =3D { + .sid =3D { + .override =3D 0x3c0, + .security =3D 0x3c4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDECSWR, + .name =3D "nvdecswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVDEC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVDEC, + .regs =3D { + .sid =3D { + .override =3D 0x3c8, + .security =3D 0x3cc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVENCSRD, + .name =3D "nvencsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVENC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVENC, + .regs =3D { + .sid =3D { + .override =3D 0xe0, + .security =3D 0xe4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVENCSWR, + .name =3D "nvencswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVENC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVENC, + .regs =3D { + .sid =3D { + .override =3D 0x158, + .security =3D 0x15c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE0R, + .name =3D "pcie0r", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_0, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE0, + .regs =3D { + .sid =3D { + .override =3D 0x6c0, + .security =3D 0x6c4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE0W, + .name =3D "pcie0w", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_0, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE0, + .regs =3D { + .sid =3D { + .override =3D 0x6c8, + .security =3D 0x6cc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE1R, + .name =3D "pcie1r", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_1, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE1, + .regs =3D { + .sid =3D { + .override =3D 0x6d0, + .security =3D 0x6d4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE1W, + .name =3D "pcie1w", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_1, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE1, + .regs =3D { + .sid =3D { + .override =3D 0x6d8, + .security =3D 0x6dc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE2AR, + .name =3D "pcie2ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_2, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE2, + .regs =3D { + .sid =3D { + .override =3D 0x6e0, + .security =3D 0x6e4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE2AW, + .name =3D "pcie2aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_2, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE2, + .regs =3D { + .sid =3D { + .override =3D 0x6e8, + .security =3D 0x6ec, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE3R, + .name =3D "pcie3r", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_3, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE3, + .regs =3D { + .sid =3D { + .override =3D 0x6f0, + .security =3D 0x6f4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE3W, + .name =3D "pcie3w", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_3, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE3, + .regs =3D { + .sid =3D { + .override =3D 0x6f8, + .security =3D 0x6fc, + }, + }, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER0, + .name =3D "sw_cluster0", + .bpmp_id =3D TEGRA_ICC_BPMP_CPU_CLUSTER0, + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVL1R, + .name =3D "nvl1r", + .bpmp_id =3D TEGRA_ICC_BPMP_GPU, + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVL1W, + .name =3D "nvl1w", + .bpmp_id =3D TEGRA_ICC_BPMP_GPU, + .type =3D TEGRA_ICC_NISO, + } +}; + +static const struct tegra_mc_intmask tegra238_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOU= T | + MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + +const struct tegra_mc_soc tegra238_mc_soc =3D { + .num_clients =3D ARRAY_SIZE(tegra238_mc_clients), + .clients =3D tegra238_mc_clients, + .num_address_bits =3D 40, + .num_channels =3D 8, + .client_id_mask =3D 0x1ff, + .intmasks =3D tegra238_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra238_mc_intmasks), + .has_addr_hi_reg =3D true, + .ops =3D &tegra186_mc_ops, + .icc_ops =3D &tegra234_mc_icc_ops, + .ch_intmask =3D 0x0000ff00, + .global_intstatus_channel_shift =3D 8, + /* + * Additionally, there are lite carveouts but those are not currently + * supported. + */ + .num_carveouts =3D 32, + .regs =3D &tegra20_mc_regs, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra30_mc_irq_handlers), + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), +}; --=20 2.50.1