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Tue, 31 Mar 2026 02:54:16 -0700 (PDT) Received: from ZC-202510311500 ([123.139.39.4]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c3c747e410sm9668962eec.25.2026.03.31.02.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 02:54:15 -0700 (PDT) From: Haoyu Lu To: Tudor Ambarus Cc: Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Haoyu Lu Subject: [PATCH v3] mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA Date: Tue, 31 Mar 2026 17:53:51 +0800 Message-ID: <20260331095354.1861-1-hechushiguitu666@gmail.com> X-Mailer: git-send-email 2.53.0.windows.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT35XU02GCBA flash device does not support chip erase according to its datasheet, but supports die erase. The existing code had a TODO comment noting that the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs to be enabled and the driver implementation needs to be converted to use die erase. This patch enables the SPI_NOR_IO_MODE_EN_VOLATILE flag and adds the mt35_two_die_fixups to the MT35XU02GCBA entry, which includes the micron_st_nor_two_die_late_init() function that sets up die erase support. With these changes, the flash device can properly use die erase operations instead of chip erase. Signed-off-by: Haoyu Lu --- v3: Squash v1 and v2 into a single patch based on spi-nor/next as requested v2: Remove TODO comment and rename mt35xu01gbba_fixups to mt35_two_die_fixu= ps per review. drivers/mtd/spi-nor/micron-st.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 88033384a71e..c22d62545391 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -188,7 +188,7 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = =3D { .post_sfdp =3D mt35xu512aba_post_sfdp_fixup, }; -static const struct spi_nor_fixups mt35xu01gbba_fixups =3D { +static const struct spi_nor_fixups mt35_two_die_fixups =3D { .post_sfdp =3D mt35xu512aba_post_sfdp_fixup, .late_init =3D micron_st_nor_two_die_late_init, }; @@ -205,7 +205,7 @@ static const struct flash_info micron_nor_parts[] =3D { .id =3D SNOR_ID(0x2c, 0x5b, 0x1b), .mfr_flags =3D USE_FSR, .fixup_flags =3D SPI_NOR_IO_MODE_EN_VOLATILE, - .fixups =3D &mt35xu01gbba_fixups, + .fixups =3D &mt35_two_die_fixups, }, { /* * The MT35XU02GCBA flash device does not support chip erase, @@ -215,7 +215,6 @@ static const struct flash_info micron_nor_parts[] =3D { * MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE flag probably * needs to be enabled. * - * TODO: Fix these and test on real hardware. */ .id =3D SNOR_ID(0x2c, 0x5b, 0x1c), .name =3D "mt35xu02g", @@ -223,7 +223,8 @@ static const struct flash_info micron_nor_parts[] =3D { .no_sfdp_flags =3D SECT_4K | SPI_NOR_OCTAL_READ, .mfr_flags =3D USE_FSR, - .fixup_flags =3D SPI_NOR_4B_OPCODES, + .fixup_flags =3D SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE, + .fixups =3D &mt35_two_die_fixups, }, }; -- 2.53.0.windows.1