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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c8a1de559csm189692eec.22.2026.03.31.02.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 02:02:25 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Krzysztof Kozlowski , Manivannan Sadhasivam , Mrinmay Sarkar , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH] arm64: dts: qcom: lemans: Move PCIe devices into soc node Date: Tue, 31 Mar 2026 17:01:47 +0800 Message-ID: <20260331090147.18522-1-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Gb0aXAXL c=1 sm=1 tr=0 ts=69cb8da4 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=rs7BxoZ7CQHKALr8RUwA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: LWy1H2EkTs5r6ytbLsJB_1y2AT8rRykK X-Proofpoint-ORIG-GUID: LWy1H2EkTs5r6ytbLsJB_1y2AT8rRykK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzMxMDA4NSBTYWx0ZWRfXwvWJDzJ9Jghn Au3nYg9qLP/1XNoEWlMI5sT8cugMaoODEha5X5DXFnORhJw4t/eGs46djRz+7G0TvqanVKQvBzs 2Xrhklis2ZOuZnD3MKQJpkrvWUCOZFBGUSXhjxxGqdMOUeu7+JKYHv2oMAkmFs1besQrETl6tdH M7XPLuB4/FM74k4PY115319ir5eAA8ns16t43n79yy+EXB9cSja7Ck4MQ6NQjY/pbGe3oymR1EU DnJDoNw/YWOD9GlJBOTGXKzyXvig/SvV3J2jrd0GCSlUZ5FuxZN8Jd6M13Iy4Ng3GP8I0o8OdRI 9uk8dD5CAfM+/DRVICoRzgjcsLeJottqOx/xp+Bdh7T2OWSePGB9/yolvnjZYro+igIkeyHIQQr wezFYuT3s8Ik5R772Hn7qGJU/v1+mottaJHc1TXRaFNoScOUXBogLEyobKEhkhTOaUayEkzhnTz V/ijluGuAil0oMOk3hQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-31_02,2026-03-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603310085 Content-Type: text/plain; charset="utf-8" These PCIe devices with MMIO address should be inside soc node rather than outside. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio --- This is compile tested only! arch/arm64/boot/dts/qcom/lemans.dtsi | 692 +++++++++++++-------------- 1 file changed, 346 insertions(+), 346 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index f565067bda31..03a712d82d78 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2694,6 +2694,352 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + pcie0: pcie@1c00000 { + compatible =3D "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type =3D "pci"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + + status =3D "disabled"; + + pcieport0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible =3D "qcom,sa8775p-pcie-ep"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts =3D , + , + ; + + interrupt-names =3D "global", "doorbell", "dma"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus =3D <&pcie_smmu 0x0000 0x7f>; + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_0_GDSC>; + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + num-lanes =3D <2>; + linux,pci-domain =3D <0>; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x1c04000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1: pcie@1c10000 { + compatible =3D "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type =3D "pci"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + num-lanes =3D <4>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible =3D "qcom,sa8775p-pcie-ep"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts =3D , + , + ; + + interrupt-names =3D "global", "doorbell", "dma"; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus =3D <&pcie_smmu 0x80 0x7f>; + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_1_GDSC>; + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + num-lanes =3D <4>; + linux,pci-domain =3D <1>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg =3D <0x0 0x1c14000 0x0 0x4000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; @@ -8601,350 +8947,4 @@ turing_llm_tpdm_out: endpoint { }; }; }; - - pcie0: pcie@1c00000 { - compatible =3D "qcom,pcie-sa8775p"; - reg =3D <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01c03000 0x0 0x1000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type =3D "pci"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - bus-range =3D <0x00 0xff>; - - dma-coherent; - - linux,pci-domain =3D <0>; - num-lanes =3D <2>; - - interrupts =3D , - , - , - , - , - , - , - , - ; - interrupt-names =3D "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; - - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; - assigned-clock-rates =3D <19200000>; - - interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; - - resets =3D <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; - reset-names =3D "pci", - "link_down"; - - power-domains =3D <&gcc PCIE_0_GDSC>; - - phys =3D <&pcie0_phy>; - phy-names =3D "pciephy"; - - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; - eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; - - status =3D "disabled"; - - pcieport0: pcie@0 { - device_type =3D "pci"; - reg =3D <0x0 0x0 0x0 0x0 0x0>; - bus-range =3D <0x01 0xff>; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - }; - }; - - pcie0_ep: pcie-ep@1c00000 { - compatible =3D "qcom,sa8775p-pcie-ep"; - reg =3D <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf20>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x4000>, - <0x0 0x40200000 0x0 0x1fe00000>, - <0x0 0x01c03000 0x0 0x1000>, - <0x0 0x40005000 0x0 0x2000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts =3D , - , - ; - - interrupt-names =3D "global", "doorbell", "dma"; - - interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus =3D <&pcie_smmu 0x0000 0x7f>; - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_0_GDSC>; - phys =3D <&pcie0_phy>; - phy-names =3D "pciephy"; - num-lanes =3D <2>; - linux,pci-domain =3D <0>; - - status =3D "disabled"; - }; - - pcie0_phy: phy@1c04000 { - compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; - reg =3D <0x0 0x1c04000 0x0 0x2000>; - - clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates =3D <100000000>; - - resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names =3D "phy"; - - #clock-cells =3D <0>; - clock-output-names =3D "pcie_0_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - pcie1: pcie@1c10000 { - compatible =3D "qcom,pcie-sa8775p"; - reg =3D <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60100000 0x0 0x100000>, - <0x0 0x01c13000 0x0 0x1000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; - device_type =3D "pci"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; - bus-range =3D <0x00 0xff>; - - dma-coherent; - - linux,pci-domain =3D <1>; - num-lanes =3D <4>; - - interrupts =3D , - , - , - , - , - , - , - , - ; - interrupt-names =3D "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates =3D <19200000>; - - interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; - - resets =3D <&gcc GCC_PCIE_1_BCR>, - <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names =3D "pci", - "link_down"; - - power-domains =3D <&gcc PCIE_1_GDSC>; - - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; - eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; - - status =3D "disabled"; - - pcie@0 { - device_type =3D "pci"; - reg =3D <0x0 0x0 0x0 0x0 0x0>; - bus-range =3D <0x01 0xff>; - - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; - }; - }; - - pcie1_ep: pcie-ep@1c10000 { - compatible =3D "qcom,sa8775p-pcie-ep"; - reg =3D <0x0 0x01c10000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf20>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x4000>, - <0x0 0x60200000 0x0 0x1fe00000>, - <0x0 0x01c13000 0x0 0x1000>, - <0x0 0x60005000 0x0 0x2000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", - "mmio", "dma"; - - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; - - clock-names =3D "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; - - interrupts =3D , - , - ; - - interrupt-names =3D "global", "doorbell", "dma"; - - interconnects =3D <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; - interconnect-names =3D "pcie-mem", "cpu-pcie"; - - dma-coherent; - iommus =3D <&pcie_smmu 0x80 0x7f>; - resets =3D <&gcc GCC_PCIE_1_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_1_GDSC>; - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - num-lanes =3D <4>; - linux,pci-domain =3D <1>; - - status =3D "disabled"; - }; - - pcie1_phy: phy@1c14000 { - compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; - reg =3D <0x0 0x1c14000 0x0 0x4000>; - - clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates =3D <100000000>; - - resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names =3D "phy"; - - #clock-cells =3D <0>; - clock-output-names =3D "pcie_1_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; }; --=20 2.43.0