From nobody Thu Apr 2 02:40:40 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8FEF366DA5 for ; Tue, 31 Mar 2026 02:15:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774923331; cv=none; b=NJx8MCde3iNUqtOT9iOtOynARl5i+Y8BinSV7esHUcLCGe8uxzbGw9au+md9V4x9tURSP3aVZWO+MnfsdMpSxTcY1ASmk/afLwWoFLUV9XhF2w/2ZdhoZRznaA17wg8R7nEaoF6usveYXbgwMD3Yl+XoH2JFv0TXEcjAADNaSA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774923331; c=relaxed/simple; bh=8jYbdlHHDRN/ZXZosS7i9KR7L3WkD3vpxCBE6MNpgLg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nDVIa7+KW6n6EhJTUWRNMUEVYInE0zQO3sJ/HLLYd4puEImS8vx7wblZGWiByBXis19lHcrY+Xky8DtPL8wVN8uuVUqF/j9ei3Hj8a3Sv9e1gjQkz8y6BW8d1WHAesZkUrxSxHO4Jc8ty9r+BZT5peFWVD/xfSVOMEqr5v8/h0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gaSpggwv; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gaSpggwv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774923330; x=1806459330; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8jYbdlHHDRN/ZXZosS7i9KR7L3WkD3vpxCBE6MNpgLg=; b=gaSpggwvxItJ6UUyM7BzCYbjVz8a0p3Ht/1331nHXuf7qwnWJTurPp9J /WnTIkyAMao4ezsdCjDSdIA8H+wPO2dRy0takIXHHc+PuNxZDgwzcd/65 BkhS8xHZfYYz3JnfvxNqVgcE0f9hygCOdwN10S6xEL++x3BHQCkjbHvli k0ZGSs1Hv2pxsSAuWIKLkOirh6r9XzEX6lBzWbrI33tWTxuKDOHT4Tr+P ry1QEkoDqZ6CVPs7bybRo2YcBQ9Wped/0NRYX+okGAEQ+eejGoBR0IRIf zauTipgrl/QYIEjoKS0Ia/7XXOPnUXs24UI0BZvH4tw/ZlVu/jh5XGmnW g==; X-CSE-ConnectionGUID: 36WKEGxWQeeo96Xo9tB/pA== X-CSE-MsgGUID: NJa4QR4hQOKmdiJj84i7FA== X-IronPort-AV: E=McAfee;i="6800,10657,11744"; a="93508151" X-IronPort-AV: E=Sophos;i="6.23,151,1770624000"; d="scan'208";a="93508151" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2026 19:07:52 -0700 X-CSE-ConnectionGUID: 1WP/eizETq2pJT/Zr/LijQ== X-CSE-MsgGUID: JrtncTTbRUqWJX45vx60hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,151,1770624000"; d="scan'208";a="221358712" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa006.fm.intel.com with ESMTP; 30 Mar 2026 19:07:48 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH v2 08/11] x86/microcode: Distinguish NMI control path on stop-machine callback Date: Tue, 31 Mar 2026 01:42:46 +0000 Message-ID: <20260331014251.86353-9-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260331014251.86353-1-chang.seok.bae@intel.com> References: <20260331014251.86353-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" load_cpus_stopped() currently centralizes the stop_machine() callback for both NMI and NMI-less rendezvous. microcode_update_handler() alone is enough for the latter. While the NMI-based rendezvous finally reaches the same update handler, it requires additional logic to trigger and process NMIs. That machinery will be replaced by stop-machine facility. As preparation for that conversion, split the callback path to make NMI-specific steps explicit and clear. Rename the function to align with the change. Signed-off-by: Chang S. Bae --- V1 -> V2: Rename load_cpus_stopped() (Thomas) --- arch/x86/kernel/cpu/microcode/core.c | 30 ++++++++++++---------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 651202e6fefb..abd640b1d286 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -532,7 +532,7 @@ void noinstr microcode_offline_nmi_handler(void) wait_for_ctrl(); } =20 -static noinstr bool microcode_update_handler(void) +static noinstr int microcode_update_handler(void *unused) { unsigned int cpu =3D raw_smp_processor_id(); =20 @@ -548,7 +548,7 @@ static noinstr bool microcode_update_handler(void) touch_nmi_watchdog(); instrumentation_end(); =20 - return true; + return 0; } =20 /* @@ -569,19 +569,15 @@ bool noinstr microcode_nmi_handler(void) return false; =20 raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(); + return microcode_update_handler(NULL) =3D=3D 0; } =20 -static int load_cpus_stopped(void *unused) +static int stop_cpu_in_nmi(void *unused) { - if (microcode_ops->use_nmi) { - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - } else { - /* Just invoke the handler directly */ - microcode_update_handler(); - } + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + return 0; } =20 @@ -618,13 +614,13 @@ static int load_late_stop_cpus(bool is_safe) */ store_cpu_caps(&prev_info); =20 - if (microcode_ops->use_nmi) + if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - - stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); - - if (microcode_ops->use_nmi) + stop_machine_cpuslocked(stop_cpu_in_nmi, NULL, cpu_online_mask); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + } else { + stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); + } =20 /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { --=20 2.51.0